JPH06309242A - Error detecting method - Google Patents

Abstract

PURPOSE:To ensure the validity of data by detecting efficiently a dynamic error generated at the time of writing the data in a nonvolatile memory. CONSTITUTION:In the error detecting method for adding a checksum 12c to data 12b and storing them in a nonvolatile memory 12, and detecting an error of the data 12b at the time of read-out, this method is constituted of a first step for storing a prescribed certification code 12a in the nonvolatile memory 12 together with the data 12b in the case the data 12b is stored normally in the nonvolatile memory 12, at the time of storing the data 12b in the nonvolatile memory 12, and a second step for deciding that the data 12b is an error without using the checksum 12c in the case the certification code 12a does not exist at the time of reading out the data 12b.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error detecting method for detecting an error in information, and more particularly to an error detecting method using a storage means such as a non-volatile memory.

[0002]

2. Description of the Related Art Conventionally, a read-only memory (ROM) has been used as a storage means for storing information such as a program. However, since a rewritable nonvolatile memory was announced, a part of the ROM is nonvolatile. It is often replaced with a memory to have a memory structure that gives flexibility to a program.

For example, when the version of the ROM program is upgraded or a bug is corrected, the ROM itself is not replaced, but the correction data is made resident in the non-volatile memory, and the program is corrected using the data. In the system (hereinafter, referred to as “program patch correction”), the above memory configuration is adopted.

Therefore, when a data error occurs in the non-volatile memory, a program error is caused, and it is necessary to take sufficient memory protection measures.

FIG. 12 is a conceptual diagram of patch correction of a program using a non-volatile memory in the conventional method.

As shown in FIG. 12, when the patch of the program is corrected, the program in the ROM is first loaded on the main memory (RAM) (12-1). And
The patch correction data is read from the non-volatile memory in which the patch correction data is stored in advance, and the patch is corrected at a predetermined position of the program (12-2).

In this patch correction method, for example, as disclosed in Japanese Patent Laid-Open No. 2-114330, a correction memory area is provided in a non-volatile memory, and a program is created based on the data in the correction memory. A program storage method of a device-embedded microprocessor to be modified, or a program for patch modification of a program on a main memory using a nonvolatile memory device having an unused area as disclosed in Japanese Patent Laid-Open No. 3-98126 There is a patch correction method.

However, since the non-volatile memory has a drawback that the number of times of writing is usually limited to about 10,000 times, if the number of times of writing reaches the upper limit, an information error occurs and a program error or runaway occurs. There is an inherent factor that causes it.

Therefore, in order to detect such an error in the information at an early stage and prevent a program error or the like in advance, it is general to take a memory protection measure by using hardware and software.

As a protection measure by the hardware, there is a system in which the hardware has redundancy such as multiple storage of programs, and as a protection measure by the software, redundancy is made by using, for example, a cyclic code. There is a method of detecting an error occurring in a memory by storing a program to which a code is added and performing decoding using a redundant code when reading the program.

[0011]

However, when the hardware is provided with redundancy, the additional hardware is required as the redundancy is added so that, for example, a program multiple storage memory is required. Becomes

In addition, in the error detection method using the cyclic code or the like, the error generated in the memory can be detected, but the error generated when writing in the memory cannot be detected.

For example, in the patch correction of the above program, if the power supply is stopped while the patch correction data is being updated, the processing is stopped without completing the update processing. For this reason, the patch correction data results in a part of the data being updated but not the rest.

That is, although the error detection method alone can detect an error when a bit error occurs in the non-volatile memory due to aging or the like, the error cannot be detected when an error occurs during writing as described above. Of.

Therefore, the present invention provides an error detecting method which eliminates such a problem, efficiently detects an error occurring when writing information in a storage means, and can guarantee the correctness of the information. The purpose is to do.

[0016]

In order to achieve the above object, the present invention provides an error detection method for adding an error detection code to information, storing it in a storage means, and detecting an error in the information at the time of reading. When storing the information, a first step (S4-1 to S4-3 in FIG. 4) of storing a predetermined character string different from the character string pattern at the time of erasing the information together with the information, A second step of detecting an error in the information by determining whether the character string read from the storage unit is the predetermined character string when reading the information
And steps (S6-4 to S6-7 in FIG. 6) are included.

[0017]

According to the present invention, when the information is stored in the storage means, a predetermined character string (for example, a keyword) different from the character string pattern when the information is erased is stored in the storage means together with the information in the first step. When storing and reading the information from the storage means in the second step, for example, a predetermined character string area is read before reading the information, and the character string of the area is the predetermined character string used in the first step. If the information matches with the character string, the information is normal, and if the information does not match, it is determined that the information is incorrect, so that the error of the information generated when the information is written in the storage unit can be efficiently read out. Since it can be detected, it is possible to detect an error that cannot be detected by the error detecting code and guarantee the validity of the information stored in the storage means.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the error detection method according to the present invention is applied to patch correction of a program using a non-volatile memory will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a system configuration required for patch correction of a program using a nonvolatile memory according to the present invention.

This system includes a CPU 11 for executing programs and error detection processing, and patch correction data 1.
2b, an authentication code 12a, a checksum 12c, a non-volatile memory 12 and a main memory RAM1
3, a ROM 14 storing an original program to be program-patched, an I / O 15 and a system bus 16.

At this time, the nonvolatile memory 12 is the CPU 1
In order to speed up the reading and writing of data from No. 1, the reading and writing of data is performed using the address of the memory.

The authentication code 12a is the data 12
It is an arbitrary character string that determines whether or not there is an error (hereinafter referred to as "dynamic error") that occurs due to the erase and write operations performed when updating b. It is stored in a predetermined position within 12. As the authentication code 12a, it is necessary to select a character string different from the initial value at power-on (for example, all "0" or all "F").

The authentication code 12a is stored in the nonvolatile memory 12 together with the data 12b when the data 12b is written.
If the authentication code 12a is in a predetermined position of the non-volatile memory 12 at the time of writing and reading, the data 12b
Is normally written without causing a write error, and if the authentication code 12a is not present, it serves as a status flag indicating that the data 12b was not normally written.

The checksum 12c is a calculated value for determining whether or not there is an error (hereinafter referred to as "static error") that occurs even if the non-volatile memory 12 is not written / updated. Yes, this method is used for error checking of internet packets in the Xerox network system (hereinafter referred to as "XNS").

The checksum 12c is inspection data calculated by adding the data inside the nonvolatile memory 12 excluding the checksum 12c itself.

When the present invention is applied to patch modification,
The authentication code 12a is used to detect a dynamic error in the data 12b, and the checksum 12c is used to detect a static error in the data 12b.

Next, an error detection procedure using the authentication code 12a and the checksum 12c will be described.

FIG. 2 is a diagram showing the configuration of the non-volatile memory 12 and the order of erasing and writing of each component.

In FIG. 2, the non-volatile memory 12 has an authentication code 12a composed of, for example, the characters "AAA".
And the data 12b consisting of d1 to dn and the authentication code 1
2a and the addition result of d1 to dn (hereinafter, "add (12
a. ． checksum 12 obtained from dn) ”)
and c. The authentication code 12a and the checksum 12c can be stored in any location in the non-volatile memory 12.

When updating the patch correction data 12b in the non-volatile memory 12 having the above configuration, first, the authentication code 12a, the checksum 12c, and the data 12b are erased in this order. After the erasing is completed, the data 12b, the authentication code 12a, and the checksum 12c are written in the nonvolatile memory 12 in this order.

In this way, the authentication code 12a is erased before the data 12b is erased, and the authentication code 12a is written after the data 12b is written.
If a exists in the nonvolatile memory 12, the data 12b always exists in the nonvolatile memory 12.

Therefore, by adopting the above-mentioned erasing order and writing order, the CPU 11 confirms the authentication code 12a before patch correction, and the authentication code 12a
Is "AAA", it is determined that the data 12b is legitimate data and patch correction is performed. If the authentication code 12a is erased, it is determined that the data is being updated and patch correction is stopped. You can

In addition, for example, when the power supply is stopped at the time when the authentication code 12a, the checksum 12c, and a part of the data 12b are erased, when the processing is completed without updating the data 12b, Since the CPU 11 can confirm that the authentication code 12a is in the erased state, the patch correction can be stopped.

That is, the authentication code 12a can be used as an error-detectable status flag by using the erasing order and the writing order.

The erasing process and the writing process will be described in detail below with reference to the flowcharts shown in FIGS. 3 and 4.

FIG. 3 is a flow chart showing the erasing process of the non-volatile memory 12.

First, before erasing the data 12b, the authentication code 12a "AAA" in the non-volatile memory 12 is erased (S3-1). At this time, in this embodiment, the authentication code 1
In order to confirm that 2a has been erased normally, a method of replacing the authentication code 12a with a space and erasing is used.

Therefore, the authentication code 12a is "AAA".
The character string indicates that the data 12b has been written, and the space indicates that the data 12b has been erased. Further, when it is “0”, it means that the writing is incomplete, and when it is other than “AAA”, space and “0”, it can be recognized that a data error has occurred in the authentication code 12a.

After erasing the authentication code 12a,
Checksum 12c (add (12a ... dn)) (S
3-2) and the data 12b (data 1 to n) are erased (S3-3). At this time, in this embodiment, the authentication code 12a
The checksum 12c is used to determine the status using only
The data 12b is erased by using "0".

Next, a writing procedure for the nonvolatile memory 12 will be described with reference to the flowchart shown in FIG.

First, the data 12b is written in a predetermined area in the non-volatile memory 12 (S4-1). Therefore, if a failure such as a power failure occurs at this point, the writing of the authentication code 12a has not been completed.
The data 12b is considered to be being updated (or a failure occurrence state).

Therefore, in order to reduce the time taken, the authentication code 12a is written after the data 12b (S4-2).

Finally, each data of the authentication code 12a and the data 12b is added to calculate the checksum, and the calculation result is stored in a predetermined position of the non-volatile memory 12 (S4-3).

By using the erasing order and the writing order, the patch correction data 1 is stored in the nonvolatile memory 12.
When 2b is stored, the occurrence of a dynamic error such as a write error can be detected by using the authentication code 12a.

Next, an error detection procedure using the checksum 12c in the non-volatile memory 12 will be described by taking a system using an exclusive OR (hereinafter referred to as "EOR") for each bit as an example.

As shown in FIG. 5, when two-digit hexadecimal data is stored in the authentication code 12a and the data 12b, first, the MSB (most significant bi) of each data is stored.
Take the EOR of t) and determine the MSB of the checksum 12c. And LSB (least significant bit)
Up to the above, the above calculation is repeated for each bit to calculate a checksum, and the checksum is stored in the nonvolatile memory 12.

Before the CPU 11 corrects the patch, the checksum is calculated again by the above procedure, and if the calculation result matches the content of the checksum 12c calculated at the time of storage, the data 12b has no error. Otherwise, it is determined that the data 12b has an error.

In the example of FIG. 5, the authentication code 12a is the character '
Since it is A ', the corresponding character code "hexadecimal 41
(Hereinafter, referred to as “41 (H)”) is stored.
The data 12b is "74 (H)", "65 (H)", "DE".
(H) "and" A6 (H) ", so" 28 (H) "is obtained by EORing the above data bit by bit.
Is stored in the non-volatile memory 12 as a checksum 12c at the writing stage shown in S4-3.

Then, when the CPU 11 reads the data 12b for patch correction, the checksum is calculated again by the same procedure and collated with the checksum 12c.

As a result, it is assumed that the data 12b is "74".
When the MSB of (H) ”causes a bit error and changes to“ F4 (H) ”, the checksum calculation result is“ A8.
(H) ”, so the value of checksum 12c is“ 28 (H) ”
The bit error can be detected in comparison with.

By performing the above processing, it is possible to detect whether or not a static error such as aging has occurred in a part of the nonvolatile memory 12.

Further, in this embodiment, EOR is used for convenience of explanation.
Although the method is used, other checksum methods such as a method using addition on a finite field and a parity check method can also be applied.

Next, a series of procedures for patch correction of the program using the authentication code 12a and the checksum 12c will be described with reference to the flowchart shown in FIG.

First, if the user turns on the power (S
6-1), the CPU 11 starts the system according to the data in the ROM 14 (S6-2). Then, the CPU 11 causes the RA
After erasing the contents of M13 (S6-3), the authentication code 12a in the non-volatile memory 12 is read (S6-4).

Then, it is judged whether or not the content of the read authentication code 12a matches the preset character string "AAA" (S6-5). If they do not match, the ROM 14 is not corrected without patch correction. Execute the program (S
6-10), if they match, calculate checksum (S6-
Go to 6).

Then, after calculating the checksum (S6-
6) It is determined whether the calculation result matches the content of the checksum 12c in the nonvolatile memory 12 (S6-7),
If they do not match, the program in the ROM 14 is executed without patch correction (S6-10), and if they match, the process proceeds to patch correction processing (S6-8).

That is, the CPU 11 loads the program in the ROM 14 onto the RAM 13 and then performs patch correction to sequentially store the data 12b in the nonvolatile memory 12 at a predetermined position in the RAM 13.

Then, the CPU 11 executes the program on the RAM 13 after the patch correction is completed (S6-9).

When an error is detected in the non-volatile memory 12 by performing the patch correction process according to the above procedure,
If the program in the ROM 14 is executed without patch correction and no error is detected, the program after patch correction can be executed.

By the way, since EOR is used in the above embodiment, the same column of the data 12b (for example, MS
B or LSB), checksum 12c
The values of may coincide by chance. Therefore, in order to deal with such a case, an embodiment in which the nonvolatile memory 12 is divided and used will be described with reference to FIGS. 7 to 9.

FIG. 7 is a diagram showing a configuration in which the nonvolatile memory 12 is divided into blocks and the data 12b is stored in each block.

As shown in FIG. 7, in this embodiment, an authentication code and a checksum are added to each divided block.

For this reason, the authentication code 7a and the checksum 7c are given to the block 1, and the authentication code and the checksum are similarly given to the other blocks. Here, the erasing order and the writing order of the non-volatile memory 12 are the same as in the previous example.

A processing procedure for patch correction of a program using the nonvolatile memory 12 divided into the above blocks will be described below.

FIG. 8 is a flowchart showing a processing procedure for patch correction only when no error occurs in all blocks.

In such a case, the block 1 is first subjected to error detection (S8-1) using the authentication code 7a and the checksum 7c. Here, the procedure for error detection for each block is the same as in the previous example. If the error detection result for block 1 is normal,
The process moves to the error detection process for the next block (S8-2). If an error is detected, the error detection process thereafter is stopped and R
The OM program is executed (S8-5). And so on
Error detection is successively performed using the authentication code and checksum for each block, and patch correction (S8-3) is performed only when there is no error in all blocks, and the corrected program is executed.

That is, in this processing procedure, if all the blocks are correct, the patch is corrected, but if there is at least one erroneous block, the procedure of executing the ROM program without correcting the patch is taken. This is useful when blocks depend on each other.

On the other hand, FIG. 9 is a flow chart showing the processing procedure in the case of sequentially patch-correcting only blocks having no error.

In this case, first, error detection is similarly performed on block 1 (S9-1), and if there is no abnormality in the error detection result of block 1, patch correction is performed (S9-2).
After that, the process proceeds to the error detection of the next block (S9-3). If an error is detected in the block 1, the patch detection is not performed and the process proceeds to the error detection process for the next block.
Similarly, the procedure is to perform error detection using the authentication code and checksum for all blocks, exclude the block in which the error is detected, correct the patch, and then execute the program.

That is, in this processing procedure, the patch correction of each block is performed irrespective of other blocks. Therefore, this processing procedure is effective when the blocks are independent of each other.

In addition to the above processing procedure, error detection and patch correction are sequentially performed until an error is detected. When an error is detected, the program being corrected is discarded and the ROM program is executed. There is also a processing procedure in which the above processing procedures are combined.

As described above, the data 12b for patch correction is divided into blocks in advance, and the error detection using the authentication code and the checksum is performed for each block to improve the accuracy of the error detection. The reliability of can be increased.

Next, application examples of the present invention to a multiprocessor system will be described with reference to FIGS.

FIG. 10 shows a system configuration example in which a plurality of CPUs share a non-volatile memory.

The system shown in FIG. 10 has three CPUs.
(CPU 11a, CPU 11b, CPU 11c), non-volatile memory 12 divided into blocks for sharing memory with a multiprocessor, RAM 13, and ROM
14, an I / O 15 and a system bus 16.

At this time, as a method of sharing the non-volatile memory 12, there are a method of fixedly allocating each block for each CPU and a method of appropriately allocating a necessary block to each CPU as needed. However, in the former case, the processing procedure is the same as that in the first embodiment, so the latter processing procedure in which each block is dynamically allocated to each CPU will be described here.

FIG. 11 is a flow chart showing the procedure for patch correction in the system having the above configuration.

At the time when the erasing of the RAM is completed, each CPU confirms whether or not the block in the non-volatile memory is the block allocated to itself (S11-1), and if it is the block allocated to the CPU. For example, block error detection is performed using the authentication code and checksum (S11-2),
If it is not assigned, the process moves to the next block (S11-4).

In the error detection of S11-2, if there is no error, the patch is corrected (S11-3), but if the error is detected, the patch correction is stopped and the program of the ROM 14 is executed ( S11-6).

As long as there are remaining blocks (S11
-4) The above processing (S11-1 to 11-3) is repeated, and if there is no error in all blocks, the program after patch correction is executed (S11-5).

That is, this processing procedure is a processing procedure in the case of dynamically allocating each block to the multiprocessor, and there is a possibility that an error will occur in writing as the number of times of writing to the nonvolatile memory increases. Is effective because it increases.

As described above, in the case of using the non-volatile memory, the non-volatile memory divided into blocks, and the non-volatile memory fluidly allocated for the multiprocessor, as a means for detecting a dynamic error at the time of writing, The procedure using the authentication code according to the invention and the checksum as the static error detection method has been described.

At this time, in the error detection method according to the present invention, an error detection code (error correction code) typified by a cyclic code can be applied in addition to the checksum described above. Will be described below.

The cyclic code forms a redundant code by performing matrix calculation of a generator matrix and data based on a primitive rule polynomial, and error detection (correction) is performed by matrix calculation of the inverse matrix of the generator matrix and the redundant code. Since it is a method of performing the above, unlike the checksum described above, a redundant bit is added to each data itself.

Therefore, unlike the erasing / writing procedure using the checksum, the erasing procedure is in the order of the authentication code 12a and the data 12b, and the writing procedure is the data 12b,
If the authentication codes 12a are arranged in this order, the same effect as the previous example can be obtained.

Therefore, in this erase / write sequence,
By performing the same processing as that in each of the above embodiments, not only error detection but also an error correction function can be added.

As described above, in this embodiment, in addition to the patch correction data, the authentication code and the checksum are added and stored in the nonvolatile memory, and whether the authentication code matches the predetermined character string at the time of reading. While judging whether or not
Only when the patch correction data is statically erroneous due to secular change, etc., by performing error detection by determining whether the calculated checksum value matches the checksum value stored in the non-volatile memory. In addition, since it is possible to detect the presence or absence of data error even with a dynamic error associated with data update, it is possible to guarantee the correctness of the program after patch correction.

At this time, the patch correction data is divided into blocks, and error detection using an authentication code and a checksum is performed for each block to further improve error detection accuracy and improve program reliability. You can also let it.

Also, when the non-volatile memory is shared by the multiprocessors, the validity of the data in the non-volatile memory can be guaranteed.

Furthermore, by using a cyclic code or the like instead of the checksum, not only error detection but also an error correction function can be added.

In addition, the error detection method according to the present invention is not limited to the non-volatile memory, but the RA is backed up by the power supply.
It can also be applied to storage means such as M.

In this embodiment, since the error detection method according to the present invention is applied to the patch correction of the program, the patch correction data in the non-volatile memory is the error detection target. Can also be applied to.

[0093]

As described above in detail, in the present invention, when storing information in the storage means, when the information is normally stored in the storage means, the predetermined character string is stored together with the information. In the case where the character string does not exist when the information is stored in the means, and the information is judged to be an error without using the error detection code, not only when the information is statically erroneous. , It is possible to detect information error even when a dynamic error occurs,
There is an advantage that the defect of the error detection code can be corrected and the validity of the information can be guaranteed.

At this time, there is an advantage that error detection accuracy can be improved by dividing the information into blocks and performing error detection.

[Brief description of drawings]

FIG. 1 is a block diagram showing a system configuration required when applying an error detection method according to the present invention to patch correction of a program using a nonvolatile memory.

FIG. 2 is a diagram showing a configuration of the nonvolatile memory shown in FIG. 1 and an erasing / writing sequence of each component.

FIG. 3 is a flowchart showing an erasing process of the nonvolatile memory shown in FIG.

FIG. 4 is a flowchart showing a writing process of the nonvolatile memory shown in FIG.

FIG. 5 is a diagram showing an example of a checksum calculation method.

FIG. 6 is a flowchart showing a patch correction processing procedure according to the present invention.

FIG. 7 is a diagram showing an erase and write order when the nonvolatile memory shown in FIG. 1 is divided and used.

8 is a flowchart showing an example of a processing procedure when the nonvolatile memory shown in FIG. 7 is used.

9 is a flowchart showing another processing procedure when the nonvolatile memory shown in FIG. 7 is used.

FIG. 10 is a diagram showing a system configuration when a nonvolatile memory is shared by multiple processors.

11 is a flowchart showing a patch correction processing procedure when the system configuration shown in FIG. 10 is adopted.

FIG. 12 is a conceptual diagram showing a conventional procedure for patch correction for a program.

[Explanation of symbols]

11 CPU, 12 non-volatile memory, 12a authentication code, 12b patch correction data, 12c checksum, 13 RAM, 14 ROM, 15
I / 0, 16 system bus

Claims (1)

[Claims] 1. An error detection method for adding an error detection code to information, storing the information in a storage means, and detecting an error in the information at the time of reading, in the storage of the information, a character at the time of erasing the information together with the information. A first step of storing a predetermined character string different from the row pattern in the storage means; and, when reading the information, determining whether or not the character string read from the storage means is the predetermined character string. And a second step of detecting an error in the information.