JPH0389482U - - Google Patents

Description

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.
2 is a timing chart for writing to the memory in FIG. 1, FIG. 3 is a timing chart for reading from the memory in FIG. 1, FIG. 4 is a block diagram of a conventional device, and FIG. FIG. 6 is a block diagram of a portion of a case where a field memory is used, FIG. 6 is a timing chart for writing to the memory in FIG. 5, and FIG. 7 is a timing chart for reading from the memory in FIG. 2... Frame memory writing circuit, 3... Frame memory reading and liquid crystal display circuit, FF3
...Third flip-flop (write control means), FF4...Fourth flip-flop (read control means), 31...Selector (read control means), 41, 42...Field memory (frame memory).

Claims (1)

[Scope of utility model registration request] In a liquid crystal display device in which a CRT display drive signal from a personal computer or the like is processed into liquid crystal display data by a liquid crystal display drive means and displayed on a liquid crystal display unit, a data signal corresponding to one screen of the CRT display device is divided. at least two frame memories of the same capacity for storage, and a CRT.
A data writing means for adding a writing address to the frame memory to the display data signal and writing it to the frame memory, and a writing clock whose period of the write clock signal from the data writing means is multiplied by the number of the frame memories. write control means for sequentially inputting write data from the write means into each of the frame memories in a time-sharing manner; a data read means for reading data from each frame memory; 1. A liquid crystal display device comprising: readout control means for controlling input timing of readout data from each of the frame memories to the data readout means using a readout clock multiplied by the number of frame memories.