JPH04331981A - Liquid crystal display device - Google Patents

Abstract

PURPOSE:To make a liquid crystal display based upon image data for a CRT display without requiring any mass-storage image data memory. CONSTITUTION:The image data for the CRT display are inputted in sequence through a serial/parallel conversion part 11 and while only effective image data except vertical blanking periods and horizontal blanking periods are written in a dual-port memory 12 corresponding to the write timing signal WCL from a timing signal generation part 13, the effective image data written in the dual- port memory 12 are read out corresponding to a read timing signal RCL corresponding to the LCD display timing from a timing signal generation part 12, and transferred to and displayed on a liquid crystal display device 16.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device used as a display section of a personal computer, a personal word processor, etc.

0002

[Prior Art] Generally, in data processing devices such as personal computers, in order to make the device smaller and lighter,
A display unit equipped with a liquid crystal display (LCD) has been put into practical use.

[0003] In a data processing device equipped with such a liquid crystal display device, in order to ensure compatibility with equipment equipped with a CRT display device, processing of display data is first performed using a CRT display device.
Create an image signal for T display, and convert this CRT image signal to L.
This is done by converting into an image signal for CD display.

[0004] That is, the image signal for CRT display and the LC
Since the data output timing differs from the image signal for D display due to differences in the presence or absence of blanking period, etc., all the image signals for CRT display are written to memory once, and then
Only the necessary image parts, that is, valid display data, are displayed on the LCD.
It is read out according to the display timing.

[0005]

However, operating the liquid crystal display device in the manner described above requires a large capacity image memory to store all of the image signals for CRT display.

[0006] The present invention has been made in view of the above problems.
CR without the need for large-capacity image data memory
An object of the present invention is to provide a liquid crystal display device that can perform liquid crystal display based on image data for T display.

[0007]

[Means for Solving the Problems] That is, a liquid crystal display device according to the present invention comprises: a storage means capable of simultaneously performing a data write operation and a data read operation; an input means into which image data for CRT display is input; The CR based on the vertical synchronization signal and horizontal synchronization signal of the image data for CRT display.
effective image data retrieval means for storing in the storage means only valid data excluding at least the vertical retrace period of image data for T display; The display control means is configured to include display control means for reading data in accordance with the display timing of the display device.

[0008]

[Operation] That is, the image data for CRT display is sequentially written into the storage means except for the vertical retrace period, and at the same time, the image data for CRT display written in this storage means is written at the liquid crystal display timing. By sequentially reading and displaying the information according to the information, the capacity of the storage means can be significantly reduced.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of a display control circuit in a liquid crystal display device. In the figure, 11 is a serial/
12 is a dual port memory, 13 is a timing signal generator, 14 is a write column address counter, 15 is a read column address counter, and 16 is a liquid crystal display device.

The serial/parallel converter 11 inputs image data for CRT display as serial data dot by dot in accordance with the dot timing signal DCL generated by the timing signal generator 13. The CRT image data from the serial/parallel converter 11 is sequentially written into the dual port memory 12 in accordance with the write timing signal WCL generated by the timing signal generator 13. .

In this case, the write column address of the data column corresponding to one CRT horizontal scan for the dual port memory 12 is a write column that is counted in accordance with the horizontal write signal HW generated by the timing signal generator 13. It is specified by the address counter 14.

On the other hand, the CRT image data sequentially written into the dual port memory 12 is processed by the timing signal generator 1.
The LCD image data read out from the dual port memory 13 is sequentially sent to the liquid crystal display section 16 and displayed.

In this case, the readout address of the data string corresponding to one horizontal scan of the LCD from the dual port memory 12 is a readout column that is counted in accordance with the horizontal readout signal HR generated by the timing signal generator 13. It is specified by the address counter 15.

Here, the write timing signal WCL, horizontal write signal HW, read timing signal RCL, and horizontal read signal HR generated by the timing signal generator 13 are all synchronized with the horizontal synchronization signal HCRT and vertical synchronization signal for CRT display. Generated based on signal VCRT.

FIG. 2 shows the internal configuration of the timing signal generator 13 in the display control circuit, and the horizontal synchronizing signal HCRT for CRT display is generated by the AND gate AND1.
It is supplied as its counter clock C to the l+n-ary counter 21 via the AND gate AND2, and at the same time, it is supplied as its counter clock C to the m-ary counter 22 via the AND gate AND2.

Here, the horizontal synchronizing signal HCRT is supplied to the m-ary counter 22 via the AND gate AND2.
is the write column address counter 14 in FIG.
is outputted to the write column address counter 14 as a horizontal write signal HW for counting.

[0018] Also, a vertical synchronizing signal VCR for CRT display
T is the above-mentioned l+n-ary counter 21 and m-ary counter 2
2 as its reset signal R, and is also supplied as its set signal S to flip-flop FF1. The Q output of this flip-flop FF1 is supplied to the AND gate AND1 as its gate control signal.

Here, the count value of the l+n-ary counter 21 is set corresponding to the number of horizontal scanning lines corresponding to the vertical retrace period of image data for CRT display. counter carry carry
is the reset signal R to the flip-flop FF1.
It is also supplied to the flip-flop FF2 as its set signal S.

The Q output of this flip-flop FF2 is supplied to the AND gate AND2 as its gate control signal, and is also supplied to the HR signal generator 23, the write timing signal generator 24, and the read timing signal generator 2.
5 as its enable signal ES.

The count value of the m-ary counter 22 is set corresponding to the number of horizontal scanning lines corresponding to the effective image data excluding the vertical retrace period of image data for CRT display. The counter carry Carry from the counter 22 is supplied to the flip-flop FF2 as its reset signal R.

In other words, the flip-flop FF2 is CR
It is set corresponding to a period in which valid image data is obtained excluding the vertical retrace period of image data for T display, and an enable signal is sent to the HR signal generation section 23, write timing signal generation section 24, and read timing signal generation section 25, respectively. The horizontal read signal HR generated by the HR signal generator 23 is output to the read column address counter 15 in FIG. 1 as a signal for causing the read column address counter 15 to perform a counting operation, and The dot timing signal DCL and the write timing signal WCL generated by the timing signal generator 24 are signals for causing the serial/parallel converter 11 in FIG. The read timing signal RCL is output as a signal and is also generated by the read timing signal generator 25.
is output as a signal for causing the dual port memory 12 to perform a read operation.

FIG. 3 shows a vertical synchronizing signal VCR for CRT display.
3 is a timing chart showing the relationship between the horizontal write signal HW from the timing signal generator 13 and the horizontal read signal HR with respect to the horizontal synchronization signal HCRT and the horizontal synchronization signal HCRT. FIG. 4 is a diagram showing the entire CRT display image data area for one time, including the vertical and horizontal retrace periods.

Here, if the vertical synchronizing signal frequency for CRT display is VCRT (Hz) and the total number of horizontal scanning lines of image data for CRT display is (l+n+m), then the horizontal synchronizing signal frequency for CRT display is HCRT (Hz). ) is HCRT
(Hz) =VCRT(Hz) ・(l+n+m)
...Equation 1 is obtained. Here, if the number of horizontal scanning lines for LCD display is m, the horizontal synchronizing signal frequency HL for LCD display is
CD (Hz) is expressed as follows: HLCD (Hz) = VCRT (Hz) m...Formula 2. Next, the LCD of the display control circuit with the above configuration
The display operation will be explained.

First, when the vertical synchronizing signal VCRT of the image data for CRT display is generated, the l+n-ary counter 21 and the m-ary counter 2 in the timing signal generating section 13
2 are reset, and the flip-flop F
F1 is set and the AND gate AND1 is controlled to be gate-on.

Then, the horizontal synchronizing signal HC for CRT display
RT causes the l+n-base counter 21 to perform a counting operation, and after the vertical retrace period of CRT display image data has elapsed, the counter 21 carries out the count.
When is output, the flip-flop FF1 is reset and the AND gate AND1 is controlled to be gate-off, and at the same time, the flip-flop FF2 is set and the AND gate AND2 is controlled to be gate-on. Then, the HR signal generator 23, write timing signal generator 24, and read timing signal generator 25 are all enabled.

Then, the write timing signal generator 25
Writing of valid image data for CRT display into the dual port memory 12 via the serial/parallel converter 11 is started in response to the dot timing signal DCL and the write timing signal WCL from. Further, the m-adic counter 22 performs a counting operation in response to the CRT display horizontal synchronizing signal HCRT, and the write column address counter 14 performs a counting operation in response to the horizontal write signal HW, thereby updating the write column address of the dual port memory 12. As a result, the dual port memory 12 has C.
Only valid image data for RT display is written sequentially.

On the other hand, a read timing signal RCL corresponding to the display timing of the liquid crystal display device 16 is generated from the read timing signal generating section 25 and applied to the dual port memory 12. Further, a horizontal read signal HR is generated from the HR signal generating section 23 and applied to the read column address counter 15.

Then, the effective image data for CRT display written in the dual port memory 12 is read out one horizontal scanning column at a time in accordance with the LCD display timing and sent to the liquid crystal display device 16. ,CR
The image data for T display is converted into image data for LCD display, and is output for display on the liquid crystal display device 16.

In this case, as is clear from equations 1 and 2 above, "VCRT
(Hz) ・(l+n+m)" CR written at horizontal synchronizing signal frequency HCRT (Hz) for CRT display
The effective image data for T display is converted to “VCRT (Hz) m
Horizontal synchronizing signal frequency for LCD display consisting of HLCD
(Hz), the capacity value of the dual port memory 12 only needs to be able to store image data corresponding to the number of (l+n) horizontal scanning lines.

Note that invalid image data corresponding to the horizontal retrace period is also removed in the dual port memory 12 by the same means as for writing only valid data excluding the vertical retrace period of image data for CRT display. Configure.

Therefore, according to the display control circuit in the liquid crystal display device having the above configuration, the image data for CRT display that is sequentially input through the serial/parallel converter 11 is converted to the write timing signal WCL from the timing signal generator 13. Accordingly, only valid image data excluding the vertical retrace period and horizontal retrace period is stored in the dual port memory 12.
At the same time, the effective image data written in the dual port memory 12 is read out in accordance with the read timing signal RCL corresponding to the LCD display timing from the timing signal generator 13, and the effective image data is read out from the liquid crystal display device 16.
Since it is configured so that it is transferred and displayed on the C
It becomes possible to perform liquid crystal display based on image data for RT display.

[0033]

As described above, according to the present invention, there is provided a storage means capable of simultaneously performing a data write operation and a data read operation, an input means into which image data for CRT display is input, and an input means for inputting image data for CRT display. effective image data retrieving means for storing in the storage means only valid data excluding at least the vertical retrace period of the CRT display image data based on a data vertical synchronization signal and a horizontal synchronization signal; Since the display control means reads out the effective image data stored in the storage means in accordance with the display timing of the liquid crystal display device, it is possible to use the CRT display without requiring a large capacity image data memory. It becomes possible to perform liquid crystal display based on the image data.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a display control circuit in a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing the internal configuration of a timing signal generation section in the display control circuit.

FIG. 3 is a timing chart showing the relationship between a horizontal write signal HW and a horizontal read signal HR from a timing signal generator with respect to a vertical synchronizing signal VCRT and a horizontal synchronizing signal HCRT for CRT display.

[Figure 4] Complete CR for one time including vertical and horizontal retrace periods
The figure which shows the image data area for T display.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 11... Serial/parallel converter, 12... Dual port memory, 13... Timing signal generator, 14... Write column address counter, 15... Read column address counter, 16... Liquid crystal display device, 21... L+n-ary counter, 22
...m-ary counter, 23...HR signal generation section, 24...write timing signal generation section, 25...read timing signal generation section, AND1, AND2...AND gate, FF1,
FF2...Flip-flop.

Claims (1)

[Claims] 1. In a liquid crystal display device, a storage means capable of simultaneously performing a data write operation and a data read operation;
An input means into which image data for CRT display is input, and based on a vertical synchronization signal and a horizontal synchronization signal of the image data for CRT display, only valid data excluding at least the vertical retrace period of the image data for CRT display are inputted. The image data retrieval means includes effective image data retrieval means for storing the effective image data in the storage means, and display control means for reading out the effective image data stored in the storage means by the effective image data retrieval means in accordance with the display timing of the liquid crystal display device. A liquid crystal display device characterized by: