JPS5958471A - Character display - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a character display device such as a CRT display device.

-a, in a CRT display device, the CRT controller controls the video RAM (e.g. refresh RAM).
Read the display data from M) and send it to the 081 screen,
When displaying a character pattern, the video RAM is accessed under the control of the CPU and display data is stored in the video RAM.
If the video RAM is loaded for 1 time, flickering will occur on the 081 screen, and the video RAM cannot be accessed from the CPU during that time. Therefore, conventionally, the CPU accesses the video RAM during times when no display is being performed on the 081 screen (horizontal and vertical retrace periods). For this reason, the time during which the CPU can access the video RAM is reduced, resulting in disadvantages in that screen display takes time and CPU waiting time increases.

This invention was made against the background of the above-mentioned circumstances, and its purpose is to write display data to RAM and read display data from RAM to display character pattern data. In,
To provide a character display device which lengthens the time during which RAM can be accessed when writing display data to RAM.

Hereinafter, the present invention will be specifically described based on an embodiment shown in the drawings. FIG. 1 is a block circuit diagram showing the main parts of a CRT display device according to this embodiment.
The CPU, which controls various operations, inputs and stores display data sent from a keypad (not shown), a display address indicating the display position of this data, and the like. Therefore, the display data and display address outputted from the CPU1>) are sent to the four multiplexers M1.
~Video RAM2-1~2 corresponding to this via M4
-4 respectively. Bidet: # RAM 2-1~2
-4 is, for example, a dynamic memory that uses refresh II AM in which the same data is rewritten, and CR' by each video RAM 2-1 to 2-4.
1" The display data for one screen is stored in multiple blocks, each of which can be accessed independently.Then, the output data (display address) of each video is decoded by a decoder. 3 to multiplexer M1
By outputting the signals m1 to m4 sequentially specifying . Ru.

The display data read from each video RAM 2-1 to 2-4 is output as address data to the character generator 4, and
The display data of 1 to 2-4 is sent to C via gate circuit G1.
Loaded into PUI.

The character generator 4 permanently stores character pattern data, and is stored in each bidet and tRAM 2-1 to 2-4.
The character pattern data corresponding to the display data from the synchronizing signal generating circuit 5 is output according to the address data from the synchronizing signal generating circuit 5. This character pattern data (parallel data) is further converted into corresponding serial data by a parallel-to-serial wrinkle conversion circuit 6, and is sent and displayed on a CRT screen as a video signal VD. In this case, the parallel-to-serial conversion circuit 6 outputs the video signal VD in accordance with the rotary lock RC output from the synchronization signal generation circuit 5 for each character display and the shift clock SC output for each dot display. The synchronizing signal generating circuit 5 also outputs a horizontal synchronizing signal H8 and a vertical synchronizing signal VS to the CRT. Furthermore, the synchronization signal generation circuit 5
inputs the clock signal AD to the counter 72.

This black AD is a signal that is output every time the CRT screen is scanned 174 times, and is counted by the quaternary counter 7.

This quaternary counter 7 changes its value to "1", "2", "3", "4", "l", etc. every time the clock AD is input.
This count value data is read into the CPUI via the gate circuit G2, and together with the address data output from the synchronization signal generation circuit 5,
The data is input as address data to each multiplexer M1 to M4, respectively. In this case, the count value data of the quaternary counter 7 is stored in the video RAM corresponding to its contents rlJ~"4".
This is address data that sequentially specifies 2-1 to 2-4.

Next, the operation of the above embodiment will be explained. After the display data and display address are set, the CPUI executes a write operation for one display data according to the flowchart of FIG. 2. First, in step S1, the R A MN currently accessed by the synchronization signal generation circuit 5 is
O, that is, read out the RAM number being displayed. In this case, the content rlJ ~ "4" of the quaternary counter 7 is the video RA
Since it is associated with M2-1 to M2-2-4, open the gate circuit G and read the count value data of the quaternary counter 7 to check which RAM content is being displayed. be able to. Subsequently, in step 7'S, it is checked whether the display address of the display data in the CPU is a prohibited address I or not. In this case, the prohibited address I is
These addresses are prohibited from being written to the video RAMs 2-1 to 2-4, and are defined as shown in FIG. That is, FIG. 3 shows the relationship between the count value of the quaternary counter 7 and the prohibited address area.
2-4 start address as AI, A2, As, A4
For example, the count value of the quaternary counter 7 is "
1”, A, ≦”<A3, and “2”,
It is defined as A2 <I'< A4, and the count value is "1".
” for video RAM 2-1.2-2, “2” for video RAM 2-2.2-3, and so on.
Among -1 to 2-4, the prohibited addresses are from the top address to the last address of the RAM next to the RAM being displayed.

Therefore, it is determined in step S2 that the address is a prohibited address.
If so, the process returns to step S1 and waits until the prohibited address has passed. When the prohibited address has passed, step S2
Proceed to step S.

Here, of each video RAM 2-1 to 2-4, the CPU
The process of writing display data to the display address of RAM accessed from I is executed. Therefore, writing of display data to each of the video RAMs 2-1 to 2-4 is prohibited for the RAM currently being displayed and the next RAM, but is not executed for the RAM that will be sequentially accessed next. Ru. When writing of the display data is completed, the process advances to the next step S4, and it is checked whether the display data is END. As a result, if it is not END, the process proceeds to the next step S, and the display address is updated. Subsequently, the process proceeds to step S6, and as a result of updating the display address, it is checked whether the display address has become the start address Al % A2, A3, A4 of each of the video RAMs 2-1 to 2-4. That is, in step S6, when the last address of one video RAM is updated to the first address of the next RAM, the display address may become a prohibited address.In such a case, the process returns to step S1 and the display address is updated. This is executed to check again whether the address is a prohibited address. If the result of step S6 is "NO", the process returns to step S3 and the display data writing operation is continued. Then,
Since the display data is END and 7, “YES” is selected in step S4.
If it is determined to be J, the display data writing operation ends. In such a data write operation, the CPU
1 cannot write display data to the video RAMs 2-1 to 2-4, the video RAM currently being displayed is
and the time required to specify the next RAM.

As a result, video RAM 2-1 to 2-
4 can be accessed for a longer time.

Note that the operation for reading display data from the video RAMs 2-1 to 2-4 is performed in the same manner as the above-mentioned write operation, so the explanation of the operation in this case will be omitted.

Further, it is assumed that the time used for the display data writing process shown in FIG. 2 is shorter than the time for displaying all of one video RAM. Furthermore, the number of divisions of the video RAM is
It can be set as appropriate depending on the time used for writing and the time used for display. Furthermore, the invention is not limited to application to CRTs, but can also be applied to dot matrix display devices using liquid crystals.

As described above in detail, the character display device according to the present invention stores display data for one screen divided into a plurality of blocks, and is provided with a plurality of RAMs each of which can be accessed independently. The time during which each RAMG can be accessed for writing or reading data can be made longer than in the prior art, without affecting the display screen. For this reason, the CPU
Waiting time can be shortened and high-speed data processing is possible.

[Brief explanation of drawings]

The drawings show an embodiment of the present invention, FIG. 1 is a block circuit diagram showing the main parts of a CRT display device to which the invention is applied, FIG. 2 is a flowchart explaining the data writing operation, and FIG. FIG. 2 is a diagram showing the relationship between the count value of the quaternary counter shown in FIG. 1 and the prohibited address area. ■...CPU, 2-1 to 2-4...R
AM, 5...Synchronization signal generation circuit, 7...
- Quaternary counter. Patent applicant: Casio Computer Co., Ltd. Figure 2, side 1, Figure 3

Claims (1)

[Claims] A plurality of RAMs each of which stores the display data of each block among the display data for one screen consisting of a plurality of blocks and can be accessed independently; A character display device comprising: display control means for reading and displaying; and a CPU for accessing RAMs other than those being read by the display control means among the RAMs.