JPH02123631U - - Google Patents
Info
- Publication number
- JPH02123631U JPH02123631U JP3018989U JP3018989U JPH02123631U JP H02123631 U JPH02123631 U JP H02123631U JP 3018989 U JP3018989 U JP 3018989U JP 3018989 U JP3018989 U JP 3018989U JP H02123631 U JPH02123631 U JP H02123631U
- Authority
- JP
- Japan
- Prior art keywords
- parity
- storage area
- data
- writing
- write
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000013500 data storage Methods 0.000 claims description 5
- 230000010365 information processing Effects 0.000 claims description 5
- 238000007689 inspection Methods 0.000 claims description 4
- 238000012986 modification Methods 0.000 claims description 3
- 230000004048 modification Effects 0.000 claims description 3
- 238000012360 testing method Methods 0.000 claims 4
- 230000000295 complement effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Detection And Correction Of Errors (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Description
第１図は本考案にかかる情報処理装置の一実施
例の構成図、第２図は第１図の装置の動作説明図
、第３図は本考案にかかる情報処理装置の他の実
施例の構成図、第４図は第３図の装置の動作説明
図である。
１……中央処理装置、１１……アドレス修飾信
号線、２……主記憶装置、２１……記憶部、２１
１……データ用記憶領域、２１２……パリテイ用
記憶領域、２２……パリテイ生成検査手段、２３
……パリテイデータ選択手段、２４……書き込み
制御手段。
FIG. 1 is a configuration diagram of one embodiment of the information processing device according to the present invention, FIG. 2 is an explanatory diagram of the operation of the device in FIG. 1, and FIG. 3 is a diagram showing another embodiment of the information processing device according to the present invention. The configuration diagram, FIG. 4, is an explanatory diagram of the operation of the apparatus shown in FIG. 3. DESCRIPTION OF SYMBOLS 1...Central processing unit, 11...Address modification signal line, 2...Main storage device, 21...Storage unit, 21
1... Data storage area, 212... Parity storage area, 22... Parity generation/inspection means, 23
. . . Parity data selection means, 24 . . . Writing control means.
Claims (1)
イを付加し、情報を読み出すときにそのパリテイ
を検査することにより主記憶装置を故障診断する
パリテイ生成検査手段を有する情報処理装置にお
いて、 データ用記憶領域とパリテイ用記憶領域を有す
る記憶部と、 前記主記憶装置への書き込みサイクルで、その
サイクルが、前記データ用記憶領域とパリテイ用
記憶領域の両方に対して書き込みを行う通常の書
き込みサイクルであるか、パリテイ用記憶領域だ
けへの書き込みサイクルであるかを指定するアド
レス修飾信号を発生する中央処理装置と、 前記パリテイ用記憶領域への書き込みデータと
して、パリテイ用記憶領域だけへの書き込みが指
定されている場合は中央処理装置から出力される
データの一部を選択し、それ以外の場合は前記パ
リテイ生成検査手段により生成されたパリテイを
選択するパリテイデータ選択手段と、 パリテイ用記憶領域だけへの書き込みが指定さ
れている場合は、前記パリテイデータ選択手段が
選択したパリテイデータをパリテイ用記憶領域へ
書き込み、それ以外の場合は、パリテイデータ選
択手段の選択したデータと中央処理装置からの書
き込みデータをそれぞれパリテイ用記憶領域とデ
ータ用記憶領域に書き込む書き込み制御手段、 を具備し、検査用データを前記データ用記憶領
域とパリテイ用記憶領域に書き込み、この検査用
データのパリテイを補数に書き直し、書き直した
検査用データを前記パリテイ生成検査手段に与え
、パリテイエラーの発生の有無によつてパリテイ
生成検査手段を故障診断することを特徴とする情
報処理装置。 (2) 前記書き込み制御手段として、パリテイ用
記憶領域への書き込み信号の通過を前記アドレス
修飾信号によつて制御するアンドゲートを用いた
ことを特徴とする請求項(1)の情報処理装置。[Claims for Utility Model Registration] (1) It has a parity generation/testing means for diagnosing failures of the main storage device by adding parity when writing information to the main storage device and checking the parity when reading the information. In an information processing device, a storage unit having a data storage area and a parity storage area, and a write cycle to the main storage device, the cycle writes to both the data storage area and the parity storage area. a central processing unit that generates an address modification signal that specifies whether it is a normal write cycle to perform a write cycle or a write cycle only to a parity storage area; parity data selection means for selecting a part of the data output from the central processing unit when writing only to the area is specified; otherwise for selecting the parity generated by the parity generation and inspection means; and, if writing only to the parity storage area is specified, the parity data selected by the parity data selection means is written to the parity storage area; otherwise, the parity data selection means writes the parity data selected by the parity data selection means to the parity storage area; write control means for writing selected data and write data from the central processing unit into a parity storage area and a data storage area, respectively; writing test data into the data storage area and parity storage area; An information processing device characterized in that the parity of the test data is rewritten as a complement, the rewritten test data is given to the parity generation and inspection means, and the parity generation and inspection means is diagnosed for failure based on whether or not a parity error occurs. . (2) The information processing apparatus according to claim 1, wherein the write control means uses an AND gate that controls passage of a write signal to the parity storage area by the address modification signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3018989U JPH02123631U (en) | 1989-03-16 | 1989-03-16 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3018989U JPH02123631U (en) | 1989-03-16 | 1989-03-16 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02123631U true JPH02123631U (en) | 1990-10-11 |
Family
ID=31255035
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3018989U Pending JPH02123631U (en) | 1989-03-16 | 1989-03-16 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02123631U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05327522A (en) * | 1992-05-14 | 1993-12-10 | Nec Corp | Data storage circuit |
| JP2008112224A (en) * | 2006-10-27 | 2008-05-15 | Fujitsu Ten Ltd | Error detection device and error detection method |
-
1989
- 1989-03-16 JP JP3018989U patent/JPH02123631U/ja active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05327522A (en) * | 1992-05-14 | 1993-12-10 | Nec Corp | Data storage circuit |
| JP2008112224A (en) * | 2006-10-27 | 2008-05-15 | Fujitsu Ten Ltd | Error detection device and error detection method |
| JP4652308B2 (en) * | 2006-10-27 | 2011-03-16 | 富士通テン株式会社 | Error detection system and error detection method |
| US8122316B2 (en) | 2006-10-27 | 2012-02-21 | Fujitsu Ten Limited | Error detector and error detection method |
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