JP2001256120A - Evaluation system for storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform evaluation between a storage control part and a storage part before a device is completed and to eliminate the need of a dedicated tester since a test between the storage control part and the storage part can not be performed until the device or the dedicated tester is completed and man-hour is required for dedicated tester development including debugging or the like. SOLUTION: The storage control part is provided with a control circuit for switching a normal logic part and storage part evaluation logic. Test data for electric system evaluation and storage part control are performed by setting enable signals, activation signals and mode signals from the outside. A dip switch or the like is used for setting. In this test system, since the control of an operation/non-operation for storage part evaluation, addresses and data are easily supplied by using the dip switch or the like, the need of activation from the higher order of the storage device is eliminated. Thus, the test is performed in the environment of only the storage device and the need of the dedicated tester is eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage device evaluation method for realizing an electrical system evaluation in a storage device used in a computer system at a package single level.

[0002]

2. Description of the Related Art A conventional test method is disclosed in Japanese Patent Laid-Open No. 4-153.
As described in Japanese Patent Application Publication No. 852, a method of connecting a storage device under test and a tester device and supplying a test control signal and a data signal from the tester device to the storage device under test to perform a test is common. is there. Further, in order to test the storage device under test, it is necessary to create a test program. As described above, in order to test the storage device under test, it is necessary to develop and create a dedicated tester.

[0003]

In the conventional test method as described above, the test between the storage control unit and the storage unit cannot be performed until the device or the dedicated tester is completed. Also, developing a dedicated tester requires a lot of man-hours, including debugging.

In the present invention, the evaluation between the storage control unit and the storage unit is performed before the completion of the device. The purpose is not to require a dedicated tester.

[0005]

The storage control unit has a control circuit for switching between a normal logic unit and a storage unit evaluation logic. Test data and memory control for electrical system evaluation are performed by externally setting an enable signal, a start signal, and a mode signal. The setting uses a dip switch or the like.

[0006] Further, it has a function of checking write data from the storage control unit and read data from the storage unit.

[0007]

Embodiments of the present invention will be described below in detail with reference to FIG. FIG. 1 is a block diagram illustrating an embodiment of the present invention. An evaluation storage control signal generator 6 that generates an evaluation storage control signal, a write data generator 7 that generates evaluation write data 14, and a data compare that compares read data read from the storage unit 2 with expected values. An evaluation function control unit 5 composed of a unit 8, an evaluation write data 14 generated by the write data generation unit 7,
A write data selector 3 for selecting the write data 9 to be written into the storage unit 2 during normal operation and the evaluation write data 14 generated by the write data generation unit 7, and a storage control signal during normal operation to control the storage unit 2 The storage control unit 1 includes a storage control signal selector 4 for selecting the storage control signal 11 generated by the evaluation storage control signal generation unit 11 and the evaluation storage control signal 15, and the storage unit 2.

First, the storage device evaluation function in the storage control unit 1 is enabled by supplying the enable signal 12 at the time of executing the storage device evaluation, and switching to the normal logic is performed. When the storage device evaluation function is enabled, the evaluation function control unit 5 starts the activation signal 1
3 and the mode signal 18, first, instructs the evaluation storage control signal generator 6 to issue an evaluation storage control signal 15 for writing data to the storage unit 2, and outputs the write data generator 7. To generate the evaluation write data 14. The write data pattern and address are selected by the mode signal 18. Here, the storage control signal 11 and the evaluation storage control signal 15 are stored in, for example, the storage unit 2.
The storage element used for the synchronous DRAM (SDR)
AM), RAS, CAS, WE, CS, DQM,
CLK and CKE, and it is assumed that a control signal corresponding to a storage element to be used is supplied. The write data for evaluation 14 generated by the write data generator 7 is sent to the write data selector 3 for selecting the write data for evaluation 14 by the enable signal 12 when the storage device evaluation function is enabled, and the storage control signal generator for evaluation is used. The evaluation storage control signal 15 generated in step 6 is sent to the storage control signal selector 4 for selecting the evaluation storage control signal 15 by the enable signal 12 when the storage device evaluation function is enabled. Write data 14 is written to the storage unit 2 via the data bus 17. The above is the data write operation.

Next, the evaluation storage signal generation unit 6
An evaluation storage control signal 15 for reading data written in the storage device is issued, and when the storage device evaluation function is enabled, the storage signal is sent to the storage control signal selector 4 for selecting the evaluation storage control signal 15 by the enable signal 12. Memory control signal 1
5, the data is read from the storage unit 2 to the storage control unit 1 via the data bus 17. The above is the data read operation.

Next, the read data read from the storage unit 2 is fetched by the evaluation function control unit 5, and the write data for evaluation 14 generated by the write data generation unit 7 written into the storage unit 2 by the data write operation, and The data is sent to the data compare unit 8 for comparison with the same data. When the expected write data 14 and the read data do not match, the data compare unit 8 issues a compare error signal 16 to notify the data corruption to the outside.

The storage device evaluation is performed by repeating the data write operation, the data read operation, and the data compare described above.

FIG. 2 is a time chart showing an embodiment of the present invention. The evaluation storage control signal 15 describes a command form when an SDRAM is used as an element of the storage unit 2.
In the write operation, the evaluation storage control signal 15 includes an active command (ACT) 19 and a write command (WC) 20.
Write the evaluation write data 14 sent to the data bus 17 to the storage unit 2. In the read operation, the evaluation storage control signal 15 includes an ACT 21 and a read command (RC) 22, and takes out data in the storage unit 2 to the data bus 17. The read data is transferred to the data compare unit 8 and compared with the comparison write data 23. When the data does not match, the compare error signal 1 is output.
Send out 6.

[0013]

As described above, according to the present invention,
Without using a dedicated tester, it is possible to evaluate the storage device with a simple setting of only the enable signal 12, the start signal 13, and the mode signal 18 while enabling easy switching to the normal logic.

Further, the data can be checked by the data comparing section 8 which compares the write data with the read data.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an embodiment of the present invention.

FIG. 2 is a time chart illustrating an embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Storage control part, 2 ... Storage part, 3 ... Write data selector, 4 ... Storage control signal selector, 5 ... Evaluation function control part,
6 ... Evaluation storage control signal generator, 7 ... Write data generator, 8 ... Data compare unit, 9 ... Write data, 10 ...
Read data, 11: storage control signal, 12: enable signal, 13: activation signal, 14: write data for evaluation, 1
5 ... Evaluation storage control signal 16 ... Compare error signal
17 Data bus, 18 Mode signal, 19 Active command, 20 Write command, 21 Active command, 22 Read command, data for comparison.

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Susumu Tsuneda, Inventor: 1 Horiyamashita, Hadano-shi, Kanagawa F-term (reference), Enterprise Server Division, Hitachi Ltd. 5B018 GA03 HA01 HA31 JA12 JA24 NA01 NA02 PA03 QA13 RA11 5B048 AA19 CC02 DD05 FF01

Claims (2)

[Claims] In a storage device equipped with a storage control unit and a storage unit, the storage control unit has a normal logic unit and a storage unit evaluation logic, and is provided with a control circuit for switching between the former and the latter. A storage device evaluation method, wherein an electrical system between a storage control unit and a storage unit can be evaluated without using a dedicated tester. 2. The storage device evaluation method according to claim 1, wherein
It has a logical function to check the write data from the storage control unit to the storage unit and the read data from the storage unit to the storage control unit, and it is possible to guarantee the logical coincidence between the write data and the read data for performing the electrical system evaluation. Storage device evaluation method.