JP2581788Y2 - Test apparatus for semiconductor memory having redundant circuit - Google Patents

Description

[Detailed description of the invention]

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory test apparatus having a redundant circuit, and more particularly to a semiconductor memory test apparatus having a buffer memory for transferring and storing fail information stored in a fail memory.

[0002]

2. Description of the Related Art A conventional example of a test apparatus for a semiconductor memory having a redundant circuit will be described with reference to FIG. Reference numeral 1 denotes a signal generator, which includes a timing generator, a pattern generator,
It comprises a generator, a format controller, a voltage input / output circuit, and other circuits, and generates a driver signal supplied to the semiconductor memory 2 to be tested, an expected value pattern used in the logical comparison unit 3, a timing signal, and other signals. Is what you do. The semiconductor memory 2 to be tested is a semiconductor memory having a redundant circuit. A write operation is performed by applying a driver signal output from the signal generator 1 to an internal cell of the semiconductor memory 2, and then a read operation is performed. The supplied data is supplied to the logical comparison unit 3. The logic comparison unit 3 compares the data supplied from the semiconductor memory 2 to be tested and the expected value pattern data supplied from the signal generation unit 1 with the timing specified by the timing signal supplied from the signal generation unit 1. , And sends the result, that is, the pass / fail judgment result of the semiconductor memory 2 to the fail memory 4 as fail information. The contents of the fail information sent to the fail memory 4 are fail cell address information, semiconductor memory information, data bit information and other information. Reference numeral 5 denotes a repair analysis unit which obtains a remedy solution for the semiconductor memory 2 having a redundant circuit based on the fail information stored in the fail memory 4, and performs a rescue process. The test flow is as shown in FIG.

The conventional semiconductor memory test unit comprises a signal generator 1, a logic comparator 3, and a fail memory 4.
The repair processing unit comprises a fail memory 4 and a repair analyzer 5.

[0004]

As described above, a semiconductor memory test apparatus having a redundant circuit includes data supplied from a semiconductor memory 2 to be tested and expected value / pattern data supplied from a signal generator 1. And logical comparison unit 3
When the result, that is, the result of the pass / fail judgment of the semiconductor memory 2 is sent to the fail memory 4 as fail information, the repair analysis unit 5 directly accesses the result to obtain a remedy solution. I have. Therefore, it cannot be said that the test has been completed until the rescue process is completed, and the fail information content of the fail memory 4 cannot be reset. That is, the failure information is reset when the repair processing by the repair analysis unit 5 is completed, and the next test can be started for the first time here. The total test time from the start of the test to the completion of the test is the sum of the pure test time for operating the semiconductor memory test unit and the rescue processing time for operating the rescue processing unit. Looking at the throughput of only the semiconductor memory test unit, this throughput is reduced by the rescue processing time during which the rescue processing unit operates.

This invention is intended to improve the throughput of a semiconductor memory test unit of a semiconductor memory test device having a redundant circuit.

[0006]

[MEANS FOR SOLVING THE PROBLEMS] A driver signal and an expected value
Signal generator for generating turn and other signals, tested
Ratio between the output data of the semiconductor memory to be expected and the expected value pattern
Logical comparison unit to compare and fail output by the logical comparison unit
Semiconductor memory comprising fail memory for storing information
Equipped with a test unit and a fail
The fail information stored in the memory is transferred and stored as it is.
Buffer memory and access to that buffer memory.
And repair semiconductor memory
Fail processing unit and the buffer memory
As soon as the information has been transferred and stored, the test unit
Test, and the rescue processing unit
Means for repair analysis of fail information stored in the
Yes to.

[0007]

An embodiment of the present invention will be described with reference to FIG. In FIG. 2A, reference numeral 1 denotes a signal generator, which comprises a timing generator, a pattern generator, a format controller, a voltage input / output circuit, and other circuits, and is supplied with a driver signal supplied to the semiconductor memory 2 to be tested. , An expected value pattern, a timing signal, and other signals used in the logical comparison unit 3. The semiconductor memory 2 to be tested is a semiconductor memory having a redundant circuit. A write operation is performed by applying a driver signal output from the signal generator 1 to an internal cell of the semiconductor memory 2, and then a read operation is performed. The supplied data is supplied to the logical comparison unit 3. The logical comparison unit 3
The data supplied from the semiconductor memory 2 to be tested and the expected value pattern data supplied from the signal generator 1 are logically compared at the timing designated by the timing signal supplied from the signal generator 1, and The result, that is, the result of the pass / fail judgment on the semiconductor memory 2 is sent to the fail memory 4 as fail information. The contents of the fail information sent to the fail memory 4 are fail cell address information, semiconductor memory information, data bit information and other information. Reference numeral 6 denotes a buffer memory added according to the present invention. This buffer memory 6 is a fail memory 4 of the prior art.
And the repair analysis unit 5 interposed therebetween, and the memory contents of the fail memory 4 are transferred and stored as they are. Reference numeral 5 denotes a repair analysis unit which, unlike the conventional example, does not directly access the storage contents of the fail memory 4 but accesses the fail information transferred from the fail memory 4 to the buffer memory 6 as it is. Then, a repair solution for the semiconductor memory 2 having the redundant circuit is obtained based on the fail information, and a repair process is performed on the solution.

[0008] The semiconductor memory test unit of the present invention comprises:
As in the case of the conventional example, it comprises a signal generator 1, a logic comparator 3, and a fail memory 4. The rescue processing unit comprises a buffer memory 6 and a repair analysis unit 5 unlike the conventional example. When a semiconductor memory test unit of a semiconductor memory test apparatus tests a semiconductor memory 2 having a redundant circuit and rescues it based on the test data,
When the fail information as the result of the pass / fail judgment on the semiconductor memory 2 is sent to the fail memory 4, the fail information is immediately transferred and stored in the buffer memory 6 as it is. The test flow is as shown in FIG. When the fail information is transferred from the fail memory 4 to the buffer memory 6, the fail memory 4 is reset and the next test can be started immediately. In the rescue processing unit, the repair analysis unit 5 accesses the buffer memory 6 and performs rescue processing of the semiconductor memory 2 in parallel with the semiconductor memory test unit in parallel.

[0009]

In the above-described test on the semiconductor memory 2 having the redundancy circuit, the pass / fail test time by the semiconductor memory test unit and the rescue processing time by the rescue processing unit are generally almost equal. The transfer time of the fail information to the buffer memory 6 is about 1/10 of these times.

As for the total test time from the start of the test to the completion of the test, the total test time increases by the addition of the transfer time of the fail information, and thus the throughput of the semiconductor memory test device decreases. However, regarding the pure test time for operating the semiconductor memory test unit, the transfer time of the fail information is smaller than the rescue processing time as described above, and this is reduced by ((repair processing time−fail information transfer time)). The throughput of the semiconductor memory test unit improves accordingly.

As described above, even though the throughput of the semiconductor memory test apparatus seems to decrease, the utilization efficiency of the semiconductor memory test apparatus can be improved by improving the throughput of the semiconductor memory test unit itself. Considering the improvement of the workability and other effects, the test and the rescue processing of the semiconductor memory having the redundant circuit are facilitated after all.

[Brief description of the drawings]

FIGS. 1A and 1B are diagrams illustrating a conventional example of a semiconductor memory test device, FIG. 1A is a block diagram thereof, and FIG. 2B is a diagram showing a flow of the test.

FIG. 2 is a diagram for explaining an embodiment of the present invention.
FIG. 2A is a block diagram of the semiconductor memory test device of the present invention, and FIG. 2B is a diagram showing a test flow of the semiconductor memory test device of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Signal generation part 2 Semiconductor memory to be tested 3 Logical comparison part 4 Fail memory 5 Repair analysis part 6 Buffer memory

Continuation of front page (56) References JP-A-4-53100 (JP, A) JP-A-59-146499 (JP, A) JP-A-59-152598 (JP, A) JP-A-3-176680 (JP) , A) JP-A-3-252999 (JP, A) JP-B-60-11399 (JP, B2) (58) Fields investigated (Int. Cl. ⁶ , DB name) G11C 29/00

Claims (1)

(57) [Scope of request for utility model registration] 1. A signal generator for generating a driver signal, an expected value pattern and other signals, a logical comparator for comparing output data of a semiconductor memory to be tested with an expected value pattern, and fail information output by the logical comparator. And a semiconductor memory test unit comprising a fail memory for storing the data stored in the fail memory every test cycle.
Eiru information transferred intact stored Ru buffer memory and the relief processing unit consisting of the repair analysis unit for repairing a semiconductor memory by accessing the buffer memory
When, the fail information stored transferred to the buffer memory
Immediately, the test unit performs the next test
In addition, the rescue processing unit includes the buffer memory
For repair analysis of the fail information stored in the memory
Test apparatus for a semiconductor memory having a redundancy circuit, characterized by have a.