TW594481B - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device Download PDF

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Publication number
TW594481B
TW594481B TW090130961A TW90130961A TW594481B TW 594481 B TW594481 B TW 594481B TW 090130961 A TW090130961 A TW 090130961A TW 90130961 A TW90130961 A TW 90130961A TW 594481 B TW594481 B TW 594481B
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TW
Taiwan
Prior art keywords
memory
circuit
signal
semiconductor
comparison
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Application number
TW090130961A
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Chinese (zh)
Inventor
Iwao Ishinabe
Original Assignee
Hitachi Ltd
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Publication of TW594481B publication Critical patent/TW594481B/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1087—Data input latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits

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Abstract

This invention discloses a semiconductor integrated circuit device, which comprises a comparison information latch circuit for storing comparison information which includes address information and write information to a semiconductor storage circuit and a backup comparator circuit. This backup comparator circuit compares corresponding signals of the signals in a semiconductor integrated circuit which are generated by the comparison information of the latch circuit and by an input signal for memory actions and outputs the coincidence signal.

Description

五、發明説明（1) (請先閱讀背面之注意事項再填寫本頁) 本發明係關於半導體積體電路裝置，係關於，利用在 ，例如，具有同步動態隨機存取記憶體（以下簡稱爲 SDRAM)及控制其記憶之記憶體控制器之多晶片架構之半 導體積體電路裝置時，很有效之技術。 傳統上，在連接有LSI(大規模積體電路）及 SDRAM (Synchronous Dynamic Random Access Memory)之系統， 需要實機動作確認，而動作比較單純，動作速度比較慢時 ，可以對連接該等兩者之信號本身直接連接邏輯分析儀或 檢測電路加以觀測。而對SDRAM等之存取之主體是限定 在CPU或專用處理電路時，動作比較單純，可以很容易 藉邏輯模擬等檢出不妥當的地方來。 經濟部智慧財產局員工消費合作社印製 惟，隨著技術之進步，對SDRAM等記憶體之存取速 度被要求應高速化時，如DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory)藉由利用 兩時鐘脈衝邊緣等而進一步被要求更高速之動作時，如果 是在信號傳遞路徑連接邏輯分析儀等之架構，將會受到串 訊或反射等之信號波形混亂之很大之影響，要直接觀測連 接信號很困難。 而且，朝著系統之高性能化，而增大記憶體之容量， 共用記憶體，使從多數處理電路向同一記憶體之存取大容 量化·複雜化時，也會發生嚴重之問題。亦即，會發生， 在對SDRAM等之記憶體進行存取中發生問題時，從跟帶 來該問題之處理電路不同之處理電路進行存取等之寫入動 作，會使發生問題時之狀態消失，追究其原因（除錯）非常 本紙張尺度適用中國國家標準（CNS ) A4規格（210X：297公釐） -4- 594481 :上A7 — -..一—*y 五、發明説明（2) 困難之事態。 (讀先閲讀背面之注意事項再填寫本頁) 在此’一般之邏輯不良可以提供SDRAM等之模擬模 型’藉由模擬事前加以驗證。但是，關於很難模擬之大容 量之資料存取，或由多數信號處理電路存取之複雜組合所 發生之邏輯不良，或實機動作時，有時會因定時或雜訊等 之不正常而發生之問題，在發生問題後仍繼續對半導體記 憶裝置進行存取（寫入動作）等，會使發生問題時之狀態消 失，檢出問題後之原因追查很困難。結果是，令人覺得， 系統之高性能化愈進展，供開發系統用之支援開發之良法 正在消失中。 再者’經由完成本發明後之調查，本發明人被告知， 有關後段要說明之本發明之記憶體之除錯支援功能，已有 日本國特開平5 - 342038號公報，及特開平4 - 171542 號公報之發明存在。但是，在該等公報均完全查不到有關 如本發明之在記憶電路本身配設除錯支援功能之記載。 經濟部智慧財產局員工消費合作社印製 本發明之一個目的在提供，用以追究對半導體記憶電 路之不希望有之存取，或起因於此之在半導體記憶電路內 發生之問題之原因用之支援功能。 本發明之另一目的在提供，不會對動作信號造成非所 希望之影響之記憶體存取信號觀察技術。 本發明之上述及其他目的以及新穎之特徵，可以從本 說明書之記述及附圖獲得進一步之暸解。 簡單說明本案所揭示之發明中之具代表性者之槪要如 下。亦即，配設有，用以記憶包含對半導體記憶電路之位 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -5- 594481V. Description of the invention (1) (Please read the precautions on the back before filling out this page) The present invention relates to semiconductor integrated circuit devices, and is related to, for example, having synchronous dynamic random access memory (hereinafter referred to as SDRAM) and a multi-chip-based semiconductor integrated circuit device of a memory controller that controls its memory are very effective technologies. Traditionally, in a system connected to LSI (Large-Scale Integrated Circuit) and SDRAM (Synchronous Dynamic Random Access Memory), the actual operation of the system needs to be confirmed, and the operation is relatively simple and the operation speed is slow. The signal itself is directly connected to a logic analyzer or detection circuit for observation. The main body of access to SDRAM is limited to the CPU or the dedicated processing circuit. The operation is relatively simple, and it can be easily detected by logic simulation and other inappropriate places. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. However, with the advancement of technology, the speed of access to SDRAM and other memory should be increased, such as DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory). When two clock pulses are required for higher-speed operation, if the structure is connected to a logic analyzer in the signal transmission path, it will be greatly affected by the signal waveform chaos such as crosstalk or reflection. You must directly observe Connecting signals is difficult. In addition, as the system becomes more high-performance, the capacity of the memory is increased, and the shared memory is used to increase the access capacity from most processing circuits to the same memory. When quantifying and complicating, serious problems also occur. That is, when a problem occurs in accessing memory such as SDRAM, a write operation such as access from a processing circuit different from the processing circuit that caused the problem may occur, which may cause the state when the problem occurs. Disappeared, investigate the cause (correction). The paper size applies the Chinese National Standard (CNS) A4 specification (210X: 297 mm) -4- 594481: on A7 —-.. 一 — * y V. Description of the invention (2 ) Difficult situation. (Read the precautions on the back before you fill out this page.) Here, “General Logic Defects can provide simulation models such as SDRAM”, which can be verified beforehand by simulation. However, when it comes to large-capacity data access that is difficult to simulate, or complex logic that is accessed by most signal processing circuits, or the actual machine operates, it may sometimes be caused by abnormalities such as timing or noise. If a problem occurs, the semiconductor memory device will continue to be accessed (written) after the problem occurs, which will cause the state to disappear when the problem occurs, and it is difficult to trace the cause after the problem is detected. As a result, it is felt that the higher the performance of the system is, the better methods for developing the system to support development are disappearing. Furthermore, through investigation after completion of the present invention, the present inventor was informed that the debugging support function of the memory of the present invention to be described in the following paragraphs has been disclosed in Japanese Patent Application Laid-Open No. 5-342038 and Japanese Patent Application Laid-Open No. 4- The invention of Publication No. 171542 exists. However, in these publications, no record can be found regarding the provision of a debugging support function in the memory circuit itself as in the present invention. An objective of the invention printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economics is to provide for investigating undesired access to semiconductor memory circuits, or for reasons that cause problems in semiconductor memory circuits. Support functions. Another object of the present invention is to provide a memory access signal observation technique which does not cause an undesired influence on an operation signal. The above and other objects and novel features of the present invention can be further understood from the description of the specification and the accompanying drawings. A brief description of the representative of the inventions disclosed in this case is as follows. That is, it is provided for memorizing the position of the semiconductor memory circuit. The paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) -5- 594481

五、發萌説明(3) (請先閱讀背面之注意事項再填寫本頁) 址資訊、寫入資訊之比較資訊之比較資訊閂鎖電路，及支 援用比較電路，藉此支援用比較電路，比較上述閂鎖電路 之比較資訊，與爲了記憶動作而輸入之輸入信號所作成之 半導體積體電路內之信號中對應之信號相互間，而輸出其 一致信號。 爲了更詳細敘述本發明，參照附圖說明如下。 第1圖係表示本發明之半導體積體.電路裝置之一實施 例之方塊圖。雖不特別限定，但本實施例之系統LSI(大 規模積體電路）及SDRAM以分別爲不同半導體晶片之形 態構成，且構成爲一整體，使之可以看做是實質上之一個 半導體積體電路裝置。上述系統LSI及SDRAM係例如稱 作MCP(Multi Chip Package)型之形態之半導體積體電路 裝置。 經濟部智慧財產局員工消費合作社印製 此MCP型半導體積體電路裝置係，例如以系統LSI 做爲基礎晶片，在其上堆疊構成SDRAM之半導體晶片， 再以樹脂封裝體組裝成一個組件之積層型之架構。也可以 在安裝基板並排搭載上述兩個半導體晶片，而以一個樹脂 封裝體封裝，以此架構取代上述架構。 形成上述SDRAM之製造程序，與形成CPU等之邏輯 LSI之製造程序不相同，因此，要在一片基板上形成雙方 ，便要採用各自所要求之程序，不僅製造成本變高，處理 程序之複雑化有可能對元件特性有不良影響。因此，如本 實施例之將包含CPU之系統LSI與SDRAM分別形成在個 別之半導體晶片，再將良好製品之晶片組合使成一個半導 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -6 - 594481 (F:' : 1 η- i年'.η / .if 丫 丨孓」.匚. A7 B7 補充 五、發明説明（4) 體積體電路裝置，對成本及元件特性均十分有利。 (請先閱讀背面之注意事項再填寫本頁) 系統LSI係由例如CPU(中央處理裝置或微電腦）、圖 表處理器GPU、影像 /聲音PEG、ACC信號處理電路、 密碼處理電路及直接存取記憶體控制電路DMAC、及記憶 體控制器，所構成。SDRAM則經由上述記憶體控制器由 上述CPU、圖表處理器GPU、影像 /聲音PEG、ACC信 號處理電路、密碼處理電路及直接存取記憶體控制電路 DMAC、及記憶體控制器之任一選擇性加以存取。亦即， 上述包含CPU之多數處理電路係由內部之高速封包匯流 排相互連接在一起，藉由req / ack(請求/確認）信號與 封包資訊進行資訊交換，經由記憶體控制器共用SDRAM 進行存取。CPU可藉專用信號與CPU除錯器連接，可以 從外部執行除錯處理。 經濟部智慧財產局員工消費合作社印製 本實施例係藉上述SDRAM之共用記憶體化，而使其 不只CPU，也可以由上述之多數處理電路存取SDRAM等 之記憶體。其結果，會考慮到該記憶體之存取之大容量化 、複雜化。若要強調，則是要消除，在向SDRAM等記憶 體之存取中發生問題時，因CPU以外之處理電路之寫入 動作會使發生問題時之狀態消失，其結果，追究其原因之 除錯變困難之問題。 本實施例另要解決，在使用SDRAM晶片之模擬模型 之模擬測試，很難模擬之大容量之資料存取，或由多數信 號處理電路存取之複雜組合所發生之邏輯不良，或實機動 作時，有時會因定時或雜訊等之不正常而發生之問題。因 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -7- 594481 經 濟 部 智 慧 財 產 局 消 費 合 作 社 印 製 92. 年 t修正 A7 B7 — 補充 五、發明説明（ 5) 此 5 本 實 施 例有下述 之改 進。 爲 了 要 能夠 檢出 SDRAM內之因位 址 或 資 料 造 成 之 不 正 常 存 取 y 而進 行使 用上 述 CPU除錯 器 等 之 除 錯 3 在 系 統 LSI 與 SDRAM 間 新設 本發明之比較 結 果 輸 出 信 號 5 在 比 較 結 果 輸 出信 號成 爲活 性時，經由系 統 LSI 之 記 憶 p 控 制 器 將 上 述 比較 結果 輸tt i信號傳送給 CPU j 藉 此 使 其 能 夠 將 CPU 之 處理 移至 除錯 處理。 第 2 圖 表示 本發 明之 SDRAM 之 一 實 施 例 之 方 塊 圖 〇 雖 不 特 別 限 定， 但本 實施 例之SDRAM 係 具 有 例 如 256 Μ 位 元 之 記 憶 容量 者， 具有 例如 X 16位 元 之 輸 入 輸 出 架 構 者 〇 在 上 述 SDRAM， 對應4個記憶庫# 0 〜 # 3 設 有 4 個 記 憶 體 陣 列 0對‘ 應4 個記 憶庫# 0〜# 3 之 各 記 憶 體 陣 列 備 有 矩 陣 狀 配置 之動 態型 記憶格，配置 於 同 一 列 之 記 憶 格 之 選 擇 端 子 係結 合於 各列 之字線（未圖示） ， 配 置 於 同 一 行 之 記 憶 格 之 資料: 輸入 輸出 端子，係結合 於 各 行 之 互 補 資 料 線 (未圖开 > ) 0 上 述 記 憶體 陣歹！J 之未 ;圖示之字線： ，係依據列（row) 解 碼 器 及 列 位 址信 號之 解碼 結果，由字驅 動 器 將 其 一 條 驅 動 至 選 擇 位 準 。記 億體 陣列 之未圖示之互 補 資 料 線 5 係 結 合 於 包 含 在 感 測放 大器 及行 (c ο 1 u m η)解碼 器 之 行 選 擇 電 路 之 輸 入 輸 出 線 0感 測放 大器 係藉由從記憶 格 讀 出 資 料 檢 出 出 現 在 各 個 互補 資料 線之 微小電位差而 加 以 放 大 之 放 大 電 路 0 行 選 擇 電路 包含 個別 選擇上述互補 資 料 線 而 導 通 至 輸 入 輸 出 線 之 開關 電路 〇行 開關電路則依 據 行 解 碼 器 之 行 位 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 請 先 閱 讀 背 之 注 意 事 項 再 % 寫 本 頁 -8 - 594481 92. 6. 12 A7 B7 五、發明説明（6) 址信號之解碼結果進行選擇動作。 (請先閱讀背面之注意事項再填寫本頁) 上述輸入輸出線由各記憶體庫# 〇〜# 3共用，經由 包含主放大器或寫入放大器之讀出/寫入控制電路連接 在輸入資料暫存器、輸出資料暫存器。對應此等輸入資料 暫存器及輸出資料暫存器配設有輸入資料緩衝器及輸出資 料緩衝器。端子DQO - DQ15係用以輸入或輸出由16位 元構成之資料 DO - D 1 5之資料輸入輸出端子。端子 DQMU / L掩蔽信號，對應上述端子DQO - DQ15之16位 元構成之輸入資料D 0 - D 1 5被分成上側U及下側L各8 位元（1位元組），當信號DQMU / L成爲活性位準時，在 對應之輸入資料D1 5 - D8 (U)及D7 - DO (L)施加掩蔽（禁 止寫入）。 位址緩衝器經由位址輸入端子 A0〜A12及BA0、 BA1接受位址信號，並暫行保持。位址輸入端子A1〜 A1 2供應有對應指令之時間序列之列系位址信號 A0〜 A12及行系位址信號A13〜A21。在位址輸入端子BA0、 BA1供應有後述之記憶庫位址信號BA0、BA1。 經濟部智慧財產局員工消費合作社印製 對應指令以時間序列輸入之上述位址信號中，列系位 址信號A 1 2 - A0係經由記憶格控制電路保持在列位址閂 鎖電路，行系位址信號A2 1 - A 1 3係經由上述記憶格控制 電路保持在行位址閂鎖&計數電路。 再新計數器（Refresh Counter)產生自動再新 (Automatic Refresh)及自行再新（Self Refresh)時之列位址 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） -9- 594481 A7 B7 五、發明説明（7 ) (讀先閱讀背面之注意事項再填寫本頁) 上述行系位址信號A2 1 - A 1 3被供給作爲行位址閂鎖 &計數電路（Column Address Counter)之預設置資料，行位 址計數器則在由後述之指令等所指定之突發模態（burst mode)時，向行解碼器輸出當作上述預設置資料之行位址 信號A2 1 - A 1 3，或依序增値之該行位址信號A2 1 - A 1 3 之値。 模態暫存器（Mode Resister*)保持各種動作模態資訊， 上述列解碼器（Row Decoder)係僅對應由記憶庫選擇器指 定者動作，而介由字驅動器令其進行字線之選擇動作。 時鐘脈衝信號CLK、時鐘脈衝起動信號CKE係經由 時鐘脈衝緩衝器輸入。晶片選擇信號/ CS(記號/表示 附有此記號之信號係低位準起動之信號）、行位址選通信 號/ C AS、列位址選通信號/ RAS 、及寫入起動信號/ WE等之外部控制信號係經由指令緩衝器輸入。 經濟部智慧財產局員工消費合作社印製 時鐘脈衝緩衝器係接受外部之時鐘脈衝信號CLK， 產生與之同步之內部時鐘脈衝信號。雖不特別限定，但上 述內部時鐘脈衝係供給輸入資料暫存器及輸出資料暫存器 或行位址計數器等。 其他外部輸入信號係與該內部時鐘脈衝信號之上昇邊 緣同步而成有意義。晶片選擇信號/ CS藉其低位準指示 指令輸入循環之開始。晶片選擇信號/ CS在高位準時（ 晶片非選擇狀態）或其他輸入無意義。但後述之記憶庫之 選擇狀態或突發動作等之內部動作不會受到變化至晶片非 選擇狀態之影響。./ RAS、/ CAS、/WE之各信號之功能 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -10- 594481Fifth, germination instructions (3) (please read the precautions on the back before filling this page) address information, comparison information written information comparison information latch circuit, and support comparison circuit to support the use of comparison circuit, The comparison information of the above-mentioned latch circuit is compared with the corresponding signal among the signals in the semiconductor integrated circuit made by the input signal inputted for the memory action, and a consistent signal is output. In order to describe the present invention in more detail, it is explained as follows with reference to the drawings. Fig. 1 is a block diagram showing an embodiment of a semiconductor integrated circuit device of the present invention. Although not particularly limited, the system LSI (large-scale integrated circuit) and the SDRAM of this embodiment are configured in the form of different semiconductor wafers, and are formed as a whole, so that it can be regarded as a substantially semiconductor integrated circuit. Circuit device. The above-mentioned system LSI and SDRAM are, for example, semiconductor integrated circuit devices in the form of MCP (Multi Chip Package) type. The MCP-type semiconductor integrated circuit device system is printed by the consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. For example, a system LSI is used as a base chip, and a semiconductor chip constituting SDRAM is stacked thereon, and then a resin package is assembled into a component stack. Type architecture. It is also possible to mount the two semiconductor wafers side by side on the mounting substrate and package them with one resin package, instead of the above structure. The manufacturing process for forming the above-mentioned SDRAM is not the same as the manufacturing process for forming a logic LSI such as a CPU. Therefore, to form both parties on a single substrate, the respective required procedures must be adopted. Not only does the manufacturing cost become higher, but the processing procedure is complicated It may adversely affect the characteristics of the device. Therefore, as in this embodiment, the system LSI including the CPU and the SDRAM are formed on separate semiconductor wafers, and then the wafers of good products are combined to form a semiconducting paper. The paper size applies to the Chinese National Standard (CNS) A4 specification (210X297) (Centi) -6-594481 (F: ': 1 η-i years'.η / .if 丫 丨 孓 ″. 匚. A7 B7 Supplement V. Description of the invention (4) Volume body circuit device, both cost and component characteristics It is very advantageous. (Please read the notes on the back before filling in this page.) The system LSI is composed of, for example, a CPU (Central Processing Unit or Microcomputer), a graphics processor GPU, image / sound PEG, ACC signal processing circuit, password processing circuit and direct The memory control circuit is composed of DMAC and memory controller. SDRAM is composed of the above-mentioned CPU, graphics processor GPU, video / sound PEG, ACC signal processing circuit, password processing circuit, and direct memory through the above memory controller. Take any one of the memory control circuit DMAC and the memory controller for selective access. That is, most of the above-mentioned processing circuits including the CPU are interconnected by an internal high-speed packet bus. Together, information is exchanged with packet information via req / ack (request / acknowledgement) signals, and accessed via the shared SDRAM of the memory controller. The CPU can be connected to the CPU debugger by a dedicated signal, which can perform debugging from the outside Processing. This embodiment is printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. The above-mentioned embodiment uses the shared memory of the SDRAM to make it not only the CPU, but also the memory of the SDRAM and the like can be accessed by most of the processing circuits. As a result, Considering the increase in capacity and complexity of the memory access. If it is emphasized, it is necessary to eliminate. When a problem occurs in the access to the memory such as SDRAM, the write operation of the processing circuit other than the CPU is caused. The state when the problem occurs will disappear, and as a result, it will be difficult to investigate the cause of the problem. It is also necessary to solve this problem. In the simulation test of the simulation model using the SDRAM chip, it is difficult to simulate the large-capacity data storage. Logic failure caused by complex combinations accessed by most signal processing circuits, or when the real machine operates, sometimes due to abnormalities such as timing or noise The problem is that the paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) -7- 594481 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 92. Year t Amendment A7 B7 — Supplement V. Description of Invention (5) This 5 This embodiment has the following improvements. In order to be able to detect abnormal accesses due to addresses or data in SDRAM, debug using the above-mentioned CPU debugger, etc. 3 Newly set between system LSI and SDRAM The comparison result output signal 5 of the present invention When the comparison result output signal becomes active, the above-mentioned comparison result input signal i is transmitted to the CPU j via the memory p controller of the system LSI, thereby enabling it to move the processing of the CPU to the debugging deal with. FIG. 2 is a block diagram showing an embodiment of the SDRAM of the present invention. Although not particularly limited, the SDRAM of this embodiment has a memory capacity of, for example, 256 M bits, and has an input and output structure of, for example, X 16 bits. 〇 In the above SDRAM, four memory banks # 0 to # 3 are provided. Four memory arrays 0 pairs are provided. Each of the four memory banks # 0 to # 3 is equipped with a dynamic memory cell in a matrix configuration. The selection terminals of the memory cells arranged in the same row are combined with the word lines of each row (not shown). The data of the memory cells arranged in the same row are: the input and output terminals are combined with the complementary data lines of each row (not shown) On >) 0 The above memory arrays! The word line of J: The word line shown in the figure is based on the decoding result of the row decoder and the column address signal, and one of them is driven to the selection level by the word driver. The unillustrated complementary data line 5 of the memory array is combined with the input and output lines of the row selection circuit included in the sense amplifier and the row (c ο 1 um η) decoder. The sense amplifier is obtained from the memory cell. Amplifying circuit that reads out the data and detects the small potential difference appearing on each complementary data line and amplifies it. 0 The row selection circuit includes a switching circuit that individually selects the complementary data line and is connected to the input and output lines. The row switching circuit is based on the line decoder. The paper size of this paper applies the Chinese National Standard (CNS) A4 specification (210X297 mm). Please read the precautions on the back first and then write this page-8-594481 92. 6. 12 A7 B7 V. Description of Invention (6) Address The decoding result of the signal is selected. (Please read the precautions on the back before filling in this page.) The above input and output lines are shared by each memory bank # 〇 ~ # 3, and are connected to the input data temporarily via a read / write control circuit including a main amplifier or a write amplifier. Register, output data register. Corresponding to these input data registers and output data registers, an input data buffer and an output data buffer are provided. Terminals DQO-DQ15 are used to input or output data consisting of 16 bits DO-D 1 5 data input and output terminals. The terminal DQMU / L masks the signal, corresponding to the 16-bit input data D 0-D 1 5 of the terminals DQO-DQ15. It is divided into 8 U (1 byte) each of the upper U and lower L. When the signal DQMU / When L becomes active, a mask is applied to the corresponding input data D1 5-D8 (U) and D7-DO (L) (write prohibited). The address buffer receives address signals via the address input terminals A0 ~ A12 and BA0 and BA1, and temporarily holds them. The address input terminals A1 to A1 2 are supplied with column-based address signals A0 to A12 and row-based address signals A13 to A21 in a time series corresponding to the instructions. The address input terminals BA0 and BA1 are supplied with bank address signals BA0 and BA1 described later. Among the above-mentioned address signals input by the consumer co-operative society of the Intellectual Property Bureau of the Ministry of Economic Affairs in accordance with the instructions and inputted in time series, the column address signals A 1 2-A0 are maintained in the column address latch circuit through the memory cell control circuit. The address signals A2 1-A 1 3 are held at the row address latch & counting circuit via the memory cell control circuit. The address when the Refresh Counter generates Automatic Refresh and Self Refresh. The paper size applies the Chinese National Standard (CNS) A4 specification (210X 297 mm) -9- 594481 A7 B7 V. Description of the invention (7) (Read the precautions on the back before filling in this page) The above-mentioned row address signals A2 1-A 1 3 are supplied as row address latches & counting circuits (Column Address Counter ), The row address counter outputs the row address signal A2 1-A as the above-mentioned preset data to the row decoder when the burst mode is specified by the instruction described later. 1 3, or sequentially increase the address signal of the row A2 1-A 1 3. The mode register (Mode Resister *) maintains various motion modal information. The above-mentioned row decoder (Row Decoder) only corresponds to the action specified by the memory selector, and the word driver is used to select the word line through the word driver. . The clock signal CLK and the clock start signal CKE are input through a clock buffer. Chip selection signal / CS (sign / signal with this sign is a low level start signal), row address strobe signal / C AS, column address strobe signal / RAS, and write start signal / WE, etc. The external control signal is input through the instruction buffer. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. The clock pulse buffer accepts an external clock pulse signal CLK to generate an internal clock pulse signal synchronized with it. Although not particularly limited, the above-mentioned internal clock pulses are supplied to an input data register, an output data register, or a line address counter. The other external input signals are meaningful in synchronization with the rising edge of the internal clock signal. The chip select signal / CS indicates the start of the command input cycle by its low level. The chip selection signal / CS is at high level (chip is not selected) or other inputs are meaningless. However, internal operations such as the selection state or sudden actions of the memory bank described later will not be affected by changes to the non-selection state of the chip. Functions of each signal of ./ RAS, / CAS, / WE This paper size is applicable to China National Standard (CNS) A4 specification (210X297 mm) -10- 594481

五、發明説明（8) 與通常之DRAM之對應信號不同，在定義後述之指令循 環時成爲有意義之信號。 (請先閲讀背面之注意事項再填寫本頁) 時鐘脈衝起動信號CKE係用以指示下一時鐘脈衝信 號之有效性之信號，該信號CKE在高位準時，下一時鐘 脈衝信號CLK之上昇邊緣爲有效，低位準時爲無效。再 者，在讀出模態時，配設有控制資料輸出緩衝器之輸出起 動之外部控制信號/ 〇E時，此信號/ 0E也供給指令緩 衝器，該信號在例如高位準時資料輸出緩衝器成爲高輸出 阻抗狀態。 上述列位址信號係由，同步於時鐘脈衝信號CLK(內 部時鐘脈衝信號）之上昇邊緣之後述之列位址選通記憶庫 活性指令循環之A0〜A 1 2之位準加以定義。 經濟部智慧財產局員工消費合作社印製 位址信號B A0及B A 1在上述列位址選通記憶庫活性 指令循環時被看做是記憶庫選擇信號BAO、BA1，依BAO 、B A1之組合，選擇4個記憶庫# 0〜# 3中之1個。雖 不特別限定，但記憶庫之選擇控制可以藉由僅選擇記憶體 側之列解碼器之活性化、非選擇記憶庫側之行開關電路之 全非選擇、僅連接至選擇記憶庫側之資料輸入緩衝器及資 料輸出緩衝器等處理來控制。 上述行位址信號係如上述，記憶容量爲2 56 Μ位元 ，輸入輸出架構爲 X 1 6架構時，以同步於時鐘脈衝信號 CLK(內部時鐘脈衝信號）之上昇邊緣之讀出或寫入指令（行 位址讀出指令、行位址寫入指令）循環之Α0〜Α8之位準 加以定義。而，如此定義之行位址係被當作突發存取之啓 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐） -11 - 594481V. Description of the invention (8) Different from the corresponding signal of ordinary DRAM, it becomes a meaningful signal when defining the instruction cycle described later. (Please read the precautions on the back before filling in this page) The clock pulse start signal CKE is a signal to indicate the validity of the next clock pulse signal. When the signal CKE is at a high level, the rising edge of the next clock pulse signal CLK is Valid, low time is invalid. In addition, when the readout mode is equipped with an external control signal / 0E that controls the output start of the data output buffer, this signal / 0E is also supplied to the command buffer. This signal is, for example, a high-level on-time data output buffer. It becomes a high output impedance state. The above column address signal is defined by the levels of the column address strobe memory bank A0 ~ A 1 2 which are synchronized with the rising edge of the clock pulse signal CLK (internal clock pulse signal). The address signals B A0 and BA 1 printed by the employee's consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs are regarded as bank selection signals BAO and BA1 during the above column address strobe memory bank active instruction cycle, according to the combination of BAO and B A1 , Select one of 4 banks # 0 ~ # 3. Although it is not particularly limited, the selection control of the memory bank can be performed by selecting only the activation of the column decoders on the memory side, the non-selection of the non-selection of the row switch circuit on the non-selection bank side, and the data connected only to the selected memory side Input buffer and data output buffer control. The above row address signals are as described above, the memory capacity is 2 56 megabits, and when the input and output architecture is X 1 6 architecture, read or write is synchronized to the rising edge of the clock pulse signal CLK (internal clock pulse signal). The levels of A0 ~ A8 of the instruction (line address read instruction, line address write instruction) cycle are defined. However, the address defined in this way is used as a reminder of burst access. The paper size applies the Chinese National Standard (CNS) Α4 specification (210X297 mm) -11-594481

五、發明説明（9) 始位址。 (請先閲讀背面之注意事項再填寫本頁) 其次，簡單說明由指令所指示之SDRAM之主要之普 通動作模態。 (1) 模態暫存器設置指令 係設置上述模態暫存器之指令，藉 / CS、/ RAS、/ CAS '/ WE =低位準指定該指令，應設置之資料係經由 A0〜A 1 2供給。雖不特別限定，但暫存器設置資料係區 間長度、CAS等待時間（latency time)、寫入模態等。雖 不特別限定，但可設定之區間長度爲 1 ' 2、4、8，可設 定之CAS等待時間爲2、3，可設定之寫入模態係脈衝串 寫入（burst write)與單筆寫入（single write)。 經濟部智慧財產局員工消費合作社印製 上述CAS等待時間係用以指示，在由後述之行位址 讀出指令所指示之讀出動作時，從/ CAS之下降至資料 輸出緩衝器之輸出動作間，花費內部時鐘脈衝信號幾個循 環分。因在確定讀出資料前需要讀出資料用之內部動作時 間，因而對應內部時鐘脈衝信號之使用頻率加以設定時使 用。換言之，使用頻率高之內部時鐘脈衝信號時將CAS 等待時間設定成相對大之値，使用頻率低之內部時鐘脈衝 信號時將CAS等待時間設定成相對小之値。 (2) 列位址選通•記憶庫活性指令 這是使列位址選通之指示與BA1及BAO之記憶庫之 選擇成爲有效之指令，藉由/ CS、/ RAS =低位準，/ 本紙張尺度適用中.國國家標準（CNS ) A4規格（210X297公釐） -12- 594481 Α7 Β7 五、發明説明（ (請先閱讀背面之注意事項再填寫本頁) CAS、/ WE =高位準指示，這時是供給位址端子 AO〜 A12之位址被當作列位址信號’而將供給位址端子BA0 及BA1之信號當作記憶庫之選擇信號取進。取進動作係 如上述，與內部時鐘脈衝信號之上昇邊緣同步進行。例如 ’指定該指令時，則選擇由此指定之記憶庫之字線，連接 在該字線之記憶格分別與所對應之互補資料線導通。 〇)行位址•讀出指令 此指令係開始脈衝串讀出動作所必須之指令，同時是 供給行位址選通指示之指令，以/ C S、/ C A S =低位準 ，/ RAS、/ WE =高位準指示。這時供給位址端子A0〜 A 1 1之行位址被當作行位址信號A 1 3〜A2 1取進。藉此取 進之行位址信號A 1 3〜A2 1，係如上述被當作脈衝串開始 位址供給行位址閂鎖計數器。 經濟部智慧財產局員工消費合作社印製 在藉此指示之脈衝串讀出動作，因爲在之前之列位址 選通•記憶庫活性指令循環已進行記憶庫及子線之選擇， 該選擇字線之記憶格，則與內部時鐘脈衝信號同步，依據 從行位址計數器輸出之位址信號，依序連續選擇而讀出。 連續讀出之資料數係由上述區間長度所指定之個數。同時 ，從資料輸出緩衝器之資料讀出，係等到上述CAS等待 時間所規定之內部時鐘脈衝號之循環數，再開始進行 (4)行位址•寫入指令5. Description of the invention (9) Start address. (Please read the precautions on the back before filling this page.) Secondly, briefly explain the main general operation modes of the SDRAM indicated by the instructions. (1) The modal register setting instruction is the instruction to set the above modal register. Specify this instruction by / CS, / RAS, / CAS '/ WE = low level, and the data to be set is via A0 ~ A 1 2Supply. Although not particularly limited, the register sets the data system area length, CAS latency time, and write mode. Although not particularly limited, the settable interval length is 1 '2, 4, 8, and the CAS wait time can be set at 2, 3, and the settable write mode is burst write and single stroke. Write (single write). The above-mentioned CAS waiting time is printed by the employee's consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs to indicate that when the read operation is instructed by a row address read instruction to be described later, the output operation is lowered from / CAS to the data output buffer. It takes several cycles to divide the internal clock signal. Because the internal operating time for reading data needs to be determined before reading the data, it is used when setting the use frequency of the internal clock signal. In other words, when using an internal clock signal with a high frequency, set the CAS latency to a relatively large value, and when using an internal clock signal with a low frequency, set the CAS latency to a relatively small value. (2) Row address strobe • Bank active instruction This is the instruction that makes the column address strobe instruction and the selection of BA1 and BAO banks effective, by / CS, / RAS = low level, / this Paper size is applicable. National National Standard (CNS) A4 specification (210X297 mm) -12- 594481 Α7 Β7 V. Description of invention ((Please read the precautions on the back before filling this page) CAS, / WE = high level instruction At this time, the addresses supplied to the address terminals AO ~ A12 are taken as the column address signals, and the signals supplied to the address terminals BA0 and BA1 are taken as the selection signals of the memory bank. The taking action is as described above, and The rising edge of the internal clock signal is synchronized. For example, when the command is specified, the word line of the specified memory bank is selected, and the memory cells connected to the word line are respectively connected to the corresponding complementary data lines. 〇) line Address • Read instruction This instruction is necessary to start the burst read operation, and it is also the instruction to provide the row address strobe instruction. / CS, / CAS = low level, / RAS, / WE = high level Instructions. At this time, the row addresses supplied to the address terminals A0 to A 1 1 are taken in as the row address signals A 1 3 to A2 1. The row address signals A 1 3 to A2 1 thus taken in are supplied to the row address latch counter as the burst start address as described above. The Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs has printed the pulse train readout instructions given by this, because the address strobe and memory bank active instruction cycle has already selected the memory bank and the sub-line. The memory grid is synchronized with the internal clock pulse signal, and is read out sequentially and sequentially according to the address signal output from the row address counter. The number of consecutively read data is the number specified by the above interval length. At the same time, the data read from the data output buffer waits for the number of cycles of the internal clock pulse number specified by the CAS wait time before starting (4) row address • write instruction

低位準，/ RASLow level, / RAS

該指令係以/CS、/CAS、/WE 本紙張尺度適用中.國國家標準（CNS ) A4規格（2Κ>Χ297公釐） -13- 594481 92. 6- 12 ， 々丨 A7 - —— ...:_B7 五、發明説明（11) (請先閲讀背面之注意事項再填寫本頁) 高位準指示。這時供給位址端子A0〜A 1 1之位址被當作 行位址信號A13〜A21取進。藉此取進之行位址信號A13 〜A2 1，在脈衝串寫入時被當作脈衝串開始位址供給行位 址閂鎖計數器。藉此指示之脈衝串寫入動作之程序也與脈 衝串讀出動作一樣。但寫入動作沒有CAS等待時間，寫 入資料之取進係從該行位址•寫入指令循環之1時鐘脈衝 後開始。 (5) 預充電指令 這是對以BA1及BAO選擇之記憶庫之預充電之開始 指令，以 / CS、/RAS、/WE = 低位準，/ CAS = 高位 準指示。 (6) 自動再新指令 此指令係開始自動再新所需要之指令，以 / C S、/ RAS、 / CAS =低位準，/ WE、CKE =高位準指示。 經濟部智慧財產局員工消費合作社印製 (7) 無作業指令 此指令係指示不做實質之動作之指令，以/ CS =低 位準，/ RAS、/ CAS ' / WE = 高位準指示。 在SDRAM，在1個記憶庫進行脈衝串動作時，若在 其中途指定別的記憶庫，供給列位址選通·記憶庫活性指 令時，該別的記憶庫之列位址系之動作可以進行，而對該 執行中之一方之記憶庫之動作毫無影響。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -14- 594481 A7 B7 五、發明説明（θ (請先閱讀背面之注意事項再填寫本頁) 因此，例如，在由1 6位元構成之資料輸入輸出端子 ，只要資料不衝突，在處理尙未完成之指令執行中，也可 以對跟該執行中之指令作爲處理對象之記憶庫不同之記憶 庫，發行預充電指令、列位址選通•記憶庫活性指令，令 其預先開始內部動作。 SDRAM之詳細讀出動作如下。晶片選擇 / CS、/ RAS、/ CAS、寫入起動/ WE之各信號係與CLK信號同 步輸入。與 / RAS = 0同時輸入列位址與記憶庫選擇信 號，分別以列位址緩衝器及記憶庫選擇電路加以保持。在 記憶庫選擇電路指定之記憶庫之列解碼器將列位址信號解 碼，從記憶格陣列以微小信號輸出列整體之資料。輸出之 微小信號由感測放大器加以放大、保持。被指定之記憶庫 變成活性（a c t i v e)。 經濟部智慧財產局員工消費合作社印製 從輸入列位址至例如3 C LK後，與C A S = 0之同時輸 入行位址及記憶庫選擇信號，分別由行位址緩衝器及記憶 庫選擇電路保持。若指定之記憶庫是在活性狀態，被保持 之行位址從行位址計數器輸出，由行解碼器選擇行。選擇 之資料則從感測放大器輸出。 從感測放大器輸出資料則經由資料匯流排從資料輸出 緩衝器輸出晶片外。輸出定時與從上述時鐘脈衝緩衝器供 應之時鐘脈衝之上昇邊緣同步。保存在模態暫存器之脈衝 串之長度在4以上時，行位址計數器被自動將其位址增値 ，而讀出下一行資料。 在如上述之SDRAM ’追力□比較資訊閂鎖電路、支援 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） •15- 594481The directive is based on the paper standards of / CS, / CAS, / WE. China National Standard (CNS) A4 specification (2K > X297 mm) -13- 594481 92. 6-12, 々 丨 A7-——. ..: _ B7 V. Description of the invention (11) (Please read the notes on the back before filling this page) High level instructions. At this time, the addresses supplied to the address terminals A0 to A 1 1 are taken in as the row address signals A13 to A21. The row address signals A13 to A2 1 thus taken in are used as the burst start address to supply the row address latch counter when the burst is written. The procedure of the burst write operation instructed by this is also the same as the burst read operation. However, there is no CAS waiting time for the write operation. The data is written in from the address of the row and one clock pulse of the write command cycle. (5) Pre-charge instruction This is the start instruction of pre-charge for the bank selected by BA1 and BAO. It is indicated by / CS, / RAS, / WE = low level, / CAS = high level. (6) Automatic renew instruction This instruction is the instruction required to start automatic renew. It is indicated by / C S, / RAS, / CAS = low level, / WE, CKE = high level. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs (7) No operation instruction This instruction is an instruction that does not perform any substantial action, with / CS = low level, / RAS, / CAS '/ WE = high level instruction. In SDRAM, when performing a burst operation in one bank, if another bank is designated in the middle and a row address strobe and bank active command is provided, the row address system of the other bank can operate. Without affecting the actions of one of the banks in the execution. This paper size applies to the Chinese National Standard (CNS) A4 specification (210X297 mm) -14- 594481 A7 B7 V. Description of the invention (θ (Please read the precautions on the back before filling out this page) Therefore, for example, in 1 6 As for the data input and output terminals composed of bits, as long as the data does not conflict, during the execution of the unfinished instruction, it is also possible to issue a precharge instruction to a memory bank different from the memory of the executing instruction as the processing object. Address strobe • Memory bank active instruction to make it start internal operation in advance. The detailed read operation of SDRAM is as follows. Chip select / CS, / RAS, / CAS, write start / WE signals are input in synchronization with the CLK signal . Input the column address and bank selection signal at the same time as / RAS = 0, and hold it by the column address buffer and bank selection circuit respectively. The column decoder of the bank specified by the bank selection circuit will place the column address signal Decode and output the entire data from the memory grid array as micro signals. The output micro signals are amplified and held by the sense amplifier. The designated memory bank becomes active ( active). After printing by the consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs from the input column address to, for example, 3 C LK, the row address and memory bank selection signal are input at the same time as CAS = 0. The bank selection circuit is maintained. If the specified memory bank is in the active state, the held row address is output from the row address counter, and the row decoder selects the row. The selected data is output from the sense amplifier. Output from the sense amplifier The data is output from the data output buffer out of the chip via the data bus. The output timing is synchronized with the rising edge of the clock pulse supplied from the clock pulse buffer. When the length of the pulse train stored in the modal register is 4 or more, The row address counter is automatically incremented by its address, and the next row of data is read out. In the SDRAM as described above, the “tracing force” compares the information latch circuit to support this paper standard and applies the Chinese National Standard (CNS) A4 specification (210X297). Mm) • 15- 594481

五、發明説明（13) (請先閱讀背面之注意事項再填寫本頁) 用比較電路及比較結果輸出信號。雖不特別限定，但在比 較資訊閂鎖電路經由模態暫存器輸入有，從位址端子A0 〜A 1 2、B AO、B A 1供應之信號作爲比較資訊。此比較資 訊之輸入動作時之端子A0〜A12及B AO、B A1則，擴張 如後述之預約作爲廠商測試模態之測試模態設定動作，亦 即擴張模態暫存器設定動作，生成作爲比較資訊之列系位 址資訊A0〜A1 2、行系位址信號A 1 2 - A 1 3、記憶庫位址 資訊B AO、B A 1、在記憶格控制電路之內部狀態遷移使用 之狀態資訊CST2 - 0、及脈衝串資訊BTA2 - 0，而保持 在比較資訊閂鎖電路，而不是生成平常動作之位址信號、 記憶庫位址信號。 經濟部智慧財產局員工消費合作社印製 支援用比較電路則將保持在上述比較資訊閂鎖電路之 各資訊，與記憶動作時從列位址閂鎖&再新計數器輸出之 列系位址資訊A 1 2〜A0、從行位址閂鎖&計數器輸出之行 系位址信號A2 1 - A1 3、記憶庫位址資訊B A 1、B A0、記 憶格控制電路之內部資訊之狀態資訊C S T 2 - 0、及脈衝 串控制之脈衝串資訊B TA2 - 0中之相對應者，相互進行 比較，若一致，則形成比較結果輸出信號，輸出到外部端 子。 第3圖表示搭載於本發明之SDRAM之支援用比較電 路之一實施例之架構圖。藉由對應比較資訊閂鎖電路之比 較資訊之內部信號，作成比較結果輸出信號。而當藉由指 示上述比較結果之有效/無效之比較許可信號控制之閘 電路之全信號一致時，輸出比較結果信號。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -16- 594481 止 A7 B7 五、發明説明（ (請先閱讀背面之注意事項再填寫本頁) 本實施例係爲了使比較結果輸出信號較其他控制信號 不受雜訊等之影響’因此使其脈衝寬度成爲兩個時鐘脈衝 信號寬度。亦即’上述比較一致信號係藉由正反電路FF1 〜FF3及閘極電路G1、G2所構成之脈衝寬度擴張電路， 使其如上述具有兩個時鐘脈衝分之脈衝寬度。 上述比較許可信號，係用以按比較資訊要素指示這種 支援比較電路之動作之有效/無效，例如在輸入擴張上 述模態暫存器設定動作而輸入之比較資訊時形成。而例如 在，僅指定特定之位址條件，如A1 7 - A14 = 1 及All = 〇之條件時之比較動作時使用。 經濟部智慧財產局員工消費合作社印製 第4圖係表示本發明之系統LSI內之記憶控制器之一 實施例之主要部分方塊圖。在該圖，本來之記憶控制器之 電路方塊予以省略，而以例示方式表示對應設在上述第3 圖之SDRAM之支援比較電路之電路部分。亦即，配設起 始器比較資訊閂鎖電路及起始器比較電路1、2，以比較 電路2檢測，表示存取SDRAM之起始器之起始器識別資 訊與比較結果信號及起始器比較資訊閂鎖電路之値一致， 檢出一致後，使起始器比較結果成爲有效，而控制閘電路 G3設置正反電路FF6，上述起始器比較資訊與起始器識 別資訊一致時’藉由閘電路G4強行使能夠以資料單位禁 止向SDRAM寫入之信號DQMU / L信號成爲有效，以禁 止寫入。藉此，能夠以上述起始器防止發生問題時之狀態 消失掉，因此能夠藉下一次之動作追查其原因。 亦即，起始器比較結果成爲有效時，可以藉由產生至 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -17- 594481V. Description of the invention (13) (Please read the precautions on the back before filling this page) Use the comparison circuit and the comparison result to output the signal. Although not particularly limited, the comparison information latch circuit is input through a modal register, and signals supplied from address terminals A0 to A 1 2, B AO, and B A 1 are used as comparison information. The terminals A0 ~ A12 and B AO, B A1 during the input operation of this comparative information are expanded as described below as a test mode setting operation for the manufacturer test mode, that is, an expansion mode register setting operation, which is generated as The comparison information is the address information A0 ~ A1 2. The row address signal A 1 2-A 1 3. The memory address information B AO, BA 1. The state information used in the internal state migration of the memory cell control circuit CST2-0 and burst information BTA2-0 are kept in the comparison information latch circuit, instead of generating normal address signals and memory address signals. The comparison circuit for printing support of the employee's consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs will keep the information of the above-mentioned comparison information latch circuit, and the row address information output from the row address latch & re-counter during memory operation. A 1 2 ~ A0, row address signal output from row address latch & counter A2 1-A1 3, bank address information BA 1, B A0, status information of internal information of memory cell control circuit CST Correspondence between 2-0 and the burst information B TA2-0 of the burst control are compared with each other. If they match, a comparison result output signal is formed and output to the external terminal. Fig. 3 is a block diagram showing an embodiment of a comparison circuit for supporting SDRAM mounted in the present invention. By comparing the internal signals of the comparison information latch circuit with the comparison information, a comparison result output signal is made. When all the signals of the gate circuit controlled by the comparison permission signal indicating the validity / invalidation of the above comparison result are consistent, the comparison result signal is output. This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) -16- 594481 up to A7 B7 V. Description of the invention ((Please read the precautions on the back before filling this page) This example is for comparison results The output signal is not affected by noise, etc. compared to other control signals, so its pulse width becomes two clock pulse signal widths. That is, the above-mentioned comparatively consistent signal is obtained by the positive and negative circuits FF1 to FF3 and the gate circuits G1 and G2. The pulse width expansion circuit is configured to have a pulse width of two clock pulses as described above. The above comparison permission signal is used to indicate the validity / invalidity of the operation supporting the comparison circuit according to the comparison information element, for example, at the input It is formed when the comparison information inputted by expanding the modal register setting operation is input. For example, it is used for the comparison operation when only specific address conditions are specified, such as the conditions of A1 7-A14 = 1 and All = 〇. Economy Figure 4 printed by the Ministry of Intellectual Property Bureau's Consumer Cooperatives is a block diagram showing the main parts of an embodiment of the memory controller in the system LSI of the present invention. In this figure, the circuit block of the original memory controller is omitted, and the circuit part supporting the comparison circuit of the SDRAM provided in the above Figure 3 is shown by way of illustration. That is, an initiator comparison information latch circuit and Initiator comparison circuits 1, 2 detected by comparison circuit 2 indicate that the initiator identification information of the initiator accessing SDRAM is consistent with the comparison result signal and the initiator comparison information latch circuit. To make the starter comparison result valid, and the control gate circuit G3 is provided with a positive and negative circuit FF6. When the above starter comparison information is consistent with the starter identification information, 'the gate circuit G4 can be used to force the data to the SDRAM. The writing signal DQMU / L signal becomes effective to inhibit writing. This can prevent the state from disappearing when the problem occurs with the above-mentioned initiator, so the cause can be traced by the next operation. That is, starting When the comparison result of the device becomes valid, it can be produced to this paper size by applying the Chinese National Standard (CNS) A4 specification (210X297 mm) -17- 594481

A7 B7 五、發明説明（1句 CPU之高速封包匯流排上之非法指令封包或插入之例外 處理，將發生上述問題時之狀態讀出到CPU模擬器加以 分析。上述起始器比較資訊之設定與起始器比較結果之淸 除，可以藉由對記憶體控制器之I / 〇指令封包，在起始 器比較資訊閂鎖電路設定資訊而實施。 第5圖係表示本發明之SDRAM之作業指令之一實施 例之架構圖。本實施例可以擴張一般之SDRAM之作業指 令中之模態暫存器設置指令，而得設定比較資訊等。 亦即，模態暫存器設置指令之格式是，普通模態可由 位址端子A7 = 0而加以區別。位址端子A7 = 0時，BA1 、BAO及A12 - A8之7位元作爲作業碼（OPCODE)，A6 - A8之3位元用來設定CAS等待時間，A3用以設定脈衝 串型態，A2 - A0之3位元用以設定脈衝串之長度。 上述A7 = 1本來是預約作爲廠商測試模態。此A7 = 1之廠商測試模態未特別限制。但可加上A1 2 = 1而利用 做爲支援比較動作模態。亦即，以位址端子BA1、BA0、 A12 - A0之15位元中之A7 = 1且A12 = 1之條件，擴張 模態暫存器設置指令之格式，設定支援用比較資訊。對應 這種比較資訊設定模態，擴張上述第2圖之模態暫存器之 解碼電路，將BA1、BAO、A12 - 0解碼，而得將支援用 比較資訊設定在支援用比較資訊閂鎖電路。 上述比較資訊之列系位址資訊A1 2 _ A0，行系位址 信號A2 1 - A13、記憶庫位址資訊BAO、BA1、在記憶格 控制電路用作內部狀態遷移之狀態資訊CST2 - 0、及脈 本紙張尺度適用中國國家標準（CNS ) A4規格（210X29*7公釐） 1--N J--；----衣-- (請先閲讀背面之注意事項再填寫本頁)A7 B7 V. Description of the invention (1 sentence for the exception processing of illegal instruction packets or insertions on the high-speed packet bus of the CPU, read out the status when the above problems occur to the CPU simulator for analysis. Set the comparison information of the initiator above The elimination of the comparison result with the initiator can be implemented by the I / O instruction packet to the memory controller and setting information in the initiator comparison information latch circuit. Figure 5 shows the operation of the SDRAM of the present invention. The architecture diagram of one embodiment of the instruction. This embodiment can expand the modal register setting instruction in the general SDRAM operation instruction to obtain comparative information. That is, the format of the modal register setting instruction is Normal mode can be distinguished by address terminal A7 = 0. When address terminal A7 = 0, 7 bits of BA1, BAO and A12-A8 are used as operation codes (OPCODE), and 3 bits of A6-A8 are used Set CAS wait time, A3 is used to set the burst type, and 3 bits of A2-A0 are used to set the length of the burst. The above A7 = 1 was originally reserved as a manufacturer test mode. This A7 = 1 manufacturer test mode The state is not particularly limited. But Add A1 2 = 1 and use it to support the comparison action mode. That is, under the condition that A7 = 1 and A12 = 1 in the 15 bits of address terminals BA1, BA0, A12-A0, the expansion mode is temporarily The format of the register setting instruction is set to support the comparison information. Corresponding to this comparison information setting mode, the decoding circuit of the modal register in Fig. 2 is expanded to decode BA1, BAO, and A12-0 to obtain The support comparison information is set in the support comparison latch circuit. The above comparison information is the address information A1 2 _ A0, the row address signals A2 1-A13, the memory address information BAO, BA1, and the memory cells. The control circuit is used as the state information for internal state transition CST2-0, and the paper size of the pulse is applicable to the Chinese National Standard (CNS) A4 specification (210X29 * 7 mm) 1--N J-; ------ (Please read the notes on the back before filling this page)

'1T 經濟部智慧財產局員工消費合作社印製 -18- 594481 U 12 . … A7 ^ . : j_B7__'1T Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs -18- 594481 U 12... A7 ^.: J_B7__

五、發明説明（W (請先閲讀背面之注意事項再填寫本頁) 衝串資訊B TA2 - 0被分割成多組，藉由上述比較資訊設 定模態之多次返覆而輸入。例如，上述位址端子B A1、 BAO及A12 - AO之15位元中之A12 =1及A7 = 1被使用 在支援用比較資訊模態，因此，剩下之1 3位元可實際利 用以生成比較資訊及比較許可資訊。 上述全比較資訊可以恆常作爲一整體，藉由多次輸入 恆常以一體設定，但僅輸入特定之資訊，或者僅改寫部分 之資訊較方便，因此，以上述13位元中之BA1、BA0及 A1 1、A10之4位元設定比較資訊，以A7以外之A9 - A0 之9位元分開輸入上述比較資訊之列系位址資訊A 1 2 -A0、行系位址信號A2 1 - A 1 3、記憶庫位址資訊B A0、 BA1、在記憶格控制電路用作內部狀態遷移之狀態資訊 CST2 - 0，及脈衝串資訊BTA2 - 0。同時，在此等資訊 之外，另生成對應上述第3圖之各比較資訊之比較許可信 號。 第6圖係說明本發明之SDRAM之模態暫存器設定指 令間隔之一例之定時圖。 經濟部智慧財產局員工消費合作社印製 對應時鐘脈衝信號CLK之上昇，實施發行 / CS、/ RAS、 / C AS '/ WE之低位準之模態暫存器設置MRS之 指令，輸入位址（A0 - A12)及BS (記憶庫選擇位址）BA1、 BA0所指定之電碼（CODE)之模態暫存器設定0。此後返 覆同樣之動作η次，藉此將上述比較資訊之列系位址資訊 A12 - Α0、行系位址信號Α21 - A13、記憶庫位址資訊 BA0、BA1、在記憶格控制電路用作內部狀態遷移之狀態 本紙張尺度適用中.國國家標準（CNS ) A4規格（210X297公釐） -19- 594481 -.92. 6H' : A7 % B7V. Description of the invention (W (please read the precautions on the back before filling out this page) The rush string information B TA2-0 is divided into multiple groups and inputted by multiple replies of the setting mode of the above comparative information. For example, Among the 15 bits of the above address terminals B A1, BAO and A12-AO, A12 = 1 and A7 = 1 are used to support the comparison information mode, so the remaining 13 bits can be actually used to generate comparisons Information and comparison permission information. The above full comparison information can be taken as a whole, and it can be set as a whole by entering multiple times, but it is more convenient to enter only specific information, or to rewrite only part of the information. Therefore, the above 13 digits Set the comparison information of the four bits of BA1, BA0 and A1 1, A10 in the yuan. Separate the 9 bits of A9-A0 other than A7 to enter the row of the above comparison information. The address information is A 1 2-A0, and the row system. Address signals A2 1-A 1 3, memory bank address information B A0, BA1, used as state information CST2-0 and burst information BTA2-0 in the memory cell control circuit for internal state transition. At the same time, in this information In addition, a ratio of the comparison information corresponding to FIG. 3 is generated. Permit signal. Fig. 6 is a timing chart illustrating an example of the setting interval of the modal register of the SDRAM of the present invention. The employee cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs prints the corresponding rise of the clock pulse signal CLK and implements the issuance / CS, / RAS, / C AS '/ WE low level modal register to set MRS command, input address (A0-A12) and BS (memory bank selection address) BA1, BA0 designated code (CODE) The modal register is set to 0. After that, the same action is repeated n times, so that the above comparison information is the address information A12-Α0, the line address signals A21-A13, the memory address information BA0, BA1, used in the state of the memory cell control circuit as the internal state transition. This paper is applicable in the national standard (CNS) A4 specification (210X297 mm) -19- 594481 -.92. 6H ': A7% B7

五、發明説明（W 資訊CST2 - 0，及脈衝串資訊BTA2 - 0整體分成η + 1 (請先閲讀背面之注意事項再填寫本頁) 次輸入。如此輸入之資訊中，除了上述比較資訊以外，也 含有對應這種比較資訊配設之指示有效/無效之上述第 3圖所示之比較許可信號。 第7圖表示說明本發明之SDRAM之寫入指令間隔之 一例之定時圖。亦即，表示，因記憶庫〇活性化而輸入記 憶庫〇之列位址Row，進行字線之選擇動作，延後兩個時 鐘脈衝實施對行位址A之單筆寫入動作，接著實施對行 位址B之脈衝串（脈衝串長度4)寫入動作。 比較資訊.與寫入指令不一致時以虛線表示，比較結果 輸出保持低位準，比較資訊與寫入指令之條件在行位址 B2 —致時，比較結果輸出則輸出兩時鐘脈衝寬度之一致 輸出。 經濟部智慧財產局員工消費合作社印製 第8圖係說明本發明之系統LSI內之記憶控制器與 SDRAM間之動作之一個例子之之定時圖。本實施例在 SDRAM內之支援比較資訊閂鎖電路設定有記憶庫0、行 位址B 1，在記憶體控制器之起始器比較資訊閂鎖電路設 定有起始器（initiator)#〗。上述起始器（initiator)#〗係分配 給對上述SDRAM進行記憶存取之如上述CPU等之信號處 理電路之識別資訊。 在定時圖之後半比較資訊一致，比較結束資訊成爲有 效，在記憶體控制器內由上述第4圖之起始器比較電路2 檢出輸入該資訊之信號處理電路是那一電路，而起始器比 較結果成爲有效。在此狀態下，上述信號DQMU / L信號 本纸張尺度適用中.國國家標準（CNS ) A4規格（210X297公釐） -20- 594481 92. 6. 12 A7 B7 五、發明説明（1 係呈如傳統上之變化。 (請先閱讀背面之注意事項再填寫本頁) 第9圖係說明本發明之系統LSI內之記憶控制器與 SDRAM間之動作之另一個例子之之定時圖。此定時圖係 上述第8圖之定時圖之後半。本實施例係在上述第8圖， 定時圖之起始器比較結果維持有效之狀態，因此，在下一 起始器#1之寫入動作時，強行使DQMU / L信號成爲有 效，因下一起始器#1之寫入動作被禁止，因而保全有該 記憶格。 反之，下一起始器#0之寫入動作被許可，在CPU之 例外處理等必須有之寫入動作不受禁止，可以進行除錯處 理。 在上述第8圖之定時圖，因爲是正在對SDRAM之實 施存取之狀態，要在中途停止會使SDRAM之動作變複雜 ，因此第1次則直接完成動作，而如第9圖所示，下一次 有從同一起始器之記憶體存取動作時，如上述強行使 DQMU / L信號成爲有效，使資料之寫入動作變無效，而 保全該記憶格之記憶資訊。 經濟部智慧財產局員工消費合作社印製 在上述第1圖之半導體積體電路裝置，系統LSI內之 高速匯流排採用高速封包匯流排，以指令封包與Req / Ack(要求/許可）信號，由各功能處理電路以封包單位要 求對記憶體控制器與SDRAM之寫入，共用位址空間。本 實施例包含有，補償·確認封包之順序制用資訊之封包序 列號碼或起始器識別資訊（分別對應密碼處理、影像/聲 音 MPEG、AAC、GPU、CPU 及 DMAC 之資訊）。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -21 - 594481 ；…i 丨 A7 ; +'U B7 五、發明説明（枏 (請先閲讀背面之注意事項再填寫本頁) 因爲使用上述起始器識別資訊’可以辨別那一個信號 處理裝置在對SDRAM進行存取。SDRAM具有很大之記 憶容量，其記憶區域有時被上述起始器分割使用。使用位 址資訊及起始器資訊時’由GPU存取分配給密碼處理或 聲音信號處理之記憶區域等之動作係不正常狀態，使用起 始器資訊與上述支援用比較電路之輸出，便可以檢出起始 器對未經許可之空間進行存取。 系統LSI內之高速匯流排之封包匯流排配設有，除了 對SDRAM之 Read / Write指令外，爲了使其能在各處理 電路之內部暫存器設定之I / 〇 READ / WRITE指令及 指令封包被異常處理時之通知用之非法指令報告指令等。 同時可以從CPU等使用SDRAM之模態暫存器設定指令進 行對SDRAM之支援比較資訊之設定。 在形成於上述系統LSI內之同一處理電路，例如 DMAC、聲音處理電路、MPEG處理電路等，配設多數頻 道時，則對應各該頻道配設起始器資訊。 經濟部智慧財產局員工消費合作社印製 使用上述系統LSI內之高速封包匯流排之I / 〇 WRITE指令之對記憶體控制器之起始器比較資訊設定指 令，設定有起始器之位元資訊及各個起動位元，同時可以 淸除起始器比較結果。 第10圖係表示本發明之半導體積體電路裝置之一實 施例之初期化處理之流程圖。在移行至主程式前之初期化 設定時，設定SDRAM之支援比較資訊及記憶體控制器之 起始器比較資訊。 本紙張尺度適用中國國家標準（CMS ) A4規格（21〇X297公釐） -22- 594481V. Description of the invention (W information CST2-0, and burst information BTA2-0 is divided into η + 1 (please read the precautions on the back before filling this page). Enter the information in this way, in addition to the above comparison information It also contains the comparison permission signal shown in the above-mentioned Fig. 3, which indicates the validity / invalidation of such comparison information configuration. Fig. 7 shows a timing chart illustrating an example of the write instruction interval of the SDRAM of the present invention. That is, It means that the row address of memory 0 is input to memory bank 0 for activation of memory bank 0 to select a word line. Two clock pulses are delayed to perform a single write operation to row address A, and then to the row bit. The writing operation of the pulse train (burst length 4) at address B. Comparison information. When it is not consistent with the write instruction, it is indicated by a dashed line. The comparison result output is kept at a low level. At the same time, the output of the comparison result is the same output of two clock pulses. Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs. Figure 8 illustrates the memory controller and SDRAM in the system LSI of the present invention. Timing chart of an example of the inter-operation. The comparison information latch circuit supported in the SDRAM of this embodiment is set with memory bank 0 and row address B 1. The initiator of the memory controller compares the information latch circuit. An initiator # is set. The initiator # is the identification information assigned to the signal processing circuit such as the CPU and the like that performs memory access to the SDRAM. The information is compared in the second half of the timing chart. If they match, the comparison end information becomes valid. In the memory controller, the initiator comparison circuit 2 in the above figure 4 detects which circuit the signal processing circuit that inputs the information is, and the initiator comparison result becomes valid. In this state, the above-mentioned signal DQMU / L signal is applicable to this paper standard. National National Standard (CNS) A4 specification (210X297 mm) -20- 594481 92. 6. 12 A7 B7 V. Description of the invention (1 series is presented as Traditional changes. (Please read the precautions on the back before filling out this page.) Figure 9 is a timing diagram illustrating another example of the operation between the memory controller and the SDRAM in the system LSI of the present invention. This timing diagram Department The second half of the timing diagram of the above-mentioned Figure 8. This embodiment is based on the above-mentioned Figure 8. The comparison result of the initiator of the timing diagram remains valid. Therefore, the DQMU is forced during the writing operation of the next initiator # 1. The / L signal becomes valid, because the write operation of the next initiator # 1 is prohibited, so the memory cell is preserved. On the contrary, the write operation of the next initiator # 0 is permitted, and it must be processed in the exception of the CPU. The writing operation is not prohibited, and debugging can be performed. In the timing chart of the above Figure 8, because the SDRAM is being accessed, stopping it in the middle will complicate the operation of the SDRAM, so the first This time, the action is directly completed, and as shown in Figure 9, when the next memory access from the same initiator, the DQMU / L signal is forced to become valid as described above, making the data writing action invalid. And keep the memory information of that memory cell. The Intellectual Property Bureau employee consumer cooperative of the Ministry of Economic Affairs printed the semiconductor integrated circuit device in the above figure 1. The high-speed bus in the system LSI uses a high-speed packet bus. Each functional processing circuit requires a write unit to write to the memory controller and SDRAM in a packet unit to share the address space. This embodiment includes the packet sequence number or initiator identification information of the ordering information for compensating and confirming the packets (corresponding to the password processing, video / audio MPEG, AAC, GPU, CPU, and DMAC information). This paper size applies to Chinese National Standard (CNS) A4 specification (210X297 mm) -21-594481; ... i 丨 A7; + 'U B7 V. Description of the invention (枏 (Please read the precautions on the back before filling this page) Because the above-mentioned initiator identification information can be used to identify which signal processing device is accessing SDRAM. SDRAM has a large memory capacity, and its memory area is sometimes divided and used by the above initiators. Use the address information and start In the case of initiator information, the operation of accessing the memory area allocated to password processing or sound signal processing by the GPU is abnormal. Using the output of the initiator information and the support comparison circuit described above, the initiator pair can be detected. Unauthorized space for access. The high-speed bus in the system LSI is equipped with a packet bus. In addition to the Read / Write instructions to the SDRAM, in order to enable it to be set in the internal register of each processing circuit. / 〇 READ / WRITE instruction and illegal instruction report instruction for notification when the instruction packet is abnormally processed. At the same time, it can be set from the CPU and other modal register setting instructions using SDRAM. SDRAM support comparison information setting. In the same processing circuit formed in the above-mentioned system LSI, such as DMAC, sound processing circuit, MPEG processing circuit, etc., when most channels are provided, starter information is provided corresponding to each channel. The Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs printed the I / WRITE instruction of the high-speed packet bus in the above-mentioned system LSI to the starter comparison information setting instruction of the memory controller, and set the bit of the starter The information and each start bit can be eliminated at the same time. The comparison result of the initiator is shown in Fig. 10. Fig. 10 is a flowchart showing the initializing process of one embodiment of the semiconductor integrated circuit device of the present invention. The initial stage before moving to the main program When setting the settings, set the comparison information of SDRAM support and the comparison information of the starter of the memory controller. This paper size applies the Chinese National Standard (CMS) A4 specification (21 × 297 mm) -22- 594481

五、發明説明（2q> (請先閲讀背面之注意事項再填寫本頁) 第11圖係表示本發明之半導體積體電路裝置之一實 施例之移行至除錯處理之流程圖。可以藉由比較結果輸出 檢出產生比較條件成立，藉由產生非法指令報告或插入信 號起動CPU之例外處理程式，以例外處理等檢出發生該 存取動作，實施比較發生資訊之保全處理，而移行至除錯 程式。 第12圖係表示本發明之半導體積體電路裝置之另一 實施例之方塊圖。本實施例附加有，從設在系統LSI之記 憶體控制器對SDRAM供應比較有效信號之功能。其他架 構與上面第1圖之實施例相同。 亦即，在系統LSI與SDRAM之間配設本發明之比較 結果輸出信號與比較有效信號，而當比較結果輸出信號成 爲活性時，經由記憶體控制器傳送給CPU，藉此可以使 CPU之處理移行至除錯處理。 經濟部智慧財產局員工消費合作社印製 本實施例係與第1圖之實施例同樣，包含CPU之多 數處理電路係藉由內部之高速封包匯流排連接，藉req / ack信號與封包資訊交換資訊，經由記憶體控制器共用 SDRAM進行存取。CPU係藉專用信號連接至CPU除錯器 ，可以由外部實施除錯處理。依據本實施例時，具有可以 檢出SDRAM內之異常（因位址或資料）之存取（寫入），使 用CPU除錯器等進行除錯之效果。 第13圖係表示本發明之SDRAM之另一實施例之方 塊圖。本實施例之SDRAM係對應上述第12圖之實施例 。本實施例係與上述第2圖之實施例同樣變更SDRAM之 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -23- 594481V. Description of the invention (2q > (Please read the precautions on the back before filling out this page) Figure 11 shows the flow chart from the migration to the debugging process of one embodiment of the semiconductor integrated circuit device of the present invention. The comparison result output is detected and the comparison condition is established. The exception processing program of the CPU is started by generating an illegal instruction report or inserting a signal, and the access action is detected by exception processing, etc., and the comparison occurrence information is protected. Wrong program. Fig. 12 is a block diagram showing another embodiment of the semiconductor integrated circuit device of the present invention. In this embodiment, a function of supplying a relatively effective signal to the SDRAM from a memory controller provided in the system LSI is added. The other structures are the same as the embodiment in the above Figure 1. That is, the comparison result output signal and the comparison effective signal of the present invention are arranged between the system LSI and the SDRAM, and when the comparison result output signal becomes active, it is controlled by the memory. It is transmitted to the CPU by the processor, so that the processing of the CPU can be shifted to the debugging processing. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs The embodiment is the same as the embodiment in Figure 1. Most of the processing circuits including the CPU are connected through the internal high-speed packet bus, exchange information with the packet information via the req / ack signal, and access the shared SDRAM through the memory controller. The CPU is connected to the CPU debugger by a dedicated signal, and the debug processing can be implemented externally. According to this embodiment, it has access (write) that can detect an abnormality (by address or data) in the SDRAM, The effect of debugging using a CPU debugger, etc. Fig. 13 is a block diagram showing another embodiment of the SDRAM of the present invention. The SDRAM of this embodiment corresponds to the embodiment of Fig. 12 described above. This embodiment is related to The above-mentioned embodiment of Fig. 2 also changes the paper size of the SDRAM to apply the Chinese National Standard (CNS) A4 specification (210X297 mm) -23- 594481

五、發明説明（21) (請先閱讀背面之注意事項再填寫本頁) 模態暫存器之一部分，追加比較資訊等之輸入與比較資訊 閂鎖電路及支援用比較電路’再追加，藉比較有效信號輸 入及比較結果輸出信號’在SDRAM之內部強行使DQMU / L成爲有效之邏輯和電路。 亦即，藉比較有效信號控制支援比較電路之動作之有 效/無效，使用支援用比較電路之輸出信號控制閘電路 G，強行使信號DQMU / L成爲活性位準，控制讀出/ 寫入控制電路。 第1 4圖係表示本發明之系統LSI內之記憶體控制器（ 半導體記憶控制電路）之一實施例之方塊圖。本實施例係 配設起始器比較資訊閂鎖電路及比較電路，設有可向 SDRAM輸出，表示是從成爲支援比較對象之起始器之存 取動作之比較有效信號之功能。而，在設於SDRAM之支 援用比較電路產生之比較結果輸出信號，係在記憶體控制 器被當作通知產生非法指令信號使用。 經濟部智慧財產局員工消費合作社印製 第15圖係表示本發明之SDRAM之支援用比較電路 之另一實施例之電路圖。在本實施例，藉由上述追加之比 較有效信號，作成對應比較資訊閂鎖電路之比較資訊之與 內部信號之比較結果輸出信號。在本實施例，比較結果輸 出信號係由FF7電路保持後，藉由比較有效信號及閘電 路G6取得邏輯和而輸出。 如此，在如SDRAM之記憶電路，配設可使本發明之 功能有效，而指定其動作，設定特定問題之產生處所用之 動作條件之比較資訊閂鎖電路。對此比較資訊閂鎖電路之 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -24 - 12594481 A7 B7 五、發明説明（勾 動作設定，因爲是利用在SDRAM所具有之預約在模態暫 存器設定指令作業之廠商測試模態’因此’只要簡單之電 路之變更、追加便可以實現。 設定之比較資訊也同時包含有，在上述支援用比較電 路進行比較之信號之値，及其比較之有·無效等之資訊。 比較設定在本比較資訊閂鎖電路之動作條件與內部之動作 之支援用比較電路，則輸入有要比較之信號之値及其比較 之有·無效等之資訊，以及成爲比較對象之內部信號（內 部狀態、行位址、列位址、模態信號、資料），依照條件 進行比較。 在例如SDRAM之記憶電路產生可以滿足比較條件之 狀態時，比較有效輸出信號成爲有效，在控制SDRAM之 記憶體控制器，比較上述比較結果輸出信號及其要因是不 是從其對象之起始器送出，一致時則在此後強行禁止該起 始器（或CPU以外之起始器）之寫入動作，且許可再新或 從CPU之讀寫，然後，告知CPU發生設定之狀況，令其 移行至除錯處理，支援保全發生問題時之狀態及追究原因 〇 藉由配設，可作成表示在記憶體控制器之對象起始器 之比較有效信號，輸入SDRAM等之記憶電路，在記憶體 內進行比較，一致時，強行使以後之比較有效信號之有效 時之寫入掩蔽信號（DQMU / L之內部信號）成爲有效，禁 止寫入處理之電路，便可實現跟從上述記憶體控制器輸入 掩蔽信號相同之功能。上述之配設比較有效信號，在其有 本紙張尺度適用中.國國家標準（CNS ) A4規格（210X297公釐） ---Ί J--?----^^衣-- (請先閱讀背面之注意事項再填寫本頁) 訂 經濟部智慧財產局員工消費合作社印製 -25- 594481 I 92. t 12i Π:」 年 3 W...V: A7 L................................_ B7_— 五、發明説明（2$ (請先閲讀背面之注意事項再填寫本頁) 效時，若比較結果一致即禁止寫入，也可以將比較結果信 號之一部分輸入記憶格控制電路，將寫入指令當作其他無 害之指令而遷移狀態來實現。 第16圖係表示本發明之SDRAM之再一實施例之方 塊圖。本實施例在記憶格控制電路附加有，能輸出非法指 令（illegal command)檢測信號之功能。可以將此非法指令 檢測信號輸入上述系統LSI之記憶體控制器，與第1 4圖 之比較結果信號同樣，令CPU產生通知發生非法指令或 插入等之例外處理，藉此，通知CPU被輸入非法指令， 令其移行至除錯處理。 要將輸入非法指令之事項輸出到SDRAM外部時，可 以配設信號輸出端子，輸出記憶格控制電路之指令判斷結 果，便可以實現。亦即，記憶格控制電路本來便設有，可 以判斷是否是能對應記憶體內部狀態之電流狀態之正確指 令之判斷電路，並定有非法指令時之動作，因此，只要配 設利用其檢測電路輸出到上述SDRAM外部之信號線及端 子便可以。 經濟部智慧財產局員工消費合作社印製 將本發明之小規模之電路追加到如SDRAM等之記憶 電路，在系統LSI與記憶電路間追加幾條配線，便可以提 供，能追究在記憶體內發生之問題之原因之支援功能。此 項架構可以利用幾條之未使用端子等，以維持與現用之記 憶電路之互換性之狀況下實現。亦即，因爲不會將觀測用 之信號直接連接在現有之記憶電路之介面，因此，不會直 接受到其影響，支援功能之設定本身也只是擴充現有之記 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -26- 594481V. Description of the invention (21) (Please read the precautions on the back before filling out this page) Part of the modal register, add the input of comparison information, etc. and the comparison information latch circuit and supporting comparison circuit, and then add, borrow The comparison valid signal input and the comparison result output signal 'enforce the DQMU / L in SDRAM to become a valid logic and circuit. That is, the effective / ineffective of the operation of the supporting comparison circuit is controlled by the comparison effective signal, and the gate circuit G is controlled by the output signal of the supporting comparison circuit, and the signal DQMU / L is forced to become the active level, and the read / write control circuit is controlled. . FIG. 14 is a block diagram showing an embodiment of a memory controller (semiconductor memory control circuit) in the system LSI of the present invention. This embodiment is provided with a starter comparison information latch circuit and a comparison circuit, and is provided with a function of a comparatively effective signal that can be output to the SDRAM, indicating that it is an access operation from the starter that supports the comparison target. However, the comparison result output signal generated by the comparison circuit provided in the support of the SDRAM is used in the memory controller as a notification to generate an illegal command signal. Printed by the Consumers' Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs FIG. 15 is a circuit diagram showing another embodiment of a comparison circuit for supporting SDRAM according to the present invention. In this embodiment, by using the above-mentioned additional comparison effective signal, an output signal corresponding to the comparison result of the comparison information of the comparison information latch circuit and the internal signal is prepared. In this embodiment, after the output signal of the comparison result is held by the FF7 circuit, a logical sum is obtained by comparing the effective signal with the gate circuit G6 and output. Thus, in a memory circuit such as SDRAM, a comparison information latch circuit is provided to make the function of the present invention effective, specify its operation, and set the operating conditions used in the place where a specific problem occurs. For this comparative information, the paper size of the latch circuit applies the Chinese National Standard (CNS) A4 specification (210X297 mm) -24-12594481 A7 B7 V. Description of the invention (hook action setting, because it is used in SDRAM to reserve the The manufacturer's test modal of the modal register setting instruction operation is therefore 'as long as simple circuit changes and additions can be implemented. The set comparison information also includes, at the same time, the comparison of the signals supported by the comparison circuit mentioned above, The comparison includes information such as invalidity, etc. To compare the operating conditions of the latch circuit and the internal comparison support circuit set in this comparative information, input the signal to be compared, and compare the validity and invalidity of the comparison. The information and internal signals (internal state, row address, column address, modal signal, data) to be compared are compared according to conditions. When, for example, the SDRAM memory circuit generates a state that can satisfy the comparison condition, the comparison is performed. The effective output signal becomes effective. In controlling the memory controller of the SDRAM, the comparison output signal and the comparison result are compared. If it is sent from the initiator of the object, if it is consistent, then the writing operation of the initiator (or an initiator other than the CPU) is forcibly prohibited, and the new or read and write from the CPU is permitted. Then, Inform the CPU of the status of the setting, make it migrate to the debugging process, and support the maintenance of the state and the cause of the problem when it occurs. ○ By configuration, a relatively effective signal indicating the object starter of the memory controller can be created and input. SDRAM and other memory circuits are compared in the memory. When they are consistent, the writing mask signal (internal signal of DQMU / L) becomes valid when the more effective signals in the future are valid. The circuit that prohibits the writing process can be used. Realize the same function as inputting the mask signal from the above memory controller. The above-mentioned configuration is more effective signal, which is applicable in the paper standard. National Standard (CNS) A4 specification (210X297 mm) --- Ί J- -? ---- ^^ 衣-(Please read the precautions on the back before filling out this page) Order printed by the Intellectual Property Bureau Staff Consumer Cooperatives of the Ministry of Economics-25- 594481 I 92. t 12i Π: `` year 3 W ... V: A7 L ................................_ B7_— V. Description of the invention (2 $ (please read the note on the back first) Please fill in this page again when the results are valid). If the comparison result is consistent, write is prohibited, or a part of the comparison result signal can be input to the memory cell control circuit, and the write instruction can be implemented as other harmless instructions and transferred to the state. 16 The figure is a block diagram showing yet another embodiment of the SDRAM of the present invention. In this embodiment, the memory cell control circuit is added with a function capable of outputting an illegal command detection signal. The illegal command detection signal can be input to the above system The memory controller of the LSI, like the comparison result signal in FIG. 14, causes the CPU to generate an exception process informing that an illegal instruction or insertion has occurred, thereby notifying the CPU that an illegal instruction has been input, and causing it to move to the debugging process. To output the illegal input command to the outside of the SDRAM, you can configure the signal output terminal and output the command judgment result of the memory cell control circuit. That is, the memory cell control circuit is originally provided with a judgment circuit that can determine whether it is a correct instruction that can correspond to the current state of the internal state of the memory, and determines the action when an illegal instruction is provided. Therefore, as long as it is equipped with a detection circuit It is sufficient to output the signal lines and terminals outside the SDRAM. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, adding the small-scale circuit of the present invention to a memory circuit such as SDRAM, and adding a few wirings between the system LSI and the memory circuit, which can be provided, and can be investigated for what happened in the memory Support function for the cause of the problem. This architecture can be implemented with several unused terminals, etc., to maintain interchangeability with the current memory circuit. That is, because the signal for observation will not be directly connected to the interface of the existing memory circuit, it will not be directly affected by it. The setting of the support function itself is only an extension of the existing notebook paper. The Chinese standard (CNS) ) A4 size (210X297 mm) -26- 594481

五、發明説明（2今 (請先閱讀背面之注意事項再填寫本頁) 憶電路所具有之模態設定功能之一部分便能夠因應，動作 速度或配線圖案等也能夠在互換之狀態，提供能追究在記 憶電路內發生之問題之原因用之支援功能。 藉由本發明，由於在發生系統性問題，而猜測其原因 與記憶電路有關連時，能夠從位址或資料或存取之處理電 路等加以限定其發生原因，保全發生問題時之記憶電路內 部之狀態使能夠查明原因，因此可以實現，使發生過程明 確以查明原因之系統開發支援。 以上，依據實施例具體說明本發明人所完成之發明， 但本案發明並不限定如上述實施例，當然可以在不脫離其 主旨之範圍內做各種變更。例如，比較結果輸出端子也可 以用，例如強制變更從記憶電路讀出之資料信號之一部分 ，使其發生同位錯誤等，來替代比較條件一致之資訊。 經濟部智慧財產局員工消費合作社印製 比較結果輸出端子及比較有效信號輸入端子，也可以 選擇使用現有之廠商測試用之端子與模態暫存器。比較結 果輸出端子及比較有效信號輸入端子也是，只要能對應 SDRAM等之記憶電路之一連串之寫入動作或讀出動作進 行輸入輸出便可以，因此其信號之寬度可以較，必須依指 令或位址或資料之記憶電路之製品規模以時鐘脈衝之1個 周期或2個周期輸入輸出之信號之寬度大。藉此，在與測 試電路等切換使用，與不利高速動作之信號端子或記憶體 控制器之配線接續時，也可以實現不受雜訊或定時影響之 確實之介面。 比較結果輸出端子也可以用，例如強制變更從記憶電 本紙張尺度適用中國國家標準（CNS ) A4規格（21〇Χ ：297公釐） -27- 594481 年 月 .修正:丨，♦…t 微見丨 A7 B7 五、發明説明（2马 (請先閱讀背面之注意事項再填寫本頁) 路讀出之資料信號之一部分，使其能在系統LSI側檢出， 來替代比較條件一致之資訊。本發明除了 一般之 SDRAM 外’也可以廣泛應用使用在代表資料轉送時利用時鐘脈衝 之兩邊緣之DDR - SDRAM等之高速SDRAM之半導體記 憶裝置之半導體積體電路裝置。半導體積體電路裝置則除 了如上述之多晶片架構外，也適應在一個安裝基板搭載如 SDRAM之|己憶電路者。 本發明係關於半導體積體電路裝置，可廣泛應用在備 有如SDRAM之記憶電路及擷取此電路之信號處理電路之 半導體積體電路裝置。 七 圖式之簡單說明 第1圖係表示本發明之半導體積體電路裝置之一實施 例之方塊圖。 第2圖係表示本發明之SDRAM之一實施例之方塊圖 第3圖係表示搭載於本發明之SdRAM之支援用比較 電路之一實施例之架構圖。 經濟部智慧財產局員工消費合作社印製 第4圖係表示本發明之系統LSI內之記憶體控制器之 一實施例之主要部分方塊圖。 第5圖係表示本發明之SDRAM之作業指令之一實施 例之架構圖。 第6圖係說明本發明之SDRAM之模態暫存器設定指 令間隔之一例之定時圖。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公楚） -28- 594481 92,,6,42 *' A7 > B7 五、發明説明（2今 第7圖係說明本發明之SDRAM之寫入指令間隔之一 例之定時圖。 (請先閱讀背面之注意事項再填寫本頁) 第8圖係說明本發明之系統LSI內之記憶體控制器與 SDRAM間之動作之一個例子之之定時圖。 第9圖係說明本發明之系統LSI內之記憶體控制器與 SDRAM間之動作之另一個例子之之定時圖。 第10圖係表示本發明之半導體積體電路裝置之一實 施例之初期化處理之流程圖。 第11圖係表示本發明之半導體積體電路裝置之一實 施例之移行至除錯處理之流程圖。 第12圖係表示本發明之半導體積體電路裝置之另一 實施例之方塊圖。 第13圖係表示本發明之SDRAM之另一實施例之方 塊圖。 第1 4圖係表示本發明之系統LSI內之記憶體控制器 之一實施例之方塊圖。 經濟部智慧財產局8工消費合作社印製 第15圖係表示本發明之SDRAM之支援用比較電路 之另一實施例之電路圖。 第16圖係表示本發明之SDRAM之再一實施例之方 塊圖。 主要元件對照表 G—..........閘電路 FF—.........正反器 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -29-V. Description of the invention (2 today (please read the precautions on the back before filling this page) Part of the modal setting function of the memory circuit can respond, and the operation speed or wiring pattern can also be exchanged to provide energy. Support function for investigating the cause of a problem occurring in a memory circuit. According to the present invention, when a systemic problem occurs and the cause is suspected to be related to the memory circuit, the processing circuit can be accessed from an address or data or accessed The causes are limited, and the internal state of the memory circuit at the time of the problem can be identified, so it can be realized, and the development process can be clarified to support the development of the system. The above has specifically explained the inventor's The completed invention, but the invention in this case is not limited to the embodiment described above, and of course, various changes can be made without departing from the gist. For example, the comparison result output terminal can also be used, such as forcibly changing the data signal read from the memory circuit. Part of it, causing parity errors, etc., to replace the information with the same comparison conditions. The Ministry of Intellectual Property Bureau of the People's Republic of China's Consumer Cooperatives printed comparison result output terminals and relatively effective signal input terminals, and can also choose to use existing manufacturers' testing terminals and modal registers. The comparison result output terminals and more effective signal input terminals are also As long as it can input and output in response to a series of write or read operations of one of the memory circuits such as SDRAM, the width of its signal can be compared. It must be based on the size of the instruction or address or data of the memory circuit. One cycle or two cycles of input and output signals have a wide width. This allows switching between test circuits and other signals, and connection with signal terminals or memory controllers that are not suitable for high-speed operation. The interface that can affect the communication or timing. The output terminal of the comparison result can also be used, such as forcibly changing the paper size from the memory book to the Chinese National Standard (CNS) A4 specification (21〇 ×: 297 mm) -27- 594481 . Correction: 丨, ♦ ... t See 丨 A7 B7 V. Description of the invention (2 horses (please read the note on the back first) Part of the data signal read out), so that it can be detected on the system LSI side to replace the information with the same comparison conditions. In addition to the general SDRAM, the present invention can also be widely used in representative data transfer The semiconductor integrated circuit device using high-speed SDRAM and semiconductor memory devices such as DDR-SDRAM on both edges of the clock pulse is used. The semiconductor integrated circuit device is also suitable for mounting on a mounting substrate such as SDRAM in addition to the multi-chip architecture described above. This is a semiconductor integrated circuit device. The present invention relates to a semiconductor integrated circuit device, which can be widely used in a semiconductor integrated circuit device provided with a memory circuit such as SDRAM and a signal processing circuit that retrieves this circuit. FIG. 1 is a block diagram showing an embodiment of a semiconductor integrated circuit device of the present invention. Fig. 2 is a block diagram showing an embodiment of the SDRAM of the present invention. Fig. 3 is a block diagram showing an embodiment of a comparison circuit for supporting the SdRAM of the present invention. Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs. FIG. 4 is a block diagram showing a main part of an embodiment of the memory controller in the system LSI of the present invention. Fig. 5 is a structural diagram showing an embodiment of an operation instruction of the SDRAM of the present invention. Fig. 6 is a timing chart illustrating an example of the modal register setting instruction interval of the SDRAM of the present invention. This paper size applies the Chinese National Standard (CNS) A4 specification (210X297). -28- 594481 92,6,42 * 'A7 > B7 V. Description of the invention (2, 7) This figure illustrates the SDRAM of the present invention. Timing chart of an example of the write command interval. (Please read the precautions on the back before filling this page.) Figure 8 illustrates the timing of an example of the operation between the memory controller and the SDRAM in the system LSI of the present invention. Fig. 9 is a timing chart illustrating another example of the operation between the memory controller and the SDRAM in the system LSI of the present invention. Fig. 10 is a diagram illustrating an embodiment of the semiconductor integrated circuit device of the present invention. Flow chart of the initializing process. Fig. 11 is a flowchart showing the migration to debugging process of one embodiment of the semiconductor integrated circuit device of the present invention. Fig. 12 is another diagram of the semiconductor integrated circuit device of the present invention. 13 is a block diagram showing another embodiment of the SDRAM of the present invention. FIG. 14 is a block diagram showing an embodiment of the memory controller in the system LSI of the present invention. Economy Intellectual Property Office Printed by the 8th Industrial Cooperative, FIG. 15 is a circuit diagram showing another embodiment of the comparison circuit for supporting the SDRAM of the present invention. FIG. 16 is a block diagram showing still another embodiment of the SDRAM of the present invention. G —............. Brake circuit FF —......... Front and reversal This paper size is applicable to Chinese National Standard (CNS) A4 specification (210X297 mm) -29-

Claims (1)

594481 S 92· 12 V . '\ Α8 S Β8 ! C8 丨 一 ；j_^_ 六、申請專利範圍 1 1. 一種半導體積體電路裝置，其特徵係具備半導體記 憶電路，該半導體記憶電路包含： 用以記憶包含位址資訊、寫入資訊的比較資訊之比較 資訊閂鎖電路；及 比較記憶在上述閂鎖電路之比較資訊及記憶動作用的 輸入信號中所對應之信號，而輸出比較結果信號之支援用 比較電路。 2. 如申請專利範圍第1項之半導體積體電路裝置，其 中對上述比較資訊閂鎖電路之比較資訊的輸入係使用：利 用設定上述半導體記憶電路的動作模態之指令中未使用的 一部分來決定之經擴充的指令而進行者。 3 .如申請專利範圍第2項之半導體積體電路裝置，其 中上述半導體記憶電路係形成在第1半導體晶片上， 上述比較資訊及記憶動作用的輸入信號係從上述第Γ 半導體晶片的外部輸入， 由上述支援用比較電路形成的比較結果信號係輸出到 上述第1半導體晶片的外部。 4.如申請專利範圍第3項之半導體積體電路裝置，其 中更具備其他第二半導體晶片，該第2半導體晶片係包含 用以控制形成於上述第1半導體晶片的半導體記憶電路的 記憶動作之記憶體控制電路， 上述第1及第2半導體晶片係作爲一個半導體積體電 路裝置而一體封裝。 5 ·如申請專利範圍第4項之半導體積體電路裝置，其 $紙張尺度適用中國國家標準（€灿）厶4規格（210/297公釐）~" ^----II (請先閱讀背面之注意事項再填寫本頁) 訂 經濟部智慧財產局員工消費合作社印製 30- 594481 A8 B8 C8 D8 六、申請專利範圍 2 中針對形成於上述第1半導體晶片的支援用比較電路，更 設有比較有效信號輸入端子，藉此比較有效信號來控制支 援用比較電路的比較動作或其輸出動作。 6·如申請專利範圍第5項之半導體積體電路裝置，其 中設有：閂鎖上述支援用比較電路的輸出，而藉此閂鎖信 號來限制對上述半導體記憶電路的寫入動作之電路。 7 ·如申請專利範圍第5項之半導體積體電路裝置，其 中根據上述支援用比較電路的輸出來限制用以控制半導體 記憶電路的記憶動作之記憶格控制電路的動作，而使維持 在檢出後之特定存取的記憶格之記憶狀態。 8. 如申請專利範圍第6項之半導體積體電路裝置，其 中，上述第2半導體晶片含有記憶體控制器、CPU及1個 乃至多數個的信號處理電路， 上述CPU及1個乃至多數個信號處理電路係經由記· 憶體控制器來共用形成於上述第1半導體晶片的半導體記 憶電路而進行存取。 9. 如申請專利範圍第7項之半導體積體電路裝置，其 中，上述第2半導體晶片含有記憶體控制器、CPU及1個 乃至多數個的信號處理電路， 上述CPU及1個乃至多數個信號處理電路係經由記 憶體控制器來共用形成於上述第1半導體晶片的半導體記 憶電路而進行存取。 1 〇·如申請專利範圍第8項之半導體積體電路裝置， 其中對形成於上述第1半導體晶片的半導體記憶裝置分配 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) 、一st> 經濟部智慧財產局員工消費合作社印製 -31 - 594481 年-月 U J " B8 C8 1 丨·、; y L;丨 D8 _ 六、申請專利範圍 3 有：分割成分別對應於形成在上述第2半導體晶片的CPU 及1個乃至多數個信號處理電路的多數記憶區域。 ^^-I. II (請先聞讀背面之注意事項再填寫本頁) 1 1.如申請專利範圍第9項之半導體積體電路裝置’ 其中，對形成於上述第1半導體晶片的半導體記憶裝置分 配有：分割成分別對應形成在上述第2半導體晶片之CPU 及1個乃至多數之信號處理電路之多數記憶區域。 12.如申請專利範圍第10項之半導體積體電路裝置’ 其中上述CPU及1個乃至多數個信號處理電路係分別對 記憶體控制器發送動作要求信號，且接收對此之許可信號 ，而將包含分配給其本身的識別信號之記憶體存取用的信 號供應給記憶體控制器， 經濟部智慧財產局員工消費合作社印製 上述記億體控制器更包含：識別資訊的記憶電路，及 用以比較存取記憶體時所輸入的識別資訊與上述記憶電路 的識別資訊之識別資訊比較電路，當從上述第1半導體晶· 片的支援用比較電路輸出的比較結果輸出信號與上述識別 資訊比較電路的輸出信號一致時，將用以限制上述第1半 導體晶片的半導體記憶電路的寫入動作之控制信號供應給 上述第1半導體晶片。 1 3 . —種半導體積體電路裝置，其特徵係包含半導體 之記憶電路，該半導體記憶電路具備接受指令而指示記憶 動作之指令解碼器， 在上述指令解碼器中設置：可檢出對應於分配給上述 記憶動作的指令之輸入信號以外的輸入信號之功能，而使 該檢測信號能夠輸出到半導體記憶電路的外部。 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐） -32- 594481594481 S 92 · 12 V. '\ Α8 S Β8! C8 丨 a; j _ ^ _ VI. Patent application scope 1 1. A semiconductor integrated circuit device characterized by a semiconductor memory circuit, the semiconductor memory circuit includes: A comparison information latch circuit including address information and comparison information of write information is memorized; and signals corresponding to the comparison information of the above latch circuit and input signals for memorizing operations are compared, and a comparison result signal is output Support comparison circuit. 2. For example, the semiconductor integrated circuit device of the scope of the patent application, wherein the input of the comparison information of the above-mentioned comparison information latch circuit is to use: using an unused part of the instruction to set the operation mode of the above-mentioned semiconductor memory circuit. Enforcement of decisions by extended instructions. 3. The semiconductor integrated circuit device according to item 2 of the patent application range, wherein the semiconductor memory circuit is formed on a first semiconductor wafer, and the comparative information and an input signal for a memory operation are input from the outside of the Γth semiconductor wafer. The comparison result signal formed by the supporting comparison circuit is output to the outside of the first semiconductor wafer. 4. The semiconductor integrated circuit device according to item 3 of the patent application scope, further including another second semiconductor wafer, the second semiconductor wafer includes a memory operation for controlling the memory operation of the semiconductor memory circuit formed on the first semiconductor wafer. In the memory control circuit, the first and second semiconductor wafers are integrally packaged as one semiconductor integrated circuit device. 5 · If the semiconductor integrated circuit device in the scope of patent application No. 4 is applied, the paper size is applicable to the Chinese national standard (€ can) 厶 4 specification (210/297 mm) ~ " ^ ---- II (please first (Please read the notes on the back and fill in this page). Order printed by the Consumers' Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs. A comparatively effective signal input terminal is provided to control the comparison operation or the output operation of the supporting comparison circuit by the comparatively effective signal. 6. The semiconductor integrated circuit device according to item 5 of the patent application scope, which is provided with a circuit that latches the output of the above-mentioned support comparison circuit and uses the latch signal to limit the write operation to the semiconductor memory circuit. 7. The semiconductor integrated circuit device according to item 5 of the scope of patent application, wherein the operation of the memory cell control circuit for controlling the memory operation of the semiconductor memory circuit is restricted according to the output of the above-mentioned support comparison circuit, so as to maintain the detection The memory status of the memory cell accessed later. 8. For a semiconductor integrated circuit device according to item 6 of the patent application, wherein the second semiconductor chip includes a memory controller, a CPU, and one or even a plurality of signal processing circuits, and the CPU and one or more signals The processing circuit is accessed by sharing and accessing the semiconductor memory circuit formed on the first semiconductor wafer via a memory controller. 9. The semiconductor integrated circuit device according to item 7 of the scope of patent application, wherein the second semiconductor chip includes a memory controller, a CPU, and one or even a plurality of signal processing circuits, and the above CPU and one or more signals The processing circuit accesses the semiconductor memory circuit formed on the first semiconductor wafer in common through a memory controller. 1 〇 · If the semiconductor integrated circuit device of item 8 of the scope of the application for a patent, wherein the semiconductor memory device formed on the first semiconductor wafer is allocated, the paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) (please (Please read the notes on the back before filling this page), 1st > Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs-31-594481-JU UJ " B8 C8 1 丨 · ,; y L; 丨 D8 _ VI, The scope of patent application 3 is divided into a plurality of memory areas corresponding to the CPU and one or even a plurality of signal processing circuits formed on the second semiconductor wafer. ^^-I. II (please read the precautions on the reverse side before filling out this page) 1 1. If you apply for a semiconductor integrated circuit device under the scope of patent application No. 9 ', where the semiconductor memory formed on the above-mentioned first semiconductor wafer The device is divided into a plurality of memory areas corresponding to the CPU and one or even a plurality of signal processing circuits formed on the second semiconductor chip, respectively. 12. The semiconductor integrated circuit device according to item 10 of the scope of the patent application, wherein the above CPU and one or even a plurality of signal processing circuits respectively send an operation request signal to the memory controller, and receive a permission signal thereon, and The memory access signal containing the identification signal allocated to itself is supplied to the memory controller. The employee ’s cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs printed the above-mentioned controller, which also includes: a memory circuit for identifying information, and The identification information comparison circuit that compares the identification information inputted when accessing the memory with the identification information of the memory circuit, and compares the output signal of the comparison result output from the comparison circuit for supporting the first semiconductor wafer with the identification information. When the output signals of the circuits match, a control signal for restricting a write operation of the semiconductor memory circuit of the first semiconductor wafer is supplied to the first semiconductor wafer. 1 3. A semiconductor integrated circuit device, characterized in that it includes a semiconductor memory circuit, the semiconductor memory circuit is provided with an instruction decoder that accepts instructions and instructs a memory operation, and is provided in the above instruction decoder: corresponding to the allocation can be detected The function of an input signal other than the input signal of the instruction of the memory operation enables the detection signal to be output to the outside of the semiconductor memory circuit. This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) -32- 594481 14.如申請專利範圍第12項之半導體積體電路裝置， 其中，上述半導體記憶電路係同步動態隨機存取記憶體 (SDRAM) ° (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -33- 594481 第90130961號專利申請案 卩一一一 中文圖式修正頁 民國㈣2拿y气修®，正14. The semiconductor integrated circuit device according to item 12 of the scope of patent application, wherein the semiconductor memory circuit is a synchronous dynamic random access memory (SDRAM) ° (Please read the precautions on the back before filling this page) Wisdom of the Ministry of Economic Affairs The paper size printed by the Property Cooperative Consumer Cooperative is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) -33- 594481 Patent Application No. 90130961 (11) Chinese Schematic Correction Page Republic of China (2) 拿 气 修 ® ,positive 594481594481 594481 第10圖594481 Figure 10 第11圖 一比較檢出 | 保全比較發生資訊 C 至除錯程式^> 594481 月 ^.x It 2 一丨丄 第Figure 11 First comparison checkout | Security comparison occurrence information C to debug program ^ > 594481 Month ^ .x It 2 一 丨 丄 第 594481 圖 4第594481 Figure 4
TW090130961A 2001-11-22 2001-12-13 Semiconductor integrated circuit device TW594481B (en)

Applications Claiming Priority (1)

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