WO2024139915A1

WO2024139915A1 - Programming method and apparatus capable of reducing space occupation in nand flash memory device, memory, and system

Info

Publication number: WO2024139915A1
Application number: PCT/CN2023/134247
Authority: WO
Inventors: 沈嘉怡
Original assignee: 东芯半导体股份有限公司
Priority date: 2022-12-29
Filing date: 2023-11-27
Publication date: 2024-07-04

Abstract

Disclosed in the present invention are a programming method and apparatus capable of reducing space occupation in an NAND flash memory device, a memory, and a system. The programming method comprises the following steps: applying a first voltage pulse and a first verification operation to NAND cells; applying a second voltage pulse and a second verification operation to the NAND cells; applying a third voltage pulse and a third verification operation to the NAND cells; performing first column scanning on the NAND cells; applying a fourth voltage pulse and a fourth verification operation to the NAND cells; and performing second column scanning on the NAND cells. The programming method and apparatus capable of reducing space occupation in an NAND flash memory device, the memory, and the system of the present invention can save the space of the NAND flash memory device and reduce costs.

Description

Programming method, device, memory and system for reducing space in NAND flash memory device

Technical Field

The present invention relates to the field of semiconductor technology, and in particular to a programming method, device, memory and system for reducing space in a NAND flash memory device.

Background technique

With the development of semiconductor technology, flash memory with faster access speed has been developed in storage devices. Flash memory is a non-volatile memory with the characteristic that the stored information will not disappear after power failure. It has become a non-volatile memory widely used in personal computers and electronic devices. The most common types of flash memory are NOR and NAND. Compared with NOR flash memory, NAND flash memory has lower cost and larger capacity, so it is more suitable for the needs of high data storage density, such as flash drives, data storage cards, etc.

In the prior art NAND flash memory, there are three basic operations: read/program/erase. Among them, the programming operation uses incremental step pulse programming (ISPP). The ISPP process consists of three steps: programming pulse, verification operation, and global check/column scan. Usually, during the first few voltage pulses, a global check is required after the verification operation. The transistors used for the global check occupy more space in the memory. At the same time, experimental data show that almost 90% of NAND cells have been programmed during the first and second voltage pulses of the ISPP process, and only about 10% of NAND cells require more voltage pulses to complete programming.

Therefore, when performing programming operations on NAND flash memory devices, how to ensure programming success while reducing the space occupied in the memory is an urgent problem to be solved.

Summary of the invention

In view of the above-mentioned deficiencies in the prior art, an object of the present invention is to provide a programming method, apparatus, memory and system for reducing space in a NAND flash memory device, aiming to solve the problem of large space in existing NAND flash memory devices.

The technical solution of the present invention is as follows: The present invention provides a programming method, device, memory and system for reducing space in a NAND flash memory device, comprising the following steps: applying a first voltage pulse and a first verification operation to a NAND cell; applying a second voltage pulse and a second verification operation to the NAND cell; applying a third voltage pulse and a third verification operation to the NAND cell; performing a first column scan on the NAND cell; applying a fourth voltage pulse and a fourth verification operation to the NAND cell; and performing a second column scan on the NAND cell.

In one embodiment of the present invention, before performing the first column scan on the NAND cells, the method further includes: classifying the NAND cells into blocks; numbering the classified NAND cells into blocks; wherein the initial number corresponds to the first block; and adding a flag memory.

In one embodiment of the present invention, a first column scan is performed on NAND cells, including: when all NAND cells in the scanned first block are successfully programmed; marking the first block as passed, and storing the passed mark and the corresponding name of the first block in a flag memory; and scanning subsequent blocks in sequence until there are NAND cells that have failed to be programmed.

In one embodiment of the present invention, scanning all NAND cells in the first block indicates successful programming, including: marking the programmed NAND cells as successful when performing the third verification operation; scanning all NAND cells in the first block; when judging that all NAND cells are marked as successful, all NAND cells are successfully programmed.

In one embodiment of the present invention, the first column scanning of the NAND cells further includes: when scanning the NAND cells in the first block and there are NAND cells that fail to be programmed; marking the first block as failed and stopping the scanning; storing the failed mark and the name of the corresponding first block in a flag memory, so as to determine the scanning based on the failed mark when performing the second column scanning of the NAND cells; Scan the starting block position.

In one embodiment of the present invention, a second column scan is performed on the NAND cell, including: obtaining a failed mark and a corresponding block in a flag memory; determining the name of the block as the position of the starting block of the second column scan; and starting the second column scan of the NAND cell based on the position.

In one embodiment of the present invention, the fourth voltage pulse is greater than the third voltage pulse, the third voltage pulse is greater than the second voltage pulse, and the second voltage pulse is greater than the first voltage pulse.

Correspondingly, the present invention provides a programming device for reducing space in a NAND flash memory device, comprising: a first operating module, used to apply a first voltage pulse and a first verification operation to a NAND cell; apply a second voltage pulse and a second verification operation to the NAND cell; apply a third voltage pulse and a third verification operation to the NAND cell; a first processing module, used to perform a first column scan on the NAND cell; a second operating module, used to apply a fourth voltage pulse and a fourth verification operation to the NAND cell; and a second processing module, used to perform a second column scan on the NAND cell.

The present invention provides a non-volatile memory storing program instructions, wherein the program instructions, when executed, implement the steps of the programming method for reducing space in the above-mentioned NAND flash memory device.

The present invention provides a computer system, comprising: a memory for storing a computer program; and a processor for running the computer program to implement the steps of the above-mentioned programming method for reducing space in a NAND flash memory device.

As described above, the programming method, apparatus, memory and system for reducing space in a NAND flash memory device of the present invention have the following beneficial effects:

(1) Save NAND flash memory device space and reduce costs.

(2) By using a more appropriate scanning method, the scanning time of the NAND cell is reduced, thereby improving the operating efficiency of the NAND flash memory device.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a flow chart of a method for reducing space in a NAND flash memory device according to an embodiment of the present invention.

FIG. 2 is a block classification diagram of a programming method for reducing space in a NAND flash memory device according to an embodiment of the present invention.

FIG. 3 is a schematic diagram of a row scan of a programming method for reducing space in a NAND flash memory device according to an embodiment of the present invention.

FIG. 4 is a schematic diagram of the structure of a programming device for reducing space in a NAND flash memory device according to an embodiment of the present invention.

FIG. 5 is a diagram of a computer system in an embodiment of the programming apparatus for reducing space in a NAND flash memory device of the present invention.

Component number description

41 First operating module

42 First processing module

43 Second operating module

44 Second processing module

51 Processor

52 Memory

Detailed ways

The present invention provides a programming method, device, memory and system for reducing space in a NAND flash memory device. In order to make the purpose, technical solution and effect of the present invention clearer and more specific, the present invention is further described in detail below. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

The programming method, device, memory and system for reducing space in a NAND flash memory device provided by the present invention can save space in the NAND flash memory device and reduce costs; in addition, the scanning time of the NAND unit can be reduced through a more appropriate scanning method, thereby ensuring that the overall completion time of the programming operation is within the specification requirements.

As shown in FIG. 1 , in one embodiment, the programming method for reducing space in a NAND flash memory device of the present invention comprises the following steps:

Step S1, applying a first voltage pulse and a first verification operation to the NAND cell; applying a second voltage pulse and a second verification operation to the NAND cell; applying a third voltage pulse and a third verification operation to the NAND cell.

Specifically, in the programming operation of the NAND flash memory device, a high voltage is first applied to the NAND cell to apply a first voltage pulse to program the NAND cell; and a first verification operation is performed, wherein the first verification operation includes: reading data from the NAND cell to check whether it is programmed, and if it is programmed, the NAND cell is marked as successful and marked as an inhibited cell. If it is not programmed successfully, a second voltage pulse will be applied later.

Then, a second voltage pulse and a second verification operation are performed on the NAND cell. In the second verification operation, similarly, the programmed NAND cell is marked as successful and marked as an inhibited cell; the NAND cell that has not been successfully programmed will subsequently undergo a third voltage pulse application.

Then, a third voltage pulse and a third verification operation are performed on the NAND cell. In the third verification operation, similarly, the programmed NAND cell is marked as successful and marked as an inhibited cell; the NAND cell that has not been successfully programmed will subsequently undergo a fourth voltage pulse application.

It can be seen from the above steps that the ISPP process used in general programming operations consists of three steps: programming pulse, verification operation, and global check/column scan. Usually, when the voltage pulses are applied for the first few times, a global check is required after the verification operation. For example, after the first voltage pulse and the first verification operation are applied to the NAND cell, a global check is performed; then, after the second voltage pulse and the second verification operation are applied to the NAND cell, another global check is performed; the transistors applied to these global check operations occupy more space in the memory, which is not conducive to space saving and cost reduction of NAND flash memory devices; at the same time, experimental data show that almost 90% of NAND cells have been programmed during the first and second voltage pulses of the ISPP process, and only about 10% of NAND cells need more voltage pulses to complete programming. Therefore, in this scheme, after the first two voltage pulses are applied, only the verification operation is performed, and the global check operation is removed; Directly thereafter, the third voltage pulse application and the third verification operation are performed.

Step S2, performing a first column scan on the NAND cell;

Specifically, after performing the third verification operation on the NAND cells, a first column scan is performed on the NAND cells.

More specifically, before the first column scanning of the NAND cells is performed, the method further includes: classifying the NAND cells into blocks; numbering the classified NAND cells into blocks; wherein the initial numbering corresponds to the first block; and adding a flag memory.

That is, the NAND cells are classified into blocks according to columns in advance, and the classification rules can be divided equally according to the capacity of the NAND flash memory device. For example, as shown in Figure 2, in this embodiment, the block classification diagram of the present invention divides the NAND cells into 4 blocks, and the blocks are numbered as block 1, block 2, block 3, and block 4. At the same time, a flag memory is added to the NAND flash memory device to store the block number names and passed marks of the scanned NAND cells that are successfully programmed and the block number names and failed marks of the scanned NAND cells that are unsuccessfully programmed during column scanning.

During the first column scanning process, when all NAND cells in the first block are successfully programmed, the first block is marked as passed, and the passed mark and the corresponding name of the first block are stored in the flag memory; and subsequent blocks are scanned in sequence until there are NAND cells that are not successfully programmed.

More specifically, scanning all NAND cells in the first block indicates successful programming, including: marking the programmed NAND cells as successful when performing the third verification operation; scanning all NAND cells in the first block; and when judging that all NAND cells are marked as successful, all NAND cells are successfully programmed.

Further specifically, during the first column scanning process, when the NAND cells in the first block are scanned and there are NAND cells that have not been successfully programmed; the first block is marked as failed and the scanning is stopped; the failed mark and the corresponding name of the first block are stored in a flag memory for use in determining the position of the scan start block based on the failed mark when performing a second column scan on the NAND cells.

Step S3, applying a fourth voltage pulse and a fourth verification operation to the NAND cell;

Specifically, when there are NAND cells that are not successfully programmed in the first column scan, a fourth voltage pulse and a fourth verification operation are required for the NAND cells. In the fourth verification operation, similarly, the programmed NAND cells are marked as successful and marked as inhibited cells; the NAND cells that are not successfully programmed need to be subjected to the next voltage pulse application. Generally, after applying four voltage pulses, performing the fourth verification operation and the second column scan operation, all NAND cells can be programmed.

More specifically, the fourth voltage pulse is greater than the third voltage pulse, the third voltage pulse is greater than the second voltage pulse, and the second voltage pulse is greater than the first voltage pulse.

Step S4, performing a second column scan on the NAND cells.

Specifically, the failed mark and the corresponding block in the mark memory are obtained; the name of the block is determined as the position of the starting block of the second column scan; based on the position, the second column scan of the NAND unit is started.

For example, as shown in FIG3 , in this embodiment, the column scanning schematic diagram of the present invention, when in the first column scanning of the above steps, if all NAND cells in the first block are programmed successfully, the first block is marked as passed, and the passed mark and the corresponding name of the first block are stored in the flag memory, and then the scanning of the second block is continued. When scanning the NAND cells in the second block, and there are NAND cells that are not programmed successfully; the second block is marked as failed, and the failed mark and the corresponding name of the second block are stored in the flag memory, and the scanning is stopped. Thereafter, when the second column scanning is performed on the NAND cells, the name of the second block marked as failed in the flag memory is obtained, and the NAND cells are scanned starting from the second block.

As shown in FIG. 4 , in one embodiment, a programming device for reducing space in a NAND flash memory device of the present invention includes:

The first operation module 41 is used to apply a first voltage pulse and a first verification operation to the NAND cell; apply a second voltage pulse and a second verification operation to the NAND cell; and apply a third voltage pulse and a third verification operation to the NAND cell;

A first processing module 42, configured to perform a first column scan on the NAND cells;

A second operation module 43, configured to apply a fourth voltage pulse and a fourth verification operation to the NAND cell;

The second processing module 44 is used to perform a second column scan on the NAND cells.

The first processing module 42 is further used to classify the NAND cells into blocks; to number the classified NAND cells into blocks, wherein the initial number corresponds to the first block; and to add a flag memory.

The technical features specifically implemented by the apparatus for reducing space in a NAND flash memory device of this embodiment are substantially the same as the principles of the various steps in the method for reducing space in a NAND flash memory device in Example 1, and the technical contents that are common between the method and the apparatus will not be repeated.

The storage medium of the present invention stores a computer program, and when the program is executed by a processor, the programming method for reducing space in the above-mentioned NAND flash memory device is implemented.

As shown in FIG. 5 , in one embodiment, the computer system of the present invention includes a processor 51 and a memory 52 .

The memory 52 is used to store computer programs.

The processor 51 is connected to the memory 52 and is used to execute the computer program stored in the memory 52 so that the NAND flash memory device executes the above-mentioned programming method for reducing space in the NAND flash memory device.

In summary, the present invention provides a method, device, memory and system for reducing programming space in a NAND flash memory device, which removes the global check operation in the programming operation of the NAND flash memory, thereby saving NAND flash memory device space and reducing costs; and by classifying and marking NAND cells in blocks, the scanning time of NAND cells is reduced, thereby improving the operating efficiency of the NAND flash memory device.

It should be understood that the application of the present invention is not limited to the above examples. For ordinary technicians in this field, improvements or changes can be made based on the above description. All these improvements and changes should fall within the scope of protection of the claims attached to the present invention.

Claims

A programming method for reducing space in a NAND flash memory device, characterized by comprising:

Applying a first voltage pulse and a first verification operation to the NAND cell; applying a second voltage pulse and a second verification operation to the NAND cell; applying a third voltage pulse and a third verification operation to the NAND cell;

Performing a first column scan on the NAND cell;

applying a fourth voltage pulse and a fourth verification operation to the NAND cell;

A second column scan is performed on the NAND cells.
The method according to claim 1, characterized in that before performing a first column scan on the NAND cell, it also includes:

Block classification of NAND cells;

The classified NAND cells are block numbered; wherein the initial number corresponds to the first block;

Added flag memory.
The method according to claim 2, wherein the first column scanning of the NAND cell comprises:

When all NAND cells in the first block are scanned and programming is successful;

The first block is marked as passed, and the passed mark and the corresponding name of the first block are stored in the flag memory; and subsequent blocks are scanned in sequence until there is a NAND cell that is not successfully programmed.
The method according to claim 3, characterized in that the scanning of all NAND cells in the first block is successful in programming, comprising:

When performing the third verification operation, marking the programmed NAND cell as successful;

Scanning all the NAND cells in the first block;

When it is determined that the marks of all the NAND cells are successful, all the NAND cells All for programming success.
The method according to claim 2, characterized in that the first column scanning of the NAND cell further comprises:

When scanning the NAND cells in the first block and there are NAND cells whose programming fails, the first block is marked as failed and the scanning is stopped;

The failed mark and the corresponding name of the first block are stored in the flag memory, so as to be used for determining the position of the scanning start block based on the failed mark when performing the second column scanning on the NAND cell.
The method according to claim 5, characterized in that the performing a second column scan on the NAND cell comprises:

Obtaining the failed mark and the corresponding block in the mark memory;

The name of the block is determined as the position of the starting block of the second column scan;

Based on the position, the second column scan of the NAND cell is started.
The method according to claim 1 is characterized in that the fourth voltage pulse is greater than the third voltage pulse, the third voltage pulse is greater than the second voltage pulse, and the second voltage pulse is greater than the first voltage pulse.
A programming device for reducing space in a NAND flash memory device, characterized by comprising:

A first operation module is used to apply a first voltage pulse and a first verification operation to the NAND cell; apply a second voltage pulse and a second verification operation to the NAND cell; and apply a third voltage pulse and a third verification operation to the NAND cell;

A first processing module, configured to perform a first column scan on the NAND cell;

a second operation module, configured to apply a fourth voltage pulse and a fourth verification operation to the NAND cell;

The second processing module is used to perform a second column scan on the NAND unit.
A non-volatile memory storing program instructions, wherein when the program instructions are executed, the programming method of reducing space in the NAND flash memory device according to any one of claims 1 to 7 is implemented Steps of the method.
A computer system, characterized in that it comprises: a memory for storing a computer program; and a processor for running the computer program to implement the steps of the programming method for reducing space in a NAND flash memory device as described in any one of claims 1 to 7.