JP2002222600A - Test method for semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a test method for a semiconductor device in which re- designing of a test data generating circuit is not required to correspond to the row/column constitution to be tested and which can be applied easily to the other product. SOLUTION: This device is a semiconductor device comprising a test pattern generator 4 testing simultaneously RAM(A) 1, RAM(B) 2, RAM(C) 3 having different row/column constitution. The test pattern generator 4 is constituted of a RAM test control circuit 5, a write-enable generating circuit 6, a row address generating circuit 7, a column address generating circuit 8, a data generating circuit 9, or the like. Each signal line of row/column addresses corresponding to each RAM is connected respectively. Row/column addresses are shifted from the minimum value to the maximum value in order and test data is supplied commonly. Thus, data retention test by a checker board pattern is realized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to an RA for a semiconductor device.
More specifically, the present invention relates to an M (Random Access Memory) test technique, which is an effective technique applied to a semiconductor device test method suitable as a technique for simultaneously performing a data retention test using a checkerboard pattern on a plurality of RAMs having different row / column configurations at the same time. About.

[0002]

2. Description of the Related Art As a technique studied by the present inventor, the following technique can be considered with respect to a semiconductor device test method. For example, RAM-BIST (Build I
In a method of testing a RAM of a system LSI having a built-in RAM macro with n Self Test, a method of simultaneously testing a plurality of types of RAMs on the LSI is mainly used to perform a data retention test in a short time. Have been.

[0003] Techniques related to such a method of testing a semiconductor device include, for example, May 30, 1997;
Published by Press Journal, Inc. "Monthly Semicon
Ductor World Special Issue ULSI Test Technology ", pages 19 to 23.

[0004]

The inventors of the present invention have examined the above-described method for testing a semiconductor device, and as a result, have found the following. Hereinafter, a method of testing a RAM of a semiconductor device, which is a premise of the present invention, studied by the present inventors will be described with reference to FIGS.

[0005] In the data retention test as described above, in order to write to all the memory cells,
The test pattern generator generates test addresses and test data in accordance with the largest RAM among the RAMs on the LSI. Here, FIG. 5 shows RAMs (A), RAMs (B), and RAMs (C) having different row / column configurations.
An example is shown in which a checkerboard pattern test is simultaneously performed on the test pattern.

At this time, in the scan-in order by the address generation as described above, a small row-column configuration R
In AM, data is written to the same memory cell a plurality of times. For example, in the case of the RAM (B), the operation of first writing to address "00-11", returning to address "00", and writing to "00-11" is repeated three times. At this time, as shown in FIG.
The checkerboard pattern does not apply to (B) and RAM (C).

To solve this, dedicated data is generated for each RAM type. In the example of FIG.
(A), RAM (B) and RAM (C) generate dedicated test data according to their respective row / column configurations. As a result, R having different row / column configurations can be used.
The AM can also perform a checkerboard pattern test at the same time.

However, when it is necessary to generate a pattern according to the row / column configuration of the RAM to be tested, when the test pattern generator is to be applied to another LSI, it is mounted on the LSI. The data generation circuit must be redesigned according to the row / column configuration of the existing RAM.

That is, in the existing RAM-BIST,
As shown in FIG. 7, the RAMs (A) 1, RAM (B) 2, and RAM (C) 3, which are mounted on the LSI and are the test targets,
In addition to the RAM test control circuit 32, the write enable (WE) generation circuit 33 and the address generation circuit 34, dedicated test data for each RAM type is provided in the test pattern generator 31 in accordance with the row / column configuration of FIG. Data generating circuits 35 to 37 are necessary. As described above, in the case of the test pattern generator 31 requiring the dedicated data generation circuits 35 to 37, the RAM to be tested is
When the data is changed or applied to other products, the data generation circuit must be redesigned.

Therefore, the present inventor has considered a method of simultaneously testing a chucker board pattern for RAMs having different row / column configurations using common data.
In particular, focusing on the regularity of the chucker board pattern on the same column address, which has been a cause of the failure to share data, it has been found that the problem can be solved by reviewing the address scan-in order.

Therefore, an object of the present invention is to test a plurality of types of RAMs with a single test pattern generator, thereby providing a test data generation circuit according to the row / column configuration of the RAM to be tested. It is an object of the present invention to provide a method of testing a semiconductor device which can be easily applied to other products without having to redesign.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0013]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

According to the present invention, RAs having different row / column configurations are used.
When testing M at the same time, the address scan-in order is partially reviewed so that the data is matched to the RAM with the largest row address and column address, and the RAM with a smaller row / column configuration is checked. The present invention proposes a test method capable of writing or reading a board pattern. The proposed scan-in order of the addresses is reviewed for the address generation method, and the above-described address generation method is switched to the address generation method for independently generating the row address and the column address. It can be realized by connecting each to a decoder / column decoder.

That is, according to the semiconductor device test method of the present invention, a row address generating circuit for generating a row address corresponding to a plurality of RAMs having the largest row configuration and a RAM having a maximum column configuration are provided. A column address generating circuit for generating a column address;
A data generation circuit for generating data according to the largest column configuration, and a row address signal line of a row configuration corresponding to each of a plurality of RAMs to a row address generation circuit, and a column address of a column configuration Are connected to a column address generating circuit, respectively, and a plurality of RAs are connected.
A data generation circuit is commonly connected to M, and the row address generated from the row address generation circuit and the column address generated from the column address generation circuit are sequentially moved from the minimum value to the maximum value or from the maximum value to the minimum value. The data is supplied to each of the plurality of RAMs, and data generated from the data generating circuit is supplied to the plurality of RAMs in common according to the order of the row address and the column address to perform writing or reading. is there.

Therefore, according to the method of testing a semiconductor device, the test address is separated into a row address and a column address, so that the test data generating circuit is not a conventional dedicated circuit adapted to the RAM to be tested but a conventional test data generating circuit. LS
It can be common to the RAM to be tested on I. As a result, it is not necessary to redesign the test data generation circuit based on the row / column configuration of the RAM to be tested, so that application to other products is facilitated.

[0017]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 shows a semiconductor device according to an embodiment of the present invention.
FIG. 2 is a functional block diagram showing a portion M, FIG. 2 is an explanatory diagram showing a method of testing the RAM of the semiconductor device according to the present embodiment, FIG. 3 is a flowchart showing a data retention test procedure, and FIG.
FIG. 2 is a functional block diagram showing the semiconductor device of the present embodiment.

First, referring to FIG. 1, an example of a configuration of a test pattern generator and a RAM in the semiconductor device of the present embodiment will be described.

The semiconductor device according to the present embodiment has, for example, three types of RAMs (A) 1 and RAs having different row / column configurations.
A test pattern generator 4 for simultaneously testing the M (B) 2 and the RAM (C) 3 is included. The test pattern generator 4 includes a RAM test control circuit 5, a write enable (WE) generation circuit 6, a row address generation circuit 7, a column address generation circuit 8, and a data generation controlled by the RAM test control circuit 5. A write enable generation circuit 6, a row address generation circuit 7, a column address generation circuit 8, and a data generation circuit 9
(A) 1, RAM (B) 2, and RAM (C) 3 are connected to corresponding circuits, respectively. For detailed connection,
This will be described later with reference to FIG.

The RAM test control circuit 5
This circuit controls the RAM (A) 1, the RAM (B) 2, and the RAM (C) 3 to simultaneously perform a RAM test using a test pattern.

The write enable generation circuit 6 is a circuit for generating a control signal for permitting writing during a RAM test.

The row address generating circuit 7 has a RAM (A)
1, a circuit for generating a row address for designating a row direction of a plurality of memory cells arranged in a grid inside the RAM (B) 2 and the RAM (C) 3. In the row address generation circuit 7, the RAM having the largest row configuration is used.
(Here, a row address corresponding to the RAM (A) 1) is generated.

The column address generating circuit 8 includes a RAM
(A) A circuit for generating a column address for designating a column direction of a plurality of memory cells arranged in a grid inside the RAM (B) 2 and the RAM (C) 3.
In the column address generating circuit 8, the RAM having the largest column configuration (here, RAM (A) 1, RAM (C)
A column address corresponding to 3) is generated.

The data generation circuit 9 is a circuit for generating data for performing a RAM test based on a test pattern. The data generating circuit 9 generates data according to the RAM having the maximum row / column configuration (here, the RAM (A) 1), and all the RAMs (A) 1, RAM
(B) 2 and RAM (C) 3 are commonly supplied regardless of the row / column configuration.

Next, an example of a method for testing a RAM of a semiconductor device will be described with reference to FIG. In this RAM test method, a data retention test using a checkerboard pattern is performed by using a RAM (A) 1, a RAM (B) 2,
(C) An example of the case where the processing is performed simultaneously on 3 is shown. At this time, the data of the chucker board pattern is the test data (FIG. 2) matched to the RAM (A) 1 having the largest row configuration and column configuration among the RAMs to be tested.
(A)).

First, the row address for the column having the column address "00" is incremented from "00" to the maximum row address "11", and when the row address becomes the maximum, the column address is set to "01". The test target address is moved in the order of incrementing the row address “00” to “11” again.

When the address to be tested is moved in this way, for example, as shown in FIG.
Since the column address has 2 bits and the row address has 2 bits, the column address is “00” → “01” →
The movement is “10” → “11”, and the row address is “00” → “01” → “10” → “11”.

In the RAM (B) 2, since the column address and the row address have only one bit, if the column address is connected to the least significant bit, respectively, the column address becomes "00" → "01" → " The movement of “10” → “11” means the movement of “0” → “1” → “0” → “1”, and the row address “00” → “01” → “1”
The movement “0” → “11” is also “0” → “1” → “0” →
The movement is “1”.

Further, in the RAM (C) 3, although the column address has two bits, the row address has only one bit. Therefore, if the row address is connected to the least significant bit, the column address becomes "00". "→" 01 "→" 1
The movement is “0” → “11”, while the movement of the row address “00” → “01” → “10” → “11” is the movement “0” → “1” → “0” → “1”. become.

If data is written or read according to the scan-in order in the RAM (A) 1 having the largest row / column configuration, the data can be read as shown in FIG.
(B) 2 or RAM having a row configuration / column configuration smaller than the designated maximum configuration as shown in (d) and (e).
(C) A checkerboard pattern test can be performed on all three simultaneously. As a result, the data generation circuit 9 may be common to all RAMs.

Next, an example of the procedure of the data retention test described above will be described with reference to FIG.

In this data retention test, RA
RAM having the largest row configuration and column configuration at the same time for M (A) 1, RAM (B) 2 and RAM (C) 3
(A) Write test data corresponding to 1 to perform a write operation (step S1). Then, after applying the power supply voltage stress (step S2), the RAM (A) 1, R
Data is simultaneously read from the AM (B) 2 and the RAM (C) 3 to perform a read operation (step S3).

The base technology of the present invention (FIGS. 6 and 7)
Are RAM (A) 1, RAM (B) 2, RAM (C) 3
Cannot be written or read at the same time, and only the RAM (A) 1 is selected first, and then the RAM (A) 1
To the RAM (B) 2 and RA
The write operation is performed by selecting M (C) 3. Also, for the read operation, the RAM (A) 1 and the RAM (A)
Since the read operation is performed by selecting the (B) 2 and the RAM (C) 3, there is a time problem, but the method of the present embodiment can solve this problem.

Next, the configuration of an example of a semiconductor device including the above-described test pattern generator 4 will be described with reference to FIG.

The semiconductor device according to the present embodiment is a RAM-B
A system LSI having a built-in RAM macro with an IST. The above-described RAM (A) 1, RAM (B) 2, test pattern generator 4, general logics 11 to 14, general logics 11 and 12, and test pattern generator. The switching circuit includes switching circuits 15 and 16 for switching the test result No. 4, comparison test circuits 17 and 18 for comparing test results, and judgment registers 19 and 20 for storing the comparison test results. In addition,
In FIG. 4, the above-mentioned RAM (C) 3 is omitted, and the above-described write enable generation circuit 6, row address generation circuit 7, column address generation circuit 8, and data generation circuit 9 are integrated into one. This is shown as a test pattern generation circuit 21.

In this system LSI, at the time of testing, the switching circuits 15 and 16 switch from the general logics 11 and 12 to the test pattern generator 4 by a diagnostic input enable (EN) signal from the RAM test control circuit 5 to generate a test pattern. The signal generated from the device 4 is RA
M (A) 1 and RAM (B) 2 are simultaneously supplied and tested. The RAM output DO of the test result is compared with an expected value by comparison decision circuits 17 and 18 based on a decision enable (EN) signal from the test pattern generation circuit 21 to decide good / bad. 19 and 20 are stored. During normal operation, the general logics 11 and 12 on the input side and the RAMs (A) 1 and R
Data is written between the RAM (A) 2 and the RAM (A) 1 and the RAM (B) 2 and the general logic 1 on the output side.
Data reading is performed between the memory devices 3 and 14.

In this system LSI, the test pattern generator 21 of the test pattern generator 4 outputs the column address COL-A of the column address generator 8.
(0) to (3), row addresses ROW-A (0) to (3) of the row address generation circuit 7, data DI of the data generation circuit 9, a write enable signal WE of the write enable generation circuit 6, a judgment enable ( EN) signal and the like are generated and output.

The test pattern generation circuit 21 of the test pattern generator 4, the RAM (A) 1 and the RAM (B) 2
Are connected corresponding to the row / column configuration. For example, for RAM (A) 1, the column address COL
-A (0) to (3), row address ROW-A (0) to
The signal line of the address (3), the data DI, and the write enable signal WE is connected. For the RAM (B) 2, addresses of column addresses COL-A (0) to (1), row addresses ROW-A (0) to (1), and signal lines for data DI and a write enable signal WE are provided. Connected.

As described above, the RAM (A) 1 and the RAM
(B) Connect the row address signal line and the column address signal line corresponding to the RAM 2 and the RAM (C) 3, respectively, and move the row address and the column address in order from the minimum value to the maximum value to test data. , A data retention test using a checkerboard pattern can be realized.

Therefore, according to the present embodiment, by separating the test address into the row address and the column address, the test data generation circuit 9 is not a dedicated circuit adapted to the conventional RAM to be tested but a conventional circuit. This can be common to the RAM to be tested on the LSI.
As a result, it is not necessary to redesign the data generation circuit 9 according to the row / column configuration of the RAM to be tested, so that application to other products is facilitated.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment, and various modifications may be made without departing from the gist of the invention. It goes without saying that it is possible.

For example, in the above-described embodiment, the case where the row address and the column address are sequentially moved from the minimum value to the maximum value has been described, but the test is performed by sequentially moving the row address and the column address from the maximum value to the minimum value. It is also possible to supply data in common and implement a data retention test using a checkerboard pattern.

As a RAM, a DRAM or an SRA
Needless to say, the present invention can be applied to M and the like.

In particular, the present invention relates to a case where a plurality of RAMs having different row / column configurations are present on a single LSI, and a plurality of types of RAMs are to be tested by a single test pattern generator. It is effective for That is, there is one test pattern generator and different row
The present invention can be applied to a test method for realizing a test of a simultaneous checkerboard pattern of a RAM having a column configuration.

[0045]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1) By separating a test address into a row address and a column address, a plurality of types of RAMs can be tested by a single test pattern generator. There is no need to redesign the test data generation circuit according to the configuration,
Further, application to other products can be easily realized.

(2) According to the above (1), it is possible to realize a semiconductor device test method for simultaneously performing a data retention test using a checkerboard pattern on a plurality of RAMs having different row / column configurations.

[Brief description of the drawings]

FIG. 1 shows a semiconductor device according to an embodiment of the present invention.
FIG. 3 is a functional block diagram illustrating a test pattern generator and a RAM.

FIGS. 2A to 2E are explanatory diagrams illustrating a method for testing a RAM of a semiconductor device according to an embodiment of the present invention;

FIG. 3 illustrates a semiconductor device according to an embodiment of the present invention;
It is a flowchart which shows the procedure of a data retention test.

FIG. 4 is a functional block diagram illustrating a semiconductor device according to an embodiment of the present invention;

FIGS. 5A to 5E are explanatory diagrams showing a method of testing a RAM of a semiconductor device as a premise of the present invention.

FIGS. 6A to 6E are explanatory diagrams showing a method of testing a RAM of another semiconductor device which is a premise of the present invention.

FIG. 7 shows another semiconductor device which is a premise of the present invention.
FIG. 3 is a functional block diagram illustrating a test pattern generator and a RAM.

[Explanation of symbols]

 Reference Signs List 1 RAM (A) 2 RAM (B) 3 RAM (C) 4 Test pattern generator 5 RAM test control circuit 6 Write enable generation circuit 7 Row address generation circuit 8 Column address generation circuit 9 Data generation circuit 11 to 14 General logic 15 , 16 switching circuit 17, 18 comparison judgment circuit 19, 20 judgment register 21 test pattern generation circuit 31 test pattern generator 32 RAM test control circuit 33 write enable generation circuit 34 address generation circuit 35-37 data generation circuit

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G01R 31/28 Q (72) Inventor Hideki Hayashi 5-22-1, Kamizuhoncho, Kodaira-shi, Tokyo Stock (72) Inventor Takashi Kiba 5-22-1, Josuihonmachi, Kodaira-shi, Tokyo Co., Ltd. (72) Inventor of Hitachi Super-LSI Systems Co., Ltd. Person Keiichi Kunishoda 3-16, Shinmachi, Ome-shi, Tokyo F-term in the Device Development Center, Hitachi, Ltd. (Reference) 2G132 AA08 AB01 AC14 AE29 AG12 AK23 AL09 AL25 5B018 GA03 HA01 JA02 JA03 JA04 JA13 NA01 QA13 5L106 DD04 DD06 DD22 DD23 EE02 GG07

Claims (1)

[Claims] 1. A plurality of RAMs having different row / column configurations.
A test method for a semiconductor device that simultaneously performs a data retention test using a checkerboard pattern, comprising: a row address generating circuit that generates a row address according to a maximum row configuration among the plurality of RAMs; A column address generating circuit for generating a column address corresponding to a column having the largest column configuration;
A data generation circuit that generates data according to the column configuration having the maximum value; and a signal line of a row configuration row address corresponding to each of the plurality of RAMs is provided to the row address generation circuit. A signal line of a column address is connected to each of the column address generation circuits, the data generation circuit is connected in common to the plurality of RAMs, and a row address generated from the row address generation circuit and a column address generation circuit are generated. Column addresses to be sequentially moved from the minimum value to the maximum value, or from the maximum value to the minimum value, and supplied to each of the plurality of RAMs. The data generation circuit is adapted to match the order of the row address and the column address. Writing or reading by supplying data generated from to the plurality of RAMs in common, Test method wherein a and.