JPH0453100A - Memory testing device - Google Patents

Abstract

PURPOSE:To improve efficiency for analyzing the tested result of a memory to be tested on a fail memory by providing an address switcher to switch a test pattern, which is outputted from a pattern generator, to an arbitrary address train. CONSTITUTION:When a pattern generator 1 generates addresses as #0, #1, #2,...#2E, #2F, #30,..., PHIF, a tested result is outputted fro a comparing decider 3 and as outputs 41 of an address switcher 4, addresses are outputted as #0, #0, #1, #1,..., OMICRONF, OMICRONF, #08,...#3F. According to these addresses, the tested result is fetched. On the other hand, when reading this fetched data from a fail memory 5, it is enough only to generate the addresses of 0-3F from a CPU 7 and to apply those addresses through the address switcher 4 to the memory 5. Thus, even when overlapped address bits are XO and YO, the data can be fetched and read out without generating discontinuity in the storage area of the memory 5.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an IC memory testing device having means for storing defective cell locations.

[Conventional technology]

In general, IC memory testing involves improving the efficiency of analyzing test results,
Alternatively, in order to reduce the capacity of the storage device that stores the test results, the inside of the memory under test is divided into specific blocks, and the test results are compressed by overlapping processing or the like in units of the divided blocks. Figure 2 is an example of this, where the memo under test IJ2a of 64 cells is divided into four blocks of 16 cells and the four blocks are overlaid.
This is an example of cell block 2b. A known example of the prior art is JP-A-57-130295. The prior art will be explained below using FIG. 3.4.5.

FIG. 3 shows the pattern generation @i that generates the test pattern, the memory under test 2, and the expected value 1 from the pattern generator 1.
3 and the address 11 from the pattern generator 1.
address converter 8 that converts the address into an address for superimposition.
and a fail memory 5 that stores the output from the comparison/determination unit 3 in accordance with the output address 81 of the address converter 8.

Here, the address converter 8 has a function of converting multiple addresses into one address, and in the example of FIG.
This address converter 8 receives the output Y3. Mask the address bit of Y2 and set it to logic level tL.
z is fixed, and in FIG. 5, the address bits of xo and yo are masked and the address is converted to a fixed logic level "L". Becomes a bit.

) Next, the operation will be explained.

FIG. 4 is a timing diagram showing an example of actual address operation when the output 11 from the pattern generator 1 is converted by the address converter 8 and the output 81 is given to the fail memory 5. are addresses #O, #L #
2...#3F, #4O, #41)...
・, #FF is generated, and at that time, the address converter 8
The output 81 of Y3. Address # with mask on Y2
0,31. #2. ......, #3F.

#O, #1. ......, outputs #3F. Therefore, the test result for memory under test of 0 to FF words is 0 to 3F.
The data can be superimposed and imported into the word fail memory 5.

Similarly, FIG. 5 is a timing diagram showing an example of actual address operation when the output 11 from the pattern generator 1 is converted by the address converter 8 and the output 81 is given to the fail memory 5. ] is the address $0. #1.
#2. ......, #2E, #2F, $t30.・・・
..., 3FF is generated, and at that time, the output 81 of the address converter 8 is the discontinuous address #O, #O, #2゜#2, which masks yo and xo. ...#2E
, $2E, #30..., Output #EE (address #1.#3.#5.#7.....#2F,
#30. ..., #FF is an unused area),
Therefore, in the case of FIG. 5, the test results of the memory under test of 0 to FF words are superimposed and imported into the fail memory 5 of 0 to FF words, and the capacity of the fail memory 5 is equal to the memory under test. 2 and 1:1 capacity is required. In other words, even if the overlapping process is performed, the capacity of the fail memory 5 cannot be reduced.

Also, when reading the test results from the fail memory 5, it is usually read out via a device other than the pattern generating m (CPU), that is, the read address needs to be read in consideration of the address bits that were masked during storage. There is. (
When reading, addresses #0, #2. ......, #E
It recognizes that the address of E is valid and reads it. ) (Problems to be Solved by the Invention) In the above-mentioned conventional technology, as shown in FIG. 5 can be made smaller, but as shown in FIG. 5, when the bits to be masked are bits that do not include the most significant bit, there is a null bit in the output address of the address converter 8.
This causes the problem that the storage area of the fail memory 5 becomes discontinuous, making it impossible to reduce the capacity.Also, when reading out the test results, data must be read out taking into consideration the discontinuous storage area, which reduces efficiency. analysis of test results is not possible.

Therefore, the present invention provides a memory test that can import and read test results without causing discontinuity in the storage area on the fail memory, which occurs when the test results are imported into the fail memory, which is the problem mentioned above. The purpose is to provide equipment.

[Means to solve the problem]

In order to achieve the above object, a memory test device according to the present invention includes means for generating a test pattern to be applied to the memory under test, and address conversion means for rearranging the bitwise arrangement of address information output from the means into an arbitrary arrangement. and,
The present invention is characterized by comprising a storage means for storing test results of the memory under test according to address information output from the address conversion means.

According to another aspect, the memory testing device according to the present invention includes means for generating a test pattern to be applied to the memory under test, and selecting some bits of address information output from the means to generate new address information. The present invention is characterized by comprising an address conversion means for outputting, and a storage means for storing the test results of the memory under test in a superimposed manner according to the address information output from the address conversion means.

In these memory testing devices, the address conversion means further outputs second address information having a smaller number of bits than the address information given to the storage means, and
A second storage means may be provided which stores the contents of the storage means in a superimposed manner according to the address information of the storage means.

[Effect]

The address conversion means in the present invention can arbitrarily rearrange the bit arrangement of the address information output from the test pattern generation means applied to the memory under test. Therefore, only the lower bits of the rearranged address information can be used as the address information given to the storage means for storing the test results, that is, the fail memory. can be prevented from becoming Note that, as a method of rearranging the address information, the bits to be masked as described in the related art are moved to higher order.

Furthermore, when reading test results, it is no longer necessary to consider the discontinuous storage area, making it possible to efficiently analyze test results.

〔Example〕

A first embodiment of the present invention will be described below with reference to FIG. 1.5.6.

FIG. 1 is a configuration diagram of the first embodiment, in which a pattern generator 1 that generates a test pattern for the memory under test, an expected value 13 from pattern generation @1, and an output from the memory under test 2 are compared. a comparison/judgment device 3 for determining whether the pattern is good or bad; and an address rearranger 4 for rearranging the addresses 11 from the pattern generator 1 into an arbitrary arrangement.

A fail memory 5 which takes in the test result output from the comparison/judgment device 3 into the output address 41 of the address recombination device 4, and a fail memory 5 which takes in the test result output from the comparison/judgment device 3, and the contents of the fail memory 5 are transferred to the address recombination device 4.
It is configured by the CPU 7 that reads the information via the CPU 7. In this embodiment, the address recombination structure of the address recombination device 4 is to take in the output from the comparison/judgment device 3 regardless of the change in X01yo, as shown in FIG. A certain xl is rearranged as AO of the address rearranger 4, and X2 is rearranged in the same way up to A5, and a logic level 'L' is output from 6 onwards.

Next, the operation of the first embodiment will be explained. FIG. 6 is a timing chart showing an example of actual operation of the output 11 of the pattern generator 1 and the output 41 of the address recombiner 4 at that time. The pattern generator 1 sets the address to #0° #1. #2.・・・・・・
...#2E, #2F, #30. ......If #FF occurs, the test result is output from the comparison/judgment device 3, and the output 41 of the address recombination device 4 outputs the address as #FF.
O, #O, #L #1. ..., #OF, #OF
, #08. . . . outputs #3F and imports the test results using these, and when reading this imported data from the fail memory 5, outputs #3F from the CPU 7.
It is sufficient to generate an address of 4 and store it in the fail memory 5 via the address recombiner 4.

Therefore, according to the first embodiment, even if the overlapping address bits are xo and yo, data can be taken in and read out without causing discontinuity in the storage area of the fail memory 5.

Next, a second embodiment will be explained. In FIG. 8, the analysis memory 6 stores the output address 4 of the address recombiner 4.
2 and the output data 51 of the fail memory 5, and the rest is the same as in FIG. At this time, the address rearrangement configuration of the address rearranger 4 becomes as shown in FIG. That is, the output 41 gives the output address 71 of the CPU 7 to the fail memory 5 through thermal conversion, and the output 41
2 sets AO-A5 of output address 71 of CPU 7 to AO-
It will be rearranged to A3.

FIG. 9 is a timing diagram showing an example of actual operation when the contents of the fail memory 5 in FIG. #],, #2゜・・・・・・, #O
F, #1.0. #11. ..., #3F, the address recombiner 4 gives the address from the output 41 to the fail memory 5, and at the same time gives the address from the output 42.
From address 31EO, 81, #2.・・・・・・＃O
F, #O, #1. #2. ..., outputs #OF. At this time, the output 51 of the fail memory 5 outputs #1 in the 0th cycle, and the analysis memory 6 takes in the data. Continue in the same manner below. At the 16th cycle, the fail memory 5 is at address #1.
0 data is read and the analysis memory 6 is stored at address #0.
Hair is accessible.

In this cycle, the output of the fail memory 5 is #(), but #l has already been written to the address #0 of the analysis memory 6 in the Oth cycle, and #1 is left as is. Also, the contents of the address #] of the analysis memory 6 were #0 in the ]th cycle, but as #1 was read from the fail memory 5 in the ]7th cycle, the contents of the address #] of the analysis memory 6 were changed to #1. Write. Thereafter, the contents of the fail memory 5 are similarly superimposed and loaded into the analysis memory 6 until the end. In this embodiment, the fail memory 5 is accessed by the CPU, but the means for accessing is not limited to the CPU, and dedicated hardware may also be used.

Also, the fail memory 5 can be used without going through the address recombiner 4.
, and analysis memory 6 are directly accessible.

Therefore, in the second embodiment, it is possible to perform an analysis process in which the test results that have been once imported into the fail memory 5 are further subjected to superimposition processing and are then imported into the analysis memory 6.

〔Effect of the invention〕

According to the present invention, by providing an address recombiner that recombines the test pattern (address) output from the pattern generator into an arbitrary address sequence, superimposition processing, etc. Therefore, test results can be stored with a high degree of freedom without causing discontinuities in the storage area, making it possible to improve the efficiency of analyzing test results of the memory under test on fail memory.
It is possible to reduce the capacity of the storage device that stores test results.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a first embodiment of the present invention, and FIG. 2 is an explanatory diagram of a known example and the present invention. FIG. 3 is a block diagram of the known example, and FIG. 4 is an operation time chart of the known example. FIG. 5 is an operation time chart of the known example, FIG. 6 is an operation time chart of the first embodiment of the present invention, FIG. 7 is a supplementary explanatory diagram of the block diagram of the first embodiment of the present invention, and FIG. FIG. 9 is a block diagram of the second embodiment of the present invention, FIG. 9 is an operation time chart of the second embodiment of the present invention, and FIG. 10 is a supplementary explanatory diagram of the block diagram of the second embodiment of the present invention. Explanation of symbols 1...Pattern generator, 11...Test address, J
2...Test data, 13...Expected value, 2...Memory under test, 3...Comparison/judgment device, 4...Address rearranger, 41...To address rearranger fail memory Output address, 42... Output address of address recombiner to analysis memory, 5... Fail memory, 51... Output of fail memory, 6... Analysis memory, 61... Analysis Memory output, 7...CPU, 71...Output address from CPU, 8...Address converter. Jikoku 4th mark 1 month C and co(]] =
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Claims (1)

[Scope of Claims] 1) means for generating a test pattern to be applied to the memory under test; address conversion means for rearranging the bit direction of address information outputted from the means; and output from the address conversion means. 1. A memory testing device, comprising: storage means for storing test results of the memory under test according to address information. 2) means for generating a test pattern to be applied to the memory under test; and address conversion means for selecting some bits of the address information output from the means and outputting new address information. A memory testing device comprising: storage means for storing test results of the memory under test in a superimposed manner according to address information output from the address conversion means. 3) The address conversion means outputs second address information having a smaller number of bits than the address information given to the storage means, and stores the contents of the storage means in a superimposed manner according to the second address information. 3. The memory testing device according to claim 1, further comprising a storage means.