JPH11213660A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow a parameter set in a semiconductor storage device to be checked by providing monitor means for outputting an internal control signal to an output terminal in accordance with an external clock signal in a test mode. SOLUTION: A monitor mode signal ϕ is input to a NAND circuit 21 together with an internal clock signal int.CLK. After a certain time, an output signal of the NAND circuit 21 is set at a low level each time when an external clock signal EXT.CLK is set at a high level. Accordingly, it becomes possible in a monitor mode toturn on a transfer gate 25 with using the external clock signal EXT.CLK as a trigger and monitor a high-level output enable signal OEM via an NC pin 27 at a predetermined time. Thus, by monitoring a level of the output enable signal OEM which is an internal signal, it becomes possible to check whether or not a CAS latency or a burst length of an SDRAM is set at a predetermined length.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device, and more particularly, to a synchronous semiconductor memory device (hereinafter, also referred to as "SDRAM") which operates in synchronization with an external clock signal.

[0002]

2. Description of the Related Art FIG. 6 is a block diagram showing a configuration of a conventional SDRAM. As shown in FIG.
AM is an external row address strobe signal Ext. / R
AS, external column address strobe signal Ext. / C
AS, external write enable signal Ext. / WE are buffered, and the internal row address strobe signal int. RAS, internal column address strobe signal int. CAS, internal write enable signal int.
WE for generating a control signal buffer 1 and an external clock signal Ext. CLK is buffered and internal clock signal int. CLK and an external address signal Ext. Address buffer 5 for buffering Add to generate an internal address signal
, Control signal buffer 1 and clock buffer 3
And the control circuit 9 connected to the address buffer 5, the mode register 7, the memory array 11 connected to the control circuit 9, the I / O buffer 13 connected to the memory array 11, and the I / O buffer 13. And a data output terminal 15 connected thereto. Here, when outputting data from the memory array 11, the output enable signal O is output from the control circuit 9 to the I / O buffer 13.
EM is supplied.

FIG. 7 is a diagram showing a configuration of a circuit for generating an output enable signal OEM. As shown in FIG. 7, the output enable signal OEM is generated via the inverters INV1 to INV4 in response to the read signal READ output from the mode register 7.

FIG. 8 is a diagram showing a configuration of a circuit for generating a row related internal signal RASE. As shown in FIG. 8, the row related internal signal RASE is generated from the internal row address strobe signal int. Inverters INV5 and INV according to RAS
6 is generated.

[0005]

However, in the evaluation of the electrical characteristics of a semiconductor memory device, generally, there is a limit in the evaluation using an external connection terminal, and it becomes necessary to monitor a larger number of signals inside the chip. Here, a number of methods for examining signals inside the chip have been proposed so far for dynamic random access memories (hereinafter, also simply referred to as "DRAM"), but are not known for SDRAM.

Accordingly, an object of the present invention is to provide an SDRAM that can monitor internal signals of a chip in a molded state.

[0007]

According to a first aspect of the present invention, there is provided a semiconductor memory device which operates in synchronization with an external clock signal and has a normal operation mode and a test mode, and stores data. Storage means, control means for controlling input / output of data to / from the storage means, output terminal, and monitor means for outputting an internal control signal generated by the control means to an output terminal in a test mode in accordance with an external clock signal Is provided.

A semiconductor memory device according to a second aspect is the semiconductor memory device according to the first aspect, further comprising an input / output buffer connected to the storage means, and the internal control signal outputs data from the storage means. This is an output enable signal that activates the input / output buffer when it is activated.

A semiconductor memory device according to a third aspect is the semiconductor memory device according to the first aspect, wherein the internal control signal is:
This is a row-related internal signal generated in response to an external row address strobe signal.

A semiconductor memory device according to a fourth aspect is the semiconductor memory device according to the second or third aspect, wherein the mode switching means for switching the normal operation mode to the test mode in accordance with the external control signal and the address signal. Further provisions are made.

[0011]

Embodiments of the present invention will be described below in detail with reference to the drawings. In the drawings, the same reference numerals indicate the same or corresponding parts.

FIG. 1 shows an SDR according to an embodiment of the present invention.
It is a figure showing composition of AM. This SDRAM has a normal operation mode and a test mode (monitor mode).
, A control signal buffer 1, a clock buffer 3, an address buffer 5, and an internal row address strobe signal int. Connected to the control signal buffer 1 and the address buffer 5. RAS, internal column address strobe signal int. CAS, internal write enable signal int. A mode register 17 to which WE and internal address signals A7 to A10 are supplied;
Control signal buffer 1, control circuit 1 connected to clock buffer 3 and address buffer 5
9, a memory array 11 connected to the control circuit 19, an I / O buffer 13 connected to the memory array 11, a data output terminal 15 connected to the I / O buffer 13, a clock buffer 3, and a mode register. 1
7 and a NAND circuit 21 connected to the
Connected to the inverter 23 and the control circuit 19
, And an NC (no connection) pin 27 connected to the transfer gate 25.

FIG. 2 is a circuit diagram showing a configuration of a monitor mode signal φ generation circuit included in mode register 17.
As shown in FIG. 2, monitor mode signal φ generation circuit generates internal row address strobe signal int. RAS
And internal column address strobe signal int. CAS and internal write enable signal int. WE is supplied, an NAND circuit 29 connected to the NAND circuit 29, an NAND circuit 33 supplied with the internal address signals A7 to A10, a transfer gate 35 connected to the NAND circuit 33, and a transfer gate And a latch circuit 37 connected to the control circuit 35.

Here, the latch circuit 37 is connected to an inverter 37.
0 and an inverter 371, and a monitor mode signal φ is output from the output terminal of the inverter 370.

The mode register 17 has a monitor mode signal φ for monitoring the row related internal signal RASE.
1 is included. This monitor mode signal φ
1 has a configuration similar to that of the monitor mode signal φ generation circuit shown in FIG. 2 as shown in FIG.
2 is further provided.

Next, the operation of the SDRAM for outputting the output enable signal OEM generated by the control circuit 19 to the NC pin 27 in the monitor mode will be described with reference to FIG.
This will be described with reference to the timing chart of FIG.

As shown in FIGS. 4B to 4E, at time T1, the external row address strobe signal Ext. / RAS,
External column address strobe signal Ext. / CAS,
External write enable signal Ext. / WE is activated to a low level (at this time, the internal row address strobe signal int.RAS, the internal column address strobe signal int.CAS, and the internal write enable signal int.WE are all activated to a high level. )
Then, the SDRAM enters the monitor mode, and the mode register 17 generates a monitor mode signal.

At this time, the NAND shown in FIG.
The output signal of the circuit 29 becomes low level and the inverter 3
Since the output signal of No. 1 becomes high level, the transfer gate 35 is turned on. Here, if all of the internal address signals A7 to A10 are set to the high level as shown in FIG. 4G, the output signal from the NAND circuit 33 shown in FIG. 2 becomes the low level. As shown in FIG. 4 (h), the monitor mode signal φ output from the inverter 370 goes high.

As shown in FIG. 1, monitor mode signal φ is supplied from internal clock signal int. N with CLK
Since it is input to the AND circuit 21, the external clock signal Ext. Each time CLK goes high, the output signal of NAND circuit 21 goes low. Therefore, in the monitor mode, the external clock signal Ex
t. The transfer gate 25 is turned on by using CLK as a trigger, and the high-level output enable signal OEM shown in FIG. 4F can be monitored via the NC pin 27 at times T4 and T5. As shown in FIGS. 4B to 4E, the external row address strobe signal Ex
t. / RAS is activated to a low level, and external column address strobe signal Ext. / CAS and external write enable signal Ext. At time T2 when / WE is deactivated to a high level, the mode register 17 outputs a signal A.
A CT is generated. The external row address strobe signal Ext. / RAS and external write enable signal Ext. / WE is deactivated to a high level, and an external column address strobe signal Ext. At time T3 when / CAS is activated to a low level, the mode register 17 generates a signal READ. Here, as described above, the output enable signal OEM shown in FIG.
Is generated based on the signal READ as shown in FIG.

In this way, by monitoring the level of the output enable signal OEM, which is an internal signal, via the NC pin 27, it is checked whether the CAS latency and burst length of the SDRAM are set to desired values. be able to.

In the above, the output enable signal OE
Although the monitoring of the internal signal of the output system M has been described, other internal signals can be similarly monitored via the NC pin 27.

As an example, the monitoring operation of the row internal signal RASE shown in FIG. 8 in the monitor mode will be described with reference to the timing chart of FIG. As shown in FIG. 5, the operation of monitoring row related internal signal RASE is basically the same as the operation of monitoring output enable signal OEM shown in FIG.

However, monitor mode signal φ1 for monitoring row-related internal signal RASE is supplied from external row address strobe signal Ext. / RAS and external column address strobe signal Ext. / CAS and external write enable signal Ext. / WE are both activated to low level, and as shown in FIGS. 5 (g) to 5 (i), internal address signal A7 is at low level and
When the internal address signals A8 to A10 are set to the high level, they are activated to the high level. In the monitor mode in which monitor mode signal φ1 is activated to a high level, as shown in FIG. 1, monitor mode signal φ1 and internal clock signal int. CLK is NAND
Since the external clock signal Ext.
The row related internal signal RASE is monitored via the NC pin 27 with the CLK as a trigger.

Here, the row related internal signal RASE is
As shown in FIG.
CT is made high during a period from T6 to T3 from when the signal READ is generated to when the external clock signal Ext. At times T7 and T8 when CLK goes high, this high-level low-related internal signal
External monitoring is possible via pin 27.

[0025]

According to the semiconductor memory device of the present invention, the internal control signal can be monitored by using the external clock signal as a trigger, and the parameters set in the semiconductor memory device can be confirmed.

According to the semiconductor memory device of the second aspect,
It is possible to confirm whether the CAS latency and the burst length are set to desired values.

According to the semiconductor memory device of the third aspect,
It is possible to confirm whether or not the control of the row system is being performed as designed.

According to the semiconductor memory device of the fourth aspect,
Further, the internal control signal can be monitored according to a signal supplied from the outside.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an SDRAM according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a monitor mode signal φ generation circuit included in the mode register shown in FIG. 1;

FIG. 3 is a circuit diagram showing a configuration of a monitor mode signal φ1 generation circuit included in the mode register shown in FIG. 1;

FIG. 4 is a timing chart for explaining an operation of monitoring an output enable signal in the SDRAM shown in FIG. 1;

FIG. 5 is a timing chart for explaining a monitoring operation of a row-related internal signal in the SDRAM shown in FIG. 1;

FIG. 6 is a diagram showing a configuration of a conventional SDRAM.

7 is a diagram showing a configuration of a circuit for generating an output enable signal in the SDRAM shown in FIG.

8 is a diagram showing a configuration of a circuit for generating a row internal signal in the SDRAM shown in FIG. 6;

[Explanation of symbols]

3 clock buffers, 11 memory arrays, 13 I
/ O buffer, 17 mode register, 19 control circuit, 21 NAND circuit, 23 inverter, 25
Transfer gate, 27 NC pin, OEM output enable signal, RASE low system internal signal.

Claims (4)

[Claims] 1. A semiconductor memory device operating in synchronization with an external clock signal and having a normal operation mode and a test mode, comprising: storage means for storing data; and input / output of the data to / from the storage means A semiconductor memory device, comprising: a control unit for controlling an output terminal; and, in the test mode, a monitor unit for outputting an internal control signal generated by the control unit to the output terminal according to the external clock signal. . 2. The apparatus according to claim 1, further comprising an input / output buffer connected to said storage means, wherein said internal control signal is an output enable signal for activating said input / output buffer when outputting data from said storage means. 2. The semiconductor memory device according to 1. 3. The semiconductor memory device according to claim 1, wherein said internal control signal is a row-related internal signal generated in response to an external row address strobe signal. 4. The semiconductor memory device according to claim 2, further comprising mode switching means for switching said normal operation mode to said test mode according to an external control signal and an address signal.