JPH05134016A - Logic integrated circuit - Google Patents

Abstract

PURPOSE:To achieve a minimum clock period test which is smaller than a minimum test period of an LSI tester in the case of the minimum clock period test. CONSTITUTION:A title item is provided with a combination logic circuit C, a flip-flop F and a clock signal CLK of the flip-flop F, an input signal I from an LSI tester, an output signal O of DUT, a clock signal TCLK for test which is input to a flip-flop T for test for testing by changing a phase difference between the flip-flop T for test and the CLK, and an output signal TO for test which is compared and judged along with the output signal O.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic integrated circuit, and more particularly to a technique effective for AC test of the logic circuit.

[0002]

2. Description of the Related Art FIG. 5 is a block diagram of a conventional logic integrated circuit.

That is, the input signal I is logically operated by the internal combinational logic circuit C and the flip-flop F to become the output signal O. CLK is an F clock signal.

FIG. 6 is a timing chart of a minimum clock cycle test of a conventional logic integrated circuit. To perform an AC test on a conventional circuit, an LSI tester applies an input signal I and a clock signal CLK to a DUT in accordance with input data of a test pattern created for a test integrated circuit (DUT).

The output signal O is sampled by the strobe pulse S of the LSI tester and compared with the expected value data of the test pattern to determine the pass / fail.

The AC test path is I → C → F (setup), CLK → F → C → O (delay time),
If there is CLK → F → C → F (minimum clock cycle), change the phase of I or CLK and perform the test.
For, test by changing the phase of S or CLK. For, the test is performed by changing the test cycle.

[0007]

However, this conventional logic integrated circuit has a problem in that it cannot perform a minimum clock cycle test smaller than the minimum test cycle of the LSI tester.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems and provides a logic integrated circuit capable of performing a minimum clock cycle test smaller than the minimum test cycle of an LSI tester by adding a test circuit. Has a purpose.

[0009]

The logic integrated circuit of the present invention is a logic integrated circuit composed of an input signal, an output signal, a combinational logic circuit, a flip-flop and a clock signal, for testing using a critical path as an input signal. , A flip-flop, a test clock signal, and a test output signal.

Further, the invention is characterized in that there are a plurality of critical paths to be tested, which are selected by a selector to become a test output signal.

[0011]

According to the above configuration, in addition to the normal input signal, flip-flop, and output signal, the test input signal, the test flip-flop, and the test output signal are provided, and both output signals are compared and judged. , It is possible to perform a test with a minimum clock cycle that is smaller than the minimum test cycle of the LSI tester.

Alternatively, since a plurality of critical paths are selected by the selector and used as the test output signal, a more detailed test can be performed.

[0013]

The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a logic integrated circuit according to an embodiment of the present invention.

In FIG. 1, the input signal I, the output signal O, the combinational logic circuit C, the flip-flop F, and the clock signal CLK are the same as those in the prior art, but in the present invention, the test flip-flop T, the test clock signal, and T are used. Output signal TO of. Usually, a path having the longest delay time among many signal paths of a logic integrated circuit is called a critical path, but it is assumed that the critical path is known when the logic circuit is designed. For example, when the path of a-c-b of FIG. 1 is a critical path, it is input to the test flip-flop T in addition to the normal flip-flop F.

FIG. 2 is a timing chart when the minimum clock period test of the logic integrated circuit according to the embodiment of the present invention is performed.

Next, the test operation will be described.

The LSI tester applies the input signal I and the clock signal CLK to the DUT at the timing shown in FIG. 2 according to the input data of the test pattern, and the test clock signal TCLK is applied to the test flip-flop T.
Apply to.

In addition to the output signal O, the test output signal T
O is sampled by the strobe pulse S of the LSI tester and compared with the expected value data of the test pattern to determine the pass / fail. At this time, the minimum clock cycle of the path of a → c → b can be measured by changing the phase difference T _c between CLK and TCLK at the timing shown in FIG. 2 and performing the test. At this time, even if the minimum clock cycle is smaller than the test cycle T _{t of the} LSI tester, the test can be performed without any problem.

Although the embodiment of FIG. 1 shows the case where there is one T, it is of course possible to add a plurality of Ts according to the number of critical paths.

FIG. 3 is a block diagram of a logic integrated circuit according to the second embodiment of the present invention.

In FIG. 3, TP is a plurality of test flip-flops, the inputs of which are connected to the respective critical paths. If the output of T is directly output to the terminal, the number of terminals for testing increases, so that it is selected by the selector SEL and used as the testing output signal TO. SI is a control signal of SEL.

FIG. 4 is a block diagram of a logic integrated circuit according to the third embodiment of the present invention.

In this case, according to the second embodiment, a configuration is adopted in which a plurality of critical paths are first selected by the selector SEL and input to the test flip-flop TP, so comparison with the second embodiment of FIG. And flip-flop T
The number of Ps can be reduced, but the delay time of SEL is added to the delay time of the critical path, and the minimum clock period is measured.

[0025]

As described above, since the present invention includes the test flip-flop and the test clock signal, the critical path of the logic integrated circuit operating in the clock cycle smaller than the minimum test cycle of the LSI tester is minimized. It has the effect that the clock period can be measured.

[Brief description of drawings]

FIG. 1 is a block diagram of a logic integrated circuit according to an embodiment of the present invention.

FIG. 2 is a timing diagram of a minimum clock cycle test of a logic integrated circuit according to an embodiment of the present invention.

FIG. 3 is a block diagram of a logic integrated circuit according to a second embodiment of the present invention.

FIG. 4 is a block diagram of a logic integrated circuit according to a third embodiment of the present invention.

FIG. 5 is a block diagram of a conventional logic integrated circuit.

FIG. 6 is a timing diagram of a minimum clock cycle test of a conventional logic integrated circuit.

[Explanation of symbols]

 I input signal O output signal C combinational logic circuit F flip-flop CLK clock signal T test flip-flop TCLK test clock signal TO test output signal TP multiple test flip-flops SEL selector SI selector control signal

Claims (2)

[Claims] 1. An input signal, an output signal, a combinational logic circuit,
A logic integrated circuit composed of a flip-flop and a clock signal, characterized by having a test flip-flop having a critical path as an input signal, a test clock signal, and a test output signal. .. 2. The logic integrated circuit according to claim 1, wherein a plurality of critical paths to be tested are selected and selected as a test output signal by a selector.