JPH09311162A - Circuit monitoring method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a circuit monitoring method which can deal with restriction relevant to the size of a circuit board and carry out more flexible signal monitoring. SOLUTION: At the time when a signal applied to a circuit 18i in the inside of an ICi, of which the inner circuit can be programmed, such as FPGA(a field programmable gate array) is monitored through a test point TPi, of input and output terminals of the ICi, empty terminals 28i which are not used at that time are used. As compared with the case that test points are set corresponding to the input and output terminals of respective IC, the number of the test points is lessened. Moreover, since the ICi has the programmable inner circuit IC, the IC is utilized and the inner circuit 30i to connect an empty 28i and an object circuit 18i to be monitored is re-programmed based on the necessity. Though the number of the empty terminals 28i is small as compared with the numbers of the input terminals 24i and the output terminals 26i utilized at that time, of signals sent to the object circuit 18i to be monitored, all of the signals to be monitored can be monitored responding to the necessity.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to an FPGA (Field
The present invention relates to an integrated circuit such as a programmable gate array) whose internal wiring can be set or changed from the outside, and particularly to a circuit monitoring method for monitoring the operation of a part or all of the integrated circuit.

[0002]

2. Description of the Related Art FPGA is a kind of semi-custom integrated circuit (gate array), and its internal wiring can be set or changed from outside (hereinafter simply referred to as "program"). As a programming method, there are a method using an SRAM cell, a method using an EPROM, a method using an antifuse, and the like. Since at least several thousands of logic gates are built in the FPGA, it is possible for the user to custom use various logic circuits by utilizing this. Further, by mounting a plurality of FPGAs on a circuit board, it is possible to realize a logic circuit having more various functions.

FIG. 3 shows a configuration of a circuit board 10 on which n semi-custom ICs (IC1, IC2, ... ICn. N: natural number) such as FPGA are mounted. The circuit board 10 is provided with connectors J1 and J2.
1 is the wiring B1, IC1 is the wiring B2 is the IC2, and so on.
Cn, IC2, ... ICn are wirings B1, B2, ... B (n +
It is connected by 1). Furthermore, IC1, IC2,
... ICn have corresponding circuits C1, C2, ... C, respectively.
n is wiring B (n + 2), B (n + 3), ... B (2n +
It is connected by 1). The above-mentioned connectors J1 and J
Reference numeral 2 is a connector for connecting the signal generator 12 and the operation target 14, respectively. When the circuit board 10 is used, the connector J1 is the signal generator 12 and the connector J2 is another circuit or measuring instrument. Motion object 14 such as
Connect each.

The circuit board 10 shown in FIG.
Test points TP1, TP2, ... TP (2n + 1) are provided. TP1, TP2, ... TP (2n + 1)
Respectively on the wirings B1, B2, ... B (2n + 1),
The wirings W1, W2, ... W (2n + 1) are connected. TP1, TP2, ... TP (2n + 1) are IC1,
IC2 is a connection member for monitoring or measuring the operation of IC2 by the measuring device 16. That is, it is checked whether or not the circuit board 10 operates as designed, whether or not the design itself is correct, and where an operation or design error occurs (hereinafter, simply “debug”).
In general, a predetermined signal is supplied from the signal generator 12 to the circuit on the circuit board 10 via the connector J1, and an operation target is further connected to the connector J2 to supply a signal to the operation target 14. While the above is being executed, the measuring instrument 16 is connected to an arbitrary test point. FIG. 3 illustrates a state in which the measuring instrument 16 is connected to TP1. Thus, TP1, TP2, ... TP (2n +
By providing 1), the operation of IC1, IC2, ... ICn can be monitored, and its debugging can be suitably executed.

[0005]

In recent years, user-customizable ICs such as FPGAs have been increasing in scale. In other words, the number of gates provided by FPGAs and the like has increased by an order of magnitude, and as a result, the number of gates
The number of input / output terminals such as GA is also increasing. On the other hand, for circuit boards or assemblies, there is a strong demand for maintaining their sizes and miniaturizing them. Therefore, it is becoming difficult to provide a sufficient number of test points on the circuit board. In particular, it is not preferable to overlook this problem in view of the fact that the IC is becoming larger in scale as described above, and therefore the number of signals that need to be monitored during debugging and the like is increasing.

One of the objects of the present invention is to make it possible to monitor and debug the circuit function while reducing the number of test points by utilizing the characteristic of the custom IC that the user can program the internal wiring. To do.

[0007]

In order to achieve such an object, the circuit monitoring method according to the first configuration of the present invention is configured so that the internal wiring of the circuit monitoring method is programmed from the outside. A first step of connecting the monitored circuit to an empty terminal that is not currently used among a plurality of input / output terminals provided in the IC, and a second step of connecting a test point for measuring instrument connection to the empty terminal. And performing a first step and a second step, and then performing a third step of monitoring a signal applied to the monitored circuit via the test point.
That is, when using an IC, not all of a large number of input / output terminals are normally used, but generally any one of the input / output terminals becomes an empty terminal. In this configuration,
This empty terminal is used for connection with the test point. Further, since the circuit to be monitored by this configuration (monitoring target circuit) is a circuit whose internal wiring is built into an IC whose outside can be programmed, the monitoring target circuit is programmed to the internal wiring of the IC. It is possible to connect to an empty terminal that can be connected to the test point. In this configuration, by such a principle,
As a result of realizing a circuit monitor via an empty terminal, even under a situation where the number of test points is restricted due to, for example, the restriction of the area on the circuit board, the signal applied to the monitored circuit in the IC is It becomes possible to appropriately monitor. That is, according to this configuration, it becomes possible to monitor the signal with a small number of test points.

The circuit monitoring method according to the second configuration of the present invention is the circuit monitoring method according to the first configuration, in which when the number of empty terminals is smaller than the number of signals to be monitored, the signal to be monitored is smaller. Until all are monitored,
In addition, at least the first and third steps are repeatedly executed while changing the connection relationship between the monitored circuit and the vacant terminal by the program of the internal wiring. That is, the number of empty terminals among the input / output terminals of the IC is generally smaller than the number of terminals actually used for input / output of signals. Therefore, when the signal is monitored using the vacant terminals as described above, the number of vacant terminals is generally smaller than the number of signals to be monitored. In this configuration, even in such a situation,
By utilizing the above-mentioned feature of the IC that the internal wiring can be programmed, the connection relationship between the monitored circuit and the empty terminal is changed. As described above, it is possible to monitor all signals to be monitored by repeatedly executing at least the first and third steps while changing the connection relationship between the monitored circuit and the empty terminal. In this way, according to the present invention, a flexible signal monitor and thus a circuit debug can be performed.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings. In the following description, reference numerals common to those in the conventional technique shown in FIG. 3 are used.
This is because members having the same reference numeral indicate that they correspond to each other, and one member in the configuration of the present invention has the same configuration as the member having the same reference symbol in the prior art. It is not meant to be limiting.

FIG. 1 shows the configuration of a circuit board 10 according to an embodiment of the present invention. In this embodiment, T
.. TPn are directly connected to IC1, IC2, ... ICn via wirings W1, W2 ,. For this connection, the vacant terminal 28i of ICi is used as shown in FIG. 2 by taking the i-th IC as an example.
That is, among the input / output terminals of ICi, the terminals other than the input terminal 24i in use and the output terminal 26i in use, that is, the empty terminals 28i, are connected to TPi via the wiring Wi.

Further, inside the ICi, a monitored circuit 18i, for example, a control circuit having a control function realized by the ICi is connected to an empty terminal 28i by an internal wiring 30i. That is, the input buffer 2 provided corresponding to the input terminal 24i in use
0i and the monitored circuit 18i, or between the output terminal 26i in use and the output buffer 22i provided corresponding thereto, to the vacant terminal 28i by the internal wiring 30i and the monitored circuit 18i. Signal is being supplied. The internal wiring 30i is a connection formed using an SRAM cell, EPROM, antifuse, or the like.

As described above, in this embodiment, the IC
IC1, IC2, ... ICn by utilizing an unused unused terminal (28i in FIG. 2) of the input / output terminals of ICn
Since IC1, IC2, ... ICn are connected to TP1, TP2, ... TPn, the number of test points is reduced to n as compared with the conventional technique of FIG. 3 which requires 2n + 1 test points. Therefore, the area occupied by the test points on the circuit board 10 can be reduced. As a result, it is possible to preferably deal with the restriction on the area of the circuit board 10. Since the vacant terminals used for that purpose are terminals not currently used for input / output, the operation of IC1, IC2, ... ICn will not be disturbed in principle.

The reason why such an effect can be realized is that, as IC1, IC2, ... ICn, a semi-custom IC whose internal wiring is programmable from the outside, for example, an FPGA is used. That is, FIG.
The internal wiring 30i shown in can be changed as appropriate. Therefore, even when the number of empty terminals (28i in FIG. 2) is smaller than the number of signals to be measured or monitored by the measuring instrument 16, this can be easily dealt with. That is, after the monitoring by the measuring device 16 is performed on a certain part of the signals, the remaining signals (or part of them)
Regarding the above, if the internal wiring 30i is changed by a program again to execute the monitoring, it becomes possible to monitor all necessary signals among the signals applied to the monitored circuit 18i even if the number of empty terminals 28i is small. in this way,
In the present embodiment, since a more flexible monitor is possible, particularly when debugging the design of the circuit board 10 or the like, the work related to the debugging becomes easy. For example, even when a monitor is required for a signal which was not initially supposed to be monitored during debugging, this can be achieved by changing the internal wiring 30i.

In the above description, IC1, IC2,
... I assumed an FPGA as ICn, but the present invention is F
It is not necessary to limit the PGA, and the present invention can be applied to any IC whose internal wiring can be set or changed from the outside.

[Brief description of drawings]

FIG. 1 is a layout diagram showing a configuration of a circuit board according to an embodiment of the present invention.

FIG. 2 is a layout diagram showing an example of a usage status of empty terminals and a setting status of internal wiring in this embodiment.

FIG. 3 is a layout diagram showing a configuration of a circuit board according to a conventional technique.

[Explanation of symbols]

10 circuit board, 12 signal generator, 14 operation target object, 16 measuring instrument, 18i monitor target circuit, 20i
Input buffer, 22i output buffer, 24i input terminal in use, 26i output terminal in use, 28i empty terminal, 30i internal wiring, IC1, IC2, ... ICi, ... I
Cn integrated circuit, C1, C2, ... Cn circuit, TP1,
TP2, ... TPi, ... TPn Test point, W1,
W2, ... Wi, ... Wn wiring.

Claims (2)

[Claims] 1. An internal wiring is externally set or changed so that a circuit to be monitored in an integrated circuit becomes an empty terminal which is not currently used among a plurality of input / output terminals provided in the integrated circuit. After performing the first step of connecting, the second step of connecting a test point for measuring instrument connection to the empty terminal, and the first and second steps, a signal related to the monitored circuit is passed through the test point. And a third step of monitoring, which is a circuit monitoring method. 2. The circuit monitoring method according to claim 1, wherein when the number of empty terminals is smaller than the number of signals to be monitored, all the signals to be monitored are monitored and the internal wiring is changed. According to the circuit monitoring method, at least the first and third steps are repeatedly executed while changing the connection relationship between the monitored circuit and the empty terminal.