JPH09159728A - Method for testing printed board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the probability of detecting faults by separating a power supply source during the course of in-circuit tests which are conducted for detecting the fault of semiconductor parts or an element mounted on a printed board. SOLUTION: The power supply to semiconductor parts 1a can be made from a power supply source 2b through a via hole 4g for supplying electric power and an internal layer dividing area 3b for supplying electric power. The power supply source which supplies electric power to semiconductor parts 1b and 1c connected with the parts 1a is a source 2c and, at the time of conducting in-circuit tests on the parts 1a, electric power is only supplied to the source 2b from an in-circuit tester 12 by using a contact terminal for supplying electric power. Since the parts 1b and 1c are not supplied with electric power, the parts 1b and 1c do not work. Therefore, only the parts 1a can be tested, because the output data of the parts 1b and 1c are not propagated to the parts 1a.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed circuit board test, and more particularly to a test for detecting a failure of a semiconductor component or element or a test for checking disconnection of a conductor wiring pattern, from a test contact terminal to a terminal of a semiconductor component or element, and The test is performed by inputting the test data into the test contact terminal connection via holes that are connected to the conductor wiring pattern, etc., and checking the consistency by comparing the obtained output data with the expected value data prepared in advance. It is about in-circuit testing.

[0002]

2. Description of the Related Art In an in-circuit test, a semiconductor component or element failure detection test is carried out for each semiconductor component or element. In the prior art, however, since both the component under test and the wiring component are the same power source, both components operate. However, in addition to the test data from the test contact terminals, it is necessary to prevent the output of the wiring components or the output data of the bidirectional pins from being propagated to the component under test, which makes it impossible to test the semiconductor components or device units. I won't. Therefore, input the control data to the input pin (hereinafter, control pin) capable of controlling the output of the wiring component or the bidirectional pin before the test of the component under test is performed,
The output pin is fixed to High or Low level, and the bidirectional pin is set to the high impedance state to logically separate the component under test from the connected component, and the output data of the connected component is propagated to the tested component. You need not to.

However, when the control pin is connected to the device under test, the test data and output data of the device under test are propagated to the control pin when the device under test is tested, and the device connected to the connection pin is high. Alternatively, the low level cannot be fixed, and the logical separation between the component under test and the connection component cannot be maintained. Also, when the control pin is directly connected to the power supply or the ground, if the value of the control data is opposite to the value of the directly connected power supply (High level) or ground (Low level), the control data cannot be input and logically separated. Cannot be achieved. If control data cannot be correctly input to the control pins and logical separation cannot be achieved in this way, the semiconductor component or device cannot be tested. Therefore, in order to prevent the test data and the output data from the component under test from propagating to the control pin, it is necessary to add a semiconductor component or element which is not necessary in the normal operation on the printed board. In order to prevent the direct connection to the power supply or the ground, it is necessary to add a component or element for enabling logical separation such as addition of a resistance element. The conventional technique is described in, for example, Japanese Patent Laid-Open No. 213000/1993.

[0004]

The above-mentioned prior art has not taken into consideration the fact that when the printed circuit board is tested by the in-circuit test, the semiconductor component or element is tested after the logical separation. . as a result,
When a logic design is performed that does not allow logical separation between the tested component and the connected component such as connecting the control pin to the tested component or directly connecting to the power supply or ground, the logic of each mounted semiconductor component or element It is impossible to perform a test to detect the failure of semiconductor parts or elements, and the addition of parts or elements to prevent the connection of the control pin to the tested part or the direct connection to the power supply or the ground is fast. There is a problem that it is difficult to deal with a logic printed circuit board and a high-density mounting printed circuit board. The present invention has been made in view of the above-mentioned problems of the prior art. The printed circuit board is provided with a separate power supply source and a separate power supply line for each of the component under test and the connection component, and the component under test is tested during an in-circuit test. By supplying power only and not operating the wired components, the output data of the wired components is prevented from propagating to the tested components, and the tested components are placed in a state equivalent to the state where they are logically separated from the wired components. It enables a failure detection test of a semiconductor component or element in the above.

[0005]

[Means for Solving the Problems] Separate power supply sources for a component under test and a connection component are provided in a plug portion of a printed circuit board, etc., and a conductor wiring pattern and an inner layer connection for power supply are connected to the power supply source. An independent power supply line is provided by using a hole, a power supply inner layer division area, or the like.

During the in-circuit test, the in-circuit tester, which is a device for performing the in-circuit test, supplies power only to the power supply source of the component under test.
No power is supplied to the wiring parts. As a result, since the wired component does not operate, the output data of the wired component does not propagate to the device under test. In other words, this is equivalent to a state in which the tested component and the connected component are logically separated, and the above problem is solved.

With the above structure, the failure detection test of the semiconductor component or element cannot be performed due to the logical configuration in which the logical separation is impossible, or the addition of the component or the element for enabling the logical separation is added. Since it is not necessary, it leads to a reduction in design period and cost. Even during the in-circuit test, the failure detection test of semiconductor parts or elements can be performed regardless of the addition or non-addition of parts or elements for achieving the logical configuration or logical separation. In addition, the conventional test device such as a jig for in-circuit test can be used as it is.

[0008]

1 and 2 show an embodiment of the prior art, and FIGS. 3 and 4 show an embodiment of the present invention. The printed circuit board includes a component mounting surface 11, a solder coating surface 10, and a power supply inner layer 9. In the failure detection test of the semiconductor component or element of the in-circuit test, power is supplied from the in-circuit tester 12 using the power-supplying contact terminals 6g to 6i, and then the component under test (eg, semiconductor component 1a) is connected. (Example: semiconductor components 1b, 1c) are logically separated from each other.

In the embodiment of the prior art, when the component to be tested is a semiconductor component 1a as shown in FIGS. 1 and 2, contact terminals 6a to 6c for power supply from the in-circuit tester 12 are used for the power supply sources 2a to 2c. Since the power is supplied to the semiconductor components 1a to 1e via the power supply via holes 4a to 4f and the power supply inner layer divided region 3a, the semiconductor components 1b and 1c connected to the semiconductor component 1a are Operate. Therefore, in order to prevent the output data output by the operation of the semiconductor components 1b and 1c from propagating to the semiconductor component 1a, the semiconductor component 1a and the semiconductor devices 1b and 1c must be logically separated. However, the semiconductor component 1b
The control pin 14b is connected to the semiconductor component 1a which is the component under test by the logic signal net 16a, and the test data of the semiconductor component 1a is propagated. Therefore, test data is input to the control pin 14b of the semiconductor component 1b in addition to the control data, and the semiconductor component 1a and the semiconductor component 1 are
b cannot be logically separated. Further, the control pin 14c of the semiconductor component 1c is directly connected to the power supply net 15a (High level) via the logic signal net 16e, and although the Low level cannot be input, the control data is Lo.
At the w level, the semiconductor component 1a and the semiconductor component 1c cannot be logically separated. That is, the semiconductor component 1a and the semiconductor component 1b may not be logically separated, and the semiconductor component 1a and the semiconductor component 1c may not be logically separated, which makes the failure detection test of the semiconductor component 1a impossible. Even when the component under test is the semiconductor component 1b, power is supplied to the semiconductor components 1a to 1e in the same manner as the semiconductor component 1a, so that the semiconductor components 1a and 1e connected to the semiconductor component 1b operate. Therefore, in order to prevent the output data output by the operation of the semiconductor components 1a and 1e from propagating to the semiconductor component 1b, the semiconductor component 1b and the semiconductor devices 1a and 1e must be logically separated. The control pin 14a of the semiconductor component 1a is not connected to the semiconductor component 1b, which is the component under test, and the test data does not propagate. Therefore, only the control data is input to the control pin 14a of the semiconductor component 1a, and the semiconductor component 1b and the semiconductor component 1a can be logically separated. However, the control pin 14d of the semiconductor component 1e
Is directly connected (High level) to the power supply net 15a via the logic signal net 16f, and Lo
Although the w level cannot be input, if the control data is the Low level, the semiconductor component 1b and the semiconductor component 1e cannot be logically separated. That is, although the semiconductor component 1b and the semiconductor component 1a can be logically separated, the semiconductor component 1b and the semiconductor component 1e may not be logically separated, and the failure detection test of the semiconductor component 1b may be impossible.

Therefore, in the embodiment of the present invention, when the component under test is the semiconductor component 1a as shown in FIGS. 3 and 4, first, the power supply source 2b is supplied from the in-circuit tester 12 to the power supply contact terminal 6e. Is used to supply power, and power is supplied only to the semiconductor component 1a via the power supply via hole 4h and the power supply inner layer division region 3c, so that the semiconductor components 1b and 1c connected to the semiconductor component 1a operate. do not do. As a result, the output data of the semiconductor components 1b and 1c are not output, so that the output data is not propagated to the semiconductor component 1a, and the state becomes equivalent to the state where the logical separation is achieved. Next, a test for detecting a failure can be performed by inputting / outputting test data from the test contact terminals 7a to 7d to the test contact terminal connection through holes 5a to 5d and collating it with expected value data. When the component under test is the semiconductor component 1b, first, power is supplied from the in-circuit tester 12 to the power supply source 2a using the power supply contact terminal 6d, and the power supply via holes 4g, 4j and the power supply inner layer are divided. Since power is supplied to the semiconductor components 1b to 1d via the region 3b, the semiconductor component 1 connected to the semiconductor component 1b is connected.
a and 1e do not work. As a result, the semiconductor components 1a, 1
Since the output data of e is not output, the output data does not propagate to the semiconductor component 1b, and the state becomes equivalent to the state where logical separation is achieved. Next, from the test contact terminals 7b to 7c, 7f to the test contact terminal connection via hole 5b.
A failure detection test can be performed by inputting / outputting test data to 5c and 5f and collating with expected value data. The semiconductor components 1c and 1d that are simultaneously supplied with power by supplying power to the semiconductor component 1b operate, but are not connected to the semiconductor component 1b and the output data of the semiconductor components 1c and 1d do not propagate to the semiconductor component 1b. , It can be operated by supplying power.

As means for supplying power to the semiconductor parts or elements mounted on the printed circuit board, contact terminals for power supply from the in-circuit tester, power supply sources, via holes for power supply, inner layer dividing regions for power supply are provided. In addition to the means for passing through, through the in-circuit tester 12 without using the power supply inner layer divided region like the semiconductor component 1e, the power supply source 2c, the power supply contact terminal 6f, the conductor wiring pattern 13
There is a means to do it via. The distribution of the power supply source is performed by connecting the semiconductor components 1a and 1b or the semiconductor components 1 which are connected to each other.
It is possible to improve the efficiency by distributing d and 1e separately and distributing the semiconductor components 1b to 1d which are not connected to each other as the same power supply source. As shown in FIG. 4, the semiconductor component 1a has a power supply net 15b (= power supply source 2b).
(FIG. 3)), the power supply net 15c (= power supply source 2a (FIG. 3)) to the semiconductor components 1b to 1d, and the power supply net 15d (= power supply to the semiconductor component 1e). Source 2c (FIG. 3)) to distribute semiconductor component 1
It is possible to carry out a failure test of the semiconductor component or the device with three types of power supply sources and power supply lines for the five semiconductor components a to 1e.

During normal operation of the printed circuit board, the plug portion 8 is connected to an external device, and the power supply sources 2a ...
Since power is supplied to all 2c at the same time, all semiconductor components 1a to 1e mounted on the printed circuit board are supplied with the same power as the conventional printed circuit board.

[0013]

As described above, according to the present invention, a logic design capable of logically separating a component under test and a wiring component,
No additional components or elements are required to enable logical isolation, and semiconductor components or elements can be reliably placed in a state equivalent to logical isolation, which shortens the design period, reduces costs, and reduces test man-hours. It is effective in reducing and improving the probability of detecting a failure.

[Brief description of the drawings]

FIG. 1 is a perspective view of a printed circuit board of an embodiment of a conventional invention.

FIG. 2 is a schematic diagram of a logic circuit on a printed circuit board according to an embodiment of the conventional invention.

FIG. 3 is a perspective view of a printed circuit board according to an embodiment of the present invention.

FIG. 4 is a schematic diagram of a logic circuit on a printed circuit board according to an embodiment of the present invention.

[Explanation of symbols]

1a to 1e ... Semiconductor parts, 2a to 2c ... Power supply source, 3a to 3c ... Power supply inner layer division region, 4a
~ 4j ... power supply via hole, 5a ~ 5f ... test contact terminal connection via hole, 6a ~ 6f ... power supply connection terminal,
7a to 7f ... connection terminal for test, 8 ... plug portion,
9 ... Power supply inner layer area, 10 ... Solder application surface, 11 ... Component mounting surface, 12 ... In-circuit tester, 13 ... Conductor wiring pattern, 14a-14d ... Control pins, 15a, 15
a-1 to 15a-2, 15b to 15c ... Power supply net, 16a to 16d ... Logic signal net.

Claims (1)

[Claims] 1. A failure of a semiconductor component or an element is detected in a printed wiring board which is composed of a conductor wiring pattern for interconnecting a semiconductor component or element mounted on a printed board and an electronic component, a conductor pad, and a through hole. In order to facilitate the test, the semiconductor parts or elements to be tested (hereinafter referred to as "tested") are used by using the plug-in section or connector which is the power supply source for the entire printed circuit board, the wiring pattern, the via hole, and the power supply inner layer division area. The power supply source and the power supply line of the semiconductor component or element (hereinafter, wiring component) connected to the component) and the device under test are separated (do not supply the same power).
This method uses a printed circuit board that supplies power to the parts under test and does not supply power to the connected parts.