JP2007271346A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit improving malfunction detection rate of a memory cell peripheral circuit at low power consumption. <P>SOLUTION: The semiconductor integrated circuit coping with scan test including scan cells 302, 316 for application of a test signal, scan cells 307, 319 for outputting the test signal, and a memory cell 301 includes a bypass path circuit 317 that is a circuit between an input terminal and an output terminal of the memory cell 301 and provided outside the memory cell 301, a mode setting means 60 for setting the memory cell 301 into a transparent mode or a bypass path mode, and a selection means 65 for selecting an output of the bypass path circuit 317 and an output of the memory cell 301 set by the mode setting means 60. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit that improves the failure detection rate of a peripheral circuit of a memory cell and performs with low power consumption.

  Large scale integration (LSI: Large Scale Integration) represented by ASIC (Application Specific Integrated Circuit) etc. is accelerating as internal circuits become more complex, dense and highly integrated. Along with the progress of semiconductor technology, various methods of shipping inspection (test) technology for manufactured LSIs have been proposed.

  For testing large-scale integrated circuits (hereinafter referred to as “LSI”), the test data generated by the test pattern generator (TPG) is input to the circuit under test (CUT). The output analysis (ORA: Output Response Analyzer) determines whether the output from the circuit to be inspected (hereinafter referred to as “CUT”) matches the expected value that is a normal pattern. Broadly divided, external test using an external tester such as LSI tester and built-in self test (BIST: Built-In Self Test) using a simple tester mounted on the chip. )

  In addition, the failure model handled in the test process for carrying out the above-mentioned LSI test cannot be handled uniformly considering the cause of the failure that may occur in the manufacturing process, but it is generally said that the stuck-at fault model is applied. It is recognized that it is practically sufficient.

  For this reason, in the test process for manufactured LSIs, attention has been focused on techniques for improving fault coverage and reducing test costs for stuck-at faults, and considering the improvement of fault coverage and cost reduction from the logic design stage. Various design for testability (DTF) methods for facilitating the shipping test have been proposed. The design method corresponds to a scan test, which is a test method for inspecting stuck-at faults in a circuit, and a scan cell consisting of D flip-flops at the front and rear stages of the CUT, which is the logic circuit inside the LSI. There is a logic scan design method in which a failure is detected in a logic circuit in an LSI by providing a (or scan register), adding a test circuit therebetween, and outputting the state of an internal element to the outside.

  An LSI designed by such a method uses an LSI tester to input a test pattern generated by an ATPG (Automatic Test Pattern Generation) tool from an external terminal in the test process. Observe the internal CUT and as a result, detect stuck-at faults.

  Therefore, in testing LSIs with multiple memory cells, if the test is performed without taking measures (test circuit addition) corresponding to the test method in the test process for the memory cell peripheral circuit, The memory cell is treated as a black box, and the memory cell peripheral circuit related to the output data from the memory cell is called a shadow logic (a circuit in which failure cannot be detected), which is a logic cone that cannot be controlled and observed from an external terminal. (Combination circuit having FF as a vertex) exists, and the failure detection rate of the memory cell peripheral circuit is lowered.

  Therefore, as a countermeasure against memory cell peripheral circuits, address input signals are aggregated using a combinational circuit that consists of a plurality of exclusive OR (XOR) circuits in a tree shape for address input. There is a way to observe. For data input / output, data input using a bypass path circuit that bypasses the data input to the memory cell from the input terminal to the output terminal of the memory cell while the memory cell is stopped. Signal observation method, address data input to memory cell address terminal, signal input to write enable (WEN) terminal and chip enable (CEN) terminal, clock CLK (clock) terminal By controlling the system clock input to the memory cell, there is a method of observing data input / output signals by operating as a transparent mode in which the input data of the memory cell is sequentially read as output data after a certain time.

  Considering semiconductor technology in recent years, when a test is simultaneously performed on a plurality of memory cells mounted on an LSI, the circuit activation rate during the test execution is high, and the test is not possible due to power consumption, current, heat, etc. Since there is a problem of stability, it is necessary to reduce power consumption during testing and perform testing in a stable state. Therefore, as to which of the above two methods is used as a test measure, a bypass path circuit that can perform a test with the memory cell stopped is used.

  However, in the test of the peripheral circuit of the memory cell, the method of using the bypass path circuit is the selection in the circuit that selects the output data from the memory cell, the terminal that takes in the output data from the memory cell, and the data that bypasses the memory cell. The failure of the node to which the signal is input cannot be detected, and the circuit that selects the output data from each memory cell and each data that bypasses the memory cell has as many test points as there are output terminals, so an undetected failure There is concern that the number of locations will increase.

  On the other hand, in the method of operating the memory cell in the transparent mode, since the memory cell is operated in the transparent mode, the signal input to the address input terminal of the memory cell is fixed to 0, so that it can be distinguished from 0 stuck-at fault. Therefore, the failure detection rate of the peripheral circuit relating to the address input of the memory cell is lowered. In consideration of power consumption and stability during testing, the system clock and chip that are input to the memory cell clock (hereinafter referred to as “CLK”) terminal are used so that all memory cells mounted on the LSI are not operated simultaneously. When a test is performed by controlling a signal input to an enable (hereinafter referred to as “CEN”) terminal and operating only a specific memory cell, the stopped memory cell becomes shadow logic. This reduces the failure detection rate of the memory built-in self test (hereinafter referred to as “memory BIST”), which tests using a circuit that captures the data output into a single comparator.

  An object of the present invention is to provide a semiconductor integrated circuit which improves the failure detection rate of a peripheral circuit of a memory cell and performs with low power consumption in view of the problems of the conventional technology.

  To achieve the above object, a semiconductor integrated circuit according to the present invention is a semiconductor integrated circuit corresponding to a scan test having a scan cell for applying a test signal, a scan cell for outputting a test signal, and a memory cell, A circuit between an input terminal and an output terminal of the memory cell, a bypass path circuit provided outside the memory cell, and mode setting means for setting the memory cell to a transparent mode or a bypass path mode; Selection means for selecting the output of the bypass path circuit and the output of the memory cell set by the mode setting means can be provided. The scan cell includes a scan register.

  As a result, the semiconductor integrated circuit of the present invention can select whether to perform a test using a bypass path circuit or to perform a test as a transparent model, improve the fault detection rate of the peripheral circuit of the memory cell, and reduce the consumption. Tests can be done with electricity.

  In order to achieve the above object, the semiconductor integrated circuit of the present invention temporarily holds an instruction code that indicates whether the bypass path mode or the transparent mode is used for each memory cell. An instruction register, an instruction decoder for decoding an instruction code held in the instruction register, and a mode setting signal register for temporarily holding a mode setting signal corresponding to the memory cell decoded by the instruction decoder The mode setting signal register can be read out during a test scan.

  Thus, the semiconductor integrated circuit of the present invention can control whether to perform a test using a bypass path circuit or a test as a transparent model for each memory cell.

  In order to achieve the above object, the semiconductor integrated circuit of the present invention has selection signal generation means for generating a selection signal for the selection means, and the selection signal generation means is connected to the mode setting signal register. The test signal may be supplied to the selection unit based on the read mode setting signal.

  As a result, the semiconductor integrated circuit according to the present invention uses data that is used when testing memory cell input / output data in a mode using a detour path circuit (hereinafter referred to as a “detour path mode”) and a transparent mode. The signal can be selected between the data signal from the bypass path circuit and the data signal output from the memory cell.

  In order to achieve the above object, the semiconductor integrated circuit of the present invention has address setting means for setting an address for the memory cell, and the address setting means is read from the mode setting signal register. Further, the test signal can be configured as address input data of the memory cell based on the mode setting signal.

  Thus, the semiconductor integrated circuit of the present invention can input a test signal as an address value of the memory cell, and can control input data to the address according to the operation mode setting of the memory cell.

  In order to achieve the above object, the semiconductor integrated circuit of the present invention has operation control signal supply means for supplying a control signal for controlling the operation of the memory cell to a chip enable terminal of the memory cell, The operation control signal supply means can be configured to supply the control signal to the chip enable terminal of the memory cell based on the mode setting signal read from the mode setting signal register.

  Accordingly, the semiconductor integrated circuit of the present invention can perform data writing to the memory cell and operation control of the memory cell, and can operate the memory cell in a transparent mode.

  In order to achieve the above object, a semiconductor integrated circuit according to the present invention has clock inversion means for inverting a clock, and the clock inversion means reads the mode setting signal read from the mode setting signal register. Based on the above, the clock can be inverted.

  Thus, the semiconductor integrated circuit of the present invention can invert the clock signal, and can input the inverted clock signal to the CLK terminal of the memory cell during the transparent mode operation. Data input to the cell can be read sequentially.

  The present invention can provide a semiconductor integrated circuit that improves the failure detection rate of the peripheral circuit of the memory cell and performs with low power consumption.

  DESCRIPTION OF EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

  First, a circuit configuration in the case of using a bypass path circuit, which is a test countermeasure method in a memory cell peripheral circuit, will be described.

  FIG. 1 is a diagram showing a configuration example of a memory cell peripheral circuit using a memory cell 101 and a bypass path circuit in an LSI according to the present invention.

  The memory cell 101 is a RAM (Random Access Memory) that stores data using a sequential circuit such as a flip-flop (Flip Flop) or a synchronous SRAM (Static Random Access Memory).

  The memory cell 101 has an address input terminal n + 1 bit (A0 to An), a data input terminal n + 1 bit (Di0 to Din), a data output terminal n + 1 bit (Do0 to Don), and a write enable (WEN: write). enable) terminal, CEN terminal, and CLK terminal.

  The memory cell 101 becomes operable (low active) when a 0 (L: Low) signal is applied to the CEN terminal. The memory cell 101 can write data when a 0 (L) signal is applied to a write enable (hereinafter referred to as “WEN”) terminal. Further, the memory cell 101 is always operable in a read enable (REN).

  In the memory cell 101, when CEN and WEN are low active, a clock signal is applied to a clock (hereinafter referred to as “CLK”) terminal and a data signal is applied to a data input terminal (Di0 to Din). Data is written and stored in the memory. The memory cell 101 can read stored data from the data output terminals (Do0 to Don) when an address input signal is applied to the address input terminals (A0 to An) when CEN is low active. .

  Next, the memory cell peripheral circuit in the LSI includes a bypass path circuit 108, scan cells (including scan registers) 102, 104, 105, 107, 110, selection circuits (MUX: multiplexers) 106, 109, and a combinational circuit 103. It has.

  The bypass path circuit 108 is a circuit between the data input terminals (Di0 to Din) and the data output terminals (Do0 to Don) of the memory cell 101, and is configured to bypass the memory cell 101. The bypass path circuit 108 outputs the data human power signal to a circuit subsequent to the memory cell 101.

  The scan cells 102, 104, 105, 107, and 110 were applied by a D flip-flop (hereinafter referred to as “D-FF”) having an input terminal (D), an output terminal (Q), and a CLK terminal. The signal can be temporarily held, and the held signal can be output as a clock signal. Further, the scan cells 102, 104, 105, 107, and 110 are used as test signal application (control) and signal output (observation) destinations after the test when performing address input and data input / output tests. In the address input test, a test signal is applied to the scan cell 102 and a signal after the test is output to the scan cell 104. In the data input / output test, a test signal is applied to the scan cell 107 and a signal after the test is output to the scan cell 110. The scan cell 105 is applied with a control signal for inputting to the WEN terminal and the CEN terminal.

  The selection circuits (hereinafter referred to as “MUX”) 106 and 109 each have a plurality of input terminals, a control signal input terminal, and an output terminal. Two or more input signals can be used as input control signals. A circuit that selects and outputs as one signal.

  The MUX 106 switches a signal to be applied to the WEN terminal and CEN terminal of the memory cell 101 based on a signal for controlling the operation switching of the memory cell peripheral circuit during the test and the normal operation.

  The MUX 109 is output from a signal output from the detour path circuit 108 and a data output terminal (Do0 to Don) of the memory cell 101 based on a signal for controlling switching of the operation of the memory cell peripheral circuit between the test and the normal operation. The signal is switched and output.

  The combinational circuit 103 is a combinational circuit in which a plurality of exclusive OR (hereinafter referred to as “XOR”) circuits are configured in a tree shape. The combinational circuit 103 collects address input signals.

  Next, the memory cell 101 and the memory cell peripheral circuit using the bypass path circuit are controlled by the ATPGEN signal, the SCANEN signal, and the SYSTEM_CLK signal.

  The ATPGEN signal is a signal that controls the operation switching between the test and normal operation in the memory cell peripheral circuit. When the ATPGEN signal is 1 (H), the test state is entered. When the ATPGEN signal is 0 (L), Control to transition to the normal operation state. The ATPGEN signal is applied to the control signal input terminals of the MUXs 106 and 109.

  The SCANEN signal is a signal that controls the operation of the memory cell 101. When the SCANEN signal is 1 (H), the memory cell 101 can be stopped, and when the SCANEN signal is 0 (L), the memory cell 101 can be written. Control to transition to a different operating state. The SCANEN signal is applied to the input terminal of the MUX 106. When the ATPGEN signal is 1 (H), the SCANEN signal is applied to the WEN terminal and the CEN terminal of the memory cell 101.

  The SYSTEM_CLK signal is a system clock signal. The SYSTEM_CLK signal is applied to the CLK terminal of the memory cell 101 that operates in synchronization with the system clock.

  Hereinafter, the flow of the test operation by the method using the bypass path circuit 108 will be described.

  First, in a method using a bypass path circuit, a 1 (H) ATPGEN signal indicating a test state is issued and applied to the control signal input terminals of the MUXs 106 and 109. Next, in order to perform the test with low power consumption, the SCANEN signal of 1 (H) is issued and the SYSTEM_CLK signal of 0 (L) is issued. As a result, the SCANEN signal is selected by the MUX 106 based on the 1 (H) ATPGEN signal, the 1 (H) SCANEN signal is applied to the WEN terminal and the CEN terminal of the memory cell 101, and the CLK terminal of the memory cell 101 Is applied with a SYSTEM_CLK signal of 0 (L), and the operation of the memory cell 101 is stopped.

  In the test of the memory cell peripheral circuit related to address input, test signals applied to the scan cell 102 as address input data are aggregated by the combinational circuit 103, and the aggregated signal is observed by the scan cell 104. Is equal to the expected value of the normal pattern.

  In the test of the memory cell peripheral circuit related to input / output data using the bypass path circuit 108, the test signal applied to the scan cell 107 as input data is applied to the input terminal of the MUX 109 via the bypass path circuit 108. , 1 (H) based on the ATPGE signal, the applied test signal is selected by the MUX 109, and the selected test signal is output from the output terminal of the MUX 109. Thereafter, the test signal output from the MUX 109 is applied to the scan cell 110 via a combinational circuit at the subsequent stage, and it is determined whether or not the signal observed by the scan cell 110 matches the expected value of the normal pattern. To do.

  As described above, the method using the detour path circuit 108 can perform the test with low power consumption.

  However, in the method using the bypass path circuit 108, the output data from the memory cell 101 and the path between the output terminal of the memory cell 101 and the input terminal of the MUX 109 in the peripheral circuit downstream of the memory cell 101 related to input / output data, The input terminal for the ATPGEN signal in the MUX 109 is not tested and failure detection is not possible. In addition, since there are as many MUXs 109 as there are paths between the output terminals of the memory cell 101 and the input terminals of the MUX 109, there is a problem in that the number of undetected faults increases.

  Next, a circuit configuration in the case of using the transparent mode which is a test countermeasure method in the memory cell peripheral circuit will be described.

  First, the transparent mode will be described.

  In the transparent mode, signals applied to the address input terminals (A0 to An), WEN terminal, CEN terminal, and CLK terminal of the memory cell 201 are controlled and input to the data input terminals (Di0 to Din) of the memory cell 201. Data is temporarily stored (capture operation), and data is output (shift operation) sequentially from the data output terminals (Do0 to Don), and operates in synchronization with the clock signal. It is. Therefore, in the transparent mode, the memory cell 201 is operated like a buffer cell.

  FIG. 2 is a diagram showing a configuration example of the memory cell 201 and the transparent mode memory cell peripheral circuit in the LSI according to the present invention.

  The configuration of the memory cell 201 and the memory cell peripheral circuit in FIG. 2 is different from the configuration of the circuit in FIG. 1 in that there is no bypass path circuit 108 for bypassing input data and MUX 109 for selecting output data, and the memory cell 201 is set in a transparent mode. As shown in FIG. 2, the scan cells (including scan registers) 202, 206, 207, 211, 212, MUX 208, and combinations included in the memory cell 201 and the memory cell peripheral circuit in FIG. The circuit 205 is the same as the scan cells 102, 104, 105, 107, 110, the MUX 106, and the combinational circuit 103 shown in the configuration example of FIG.

  Therefore, in the description of FIG. 2, description of the same configuration example as in FIG. 1 is omitted, and only the added circuit in the method using the transparent mode will be described.

  Memory cell peripheral circuits in the LSI include scan cells (including scan registers) 202, 206, 207, 211, 212, MUX 208, 210, combinational circuit 205, inverting (NOT) circuits 203, 209, and logical product (AND). A circuit 204 is provided.

  A logical product (hereinafter referred to as “AND”) circuit 204 performs a logical product operation on an input signal and outputs a result of the operation. The circuit 204 is provided in front of each address input terminal (A0 to An). Yes. The AND circuit 204 performs an AND operation between an address input signal and a signal for controlling operation switching between a test and a normal operation.

  Inverting (hereinafter referred to as “NOT”) circuits 203 and 209 are circuits that invert an input signal and output the signal. The NOT circuit 203 outputs a signal for controlling an address input signal during a test and a normal operation. The NOT circuit 209 inverts the clock signal.

  The MUX 210 switches and outputs an inverted clock signal and a normal clock signal based on a signal for controlling a clock signal during a test and a normal operation.

  Next, the memory cell 201 and the transparent mode memory cell peripheral circuit are controlled by the ATPGEN signal, the SCANEN signal, and the SYSTEM_CLK signal.

  The ATPGEN signal is a signal that controls the operation switching between the test and normal operation in the memory cell peripheral circuit. When the ATPGEN signal is 1 (H), the test state is entered. When the ATPGEN signal is 0 (L), Control to transition to the normal operation state. The ATPGEN signal is applied to the control signal input terminals of the MUXs 208 and 210 and to the input terminal of the NOT circuit 203.

  The SCANEN signal is a signal for controlling the operation of the memory cell 201. When the SCANEN signal is 1 (H), a shift operation for reading data temporarily held in the memory cell 201 from the data output terminals (Do0 to Don). When the SCANEN signal is 0 (L), control is performed so as to transit to a capture operation state in which data input from the data input terminals (Di0 to Din) is temporarily held in the memory cell 201. The SCANEN signal is applied to the input terminal of the MUX 208, and when the ATPGEN signal is 1 (H), it is applied to the WEN terminal and CEN terminal of the memory cell 201.

  The SYSTEM_CLK signal is a system clock signal. The SYSTEM_CLK signal is applied to the input terminal of the MUX 210 and the input terminal of the NOT circuit 209. When the ATPGEN signal is 1 (H), the clock signal inverted by the NOT circuit 209 is when the ATPGEN signal is 0 (L). A normal clock signal is applied to the CLK terminal of the memory cell 201.

  Hereinafter, the flow of the test operation by the method using the transparent mode will be described.

  First, in the method using the transparent mode, a 1 (H) ATPGEN signal is issued, and the MUXs 208 and 210 are controlled to select the test signal applied to the input terminal. Next, in order to perform the test by operating the memory cell 201 in the transparent mode, a SCANEN signal and a SYSTEM_CLK signal are issued with 1 (H) and 0 (L) as one cycle. As a result, the SCANEN signal selected by the MUX 208 based on the 1 (H) ATPGEN signal is applied to the WEN terminal and the CEN terminal of the memory cell 201, and the NOT circuit is connected to the CLK terminal of the memory cell 201 by the MUX 210. The SYSTEM_CLK signal inverted at 209 is applied, and the memory cell 201 operates in the transparent mode.

  In the test of the memory cell peripheral circuit related to input / output data using the transparent mode, the test signal applied to the scan cell 211 as input data is transmitted to the memory cell 201 via the data input terminals (Di0 to Din) of the memory cell 201. Are output temporarily from the data output terminals (Do0 to Don). Thereafter, the signal output from the data output terminals (Do0 to Don) of the memory cell 201 is applied to the scan cell 212 via the combinational circuit at the subsequent stage, and the signal observed by the scan cell 212 is expected to be a normal pattern. It is determined whether or not the values match.

  In the test using the transparent mode, the memory cell peripheral circuit test related to the address input is performed by operating the memory cell 201 in the transparent mode, so that the ATPGEN signal is inverted by the NOT circuit 203, and the 0 (L) ATPGEN The signal is input to the AND circuit 204 provided in the previous stage of each address input terminal (A0 to An), and the test signal applied to the scan cell 202 as the address input data is a 0 (L) signal by the AND circuit 204. Is output.

  As described above, in the method using the transparent mode, the address input data input to the address input terminals (A0 to An) of the memory cell 201 is fixed in the peripheral circuit in the previous stage of the memory cell 201 related to the address input / output data. Since the signal is (L), it is possible to determine whether the signal is fixed to 0 (L) due to stuck-at fault in the path between the scan cell 202 and the address input terminals (A0 to An) of the memory cell 201. However, there is a problem of reducing the failure detection rate. In consideration of power consumption and stability during testing, the clock input to the CLK terminal of the memory cell 201 and the signal input to the CEN terminal are controlled and specified so that not all memory cells mounted on the LSI are operated simultaneously. When only the memory cell 201 is operated and the test is performed, the stopped memory cell (for example, a memory cell other than the memory cell 201 mounted on the LSI) becomes shadow logic, so that data output of a plurality of memory cells is performed. Test with a circuit that captures a single comparator, which reduces the failure detection rate of the memory BIST.

  The present invention solves the problems in the method using the bypass path circuit 108 and the method using the transparent mode described with reference to FIGS. 1 and 2, and improves the fault detection rate of the peripheral circuit of the memory cell. The present invention proposes a circuit configuration that can be tested with power consumption.

  FIG. 3 is a diagram showing a test flow using the LSI tester 40 according to the embodiment of the present invention.

  In LSI testing, test data generated by test pattern generation (hereinafter referred to as “TPG”) is applied to the CUT, and output analysis (hereinafter referred to as “ORA”) results in normal output from the CUT. It is determined whether or not the pattern matches the expected value, and a shipping test is performed, which is performed using a tester outside the chip such as an LSI tester.

  Hereinafter, the flow of the LSI test of the embodiment will be described with reference to FIG.

  First, before performing an LSI test, a test pattern 31 is generated by an ATPG tool 30 corresponding to a TPG, based on the logical design of the CUT, at a terminal (for example, PC: Personal Computer) that performs test pattern generation, and a fault simulator Thus, the expected value pattern 32 is verified.

  After this pre-processing, in the LSI test, the generated test pattern 31 is read, and based on the read test pattern 31, waveform formation 401 of a signal serving as test data is performed, and an inspection terminal (external terminal) provided in the prober 403 is provided. Pin) is driven by a terminal drive 402, and a test signal is applied to a scan cell (including a scan register) provided in the preceding stage of the CUT of the LSI 43 installed on the inspection table 42 (the scan cell is controlled from an external pin). .

  Next, in the LSI test, the output for the test signal is detected by the output detection 404 from the scan cell provided in the latter stage of the CUT of the LSI 43, and the detected output value and the expected value of the expected value pattern 32 are compared by the pattern comparison 405. Based on the comparison result, analysis is performed by output result analysis, and the analysis result is output.

  As described above, in the test using the LSI tester, the test signal is applied from the external terminal provided in the LSI tester 40 to the scan cell provided in the preceding stage of the CUT based on the test pattern and the expected value pattern prepared in advance. Then, the output result is detected from the scan cell provided in the subsequent stage of the CUT, and the LSI 43 is subjected to a shipping test by comparing the output value with the expected value by the pattern comparison 405.

  FIG. 4 is a diagram showing a configuration example and a flow of operation of the mode setting means 60 according to the embodiment of the present invention.

  In order to improve the fault detection rate of the peripheral circuit of the memory cell and realize a circuit configuration capable of performing the test with low power consumption, the present invention provides a method using the bypass path circuit 108 shown in FIG. A method of setting a memory cell using a bypass path circuit and a memory cell using a transparent mode at a time when performing a test for a plurality of memory cells mounted on the LSI 43 by combining the methods using the transparent mode shown in FIG. As shown in FIG.

  First, a configuration example of the mode setting unit 60 will be described.

  The configuration of the mode setting means 60 shown in FIG. 4 includes an instruction register 51, an instruction decoder 52, and a mode setting signal register 53.

  The instruction register 51 is a register for setting an instruction code for operating in the transparent mode. An instruction code is received from a TDi terminal of a TAP (Test Access Port) compliant with IEEE 1149.1 (Institute of Electrical and Electronic Engineers 1149.1). Is set.

  The instruction code set in the instruction register 51 is prepared in advance for each memory cell using the IEEE1149.1 user instruction code. For example, in order to operate the memory cells A and Z in the bypass path mode and the memory cells B and Y in the transparent mode among the memory cells mounted on the LSI 43, a user command corresponding to the memory cells A, B, X, and Y A code (for example, a 5-bit code such as “10001”, “10010”, “10011”, “10100”) is prepared.

  The instruction decoder 52 is a decoder that decodes (decodes) an instruction code set in the instruction register 51.

  The mode setting signal register 53 is a register for holding an instruction (mode setting) for a plurality of memory cells decoded (decoded) by the instruction decoder 52. The mode setting signal register 53 can initialize the setting in the register by TRST of TAP.

  Next, the operation flow of the mode setting means 60 will be described.

  As shown in FIG. 4, the mode setting means 60 is a pre-process executed before the test, and operates in a bypass path mode with a specific memory cell prepared in advance in the LSI 43 mounted on the LSI 43. Is set in the instruction register 51 from the TDi terminal of the TAP, decoded by the instruction decoder 52, and the decoded instruction (mode setting) is set in the mode setting signal register 53. . Further, when decoding a plurality of instruction codes, the mode setting means 60 shifts the instruction code decoded by the instruction decoder 52 to the TDo terminal of the TAP and decodes it to the instruction register 51 ( By sequentially setting the instruction codes that have not been decoded, the plurality of instruction codes are decoded (decoded), and the plurality of decoded instructions (mode setting) are set in the mode setting signal register 53.

  As described above, the mode setting means 60 can designate in advance a memory cell using the bypass path mode for a plurality of memory cells mounted on the LSI 43 before performing the test. .

  Thus, in the LSI test, the mode setting signal (MEM_BYPASS signal) shown in FIG. 4 is issued to each memory cell based on the command (mode setting) set in the mode setting signal register 53 by the mode setting means 60, and the bypass path The operation control of the memory cell in the mode and the memory cell in the transparent mode is realized.

  FIG. 5 is a diagram showing a configuration example of the memory cell 301 inside the LSI 43 and main memory cell peripheral circuits according to the embodiment of the present invention.

  A memory cell 301 in FIG. 5 is the same as the memory cells 101 and 201 shown in the configuration examples of FIGS. Therefore, description of the memory cell 301 in FIG. 5 is omitted.

  The memory cell peripheral circuit in the LSI 43 includes a bypass path circuit 317, scan cells (including scan registers) 302, 307, 310, 316, 319, MUX 308, 311, 312, 314, 315, 318, combinational circuit 306, NOT Circuits 303 and 313, AND circuits 305 and 309, and a logical sum (OR) circuit 304 are provided.

  The bypass path circuit 317 is a circuit between the data input terminals (Di0 to Din) and the data output terminals (Do0 to Don) of the memory cell 301, and is configured to bypass the memory cell 301. The bypass path circuit 317 outputs the data human power signal to a circuit subsequent to the memory cell 301.

  The scan cells 302, 307, 310, 316, and 319 are D-FFs each having an input terminal (D), an output terminal (Q), and a CLK terminal, and temporarily hold an applied signal. The held signal can be output with the signal of H). The scan cells 302, 307, 310, 316, and 319 are used as test signal application (control) and post-test signal output (observation) destinations when testing memory cell peripheral circuits related to address input and data input / output. used. In the address input test, a test signal is applied to the scan cell 302, and a signal after the test is output to the scan cell 307. In the data input / output test, a test signal is applied to the scan cell 316, and a signal after the test is output to the scan cell 319. A control signal for inputting the scan cell 310 to the WEN terminal and the CEN terminal is applied.

  The MUXs 308, 311, 312, 314, 315, and 318 have a plurality of input terminals, control signal input terminals, and output terminals, and control switching of two or more input signals during testing and normal operation. This is a circuit that selects and outputs as a single signal based on the signal to be transmitted. The MUXs 308, 311, 312, 314, 315, and 318 switch and output output signals according to the test and normal operation. In addition, the MUXs 308, 311, and 314 switch and output output signals in the bypass path mode and the transparent mode.

  The combinational circuit 306 is a combinational circuit in which a plurality of XOR circuits are configured in a tree shape. The combinational circuit 103 collects address input signals.

  NOT circuits 303 and 313 are circuits that invert the input signals and output them. The NOT circuit 303 inverts the signal for controlling the address input signal during the test and normal operation, and the NOT circuit 313 inverts the system clock signal. Let

  The AND circuits 305 and 309 are circuits that perform an AND operation on an input signal and output an operation result. The AND circuit 305 is provided in the preceding stage of each address input terminal (A0 to An), and performs an AND operation between the address input signal and a control signal for controlling the address input signal at the time of test and normal operation. I do. The AND circuit 309 is provided in the subsequent stage of the MUX 308, and performs an AND operation between the signal output from the MUX 308 and a signal for controlling the operation switching between the test time and the normal operation.

  A logical sum (hereinafter referred to as “OR”) circuit 304 is a circuit that performs a logical sum operation on an input signal and outputs an operation result. The OR operation of the signal for controlling the operation switching between the test and normal operation in the memory cell peripheral circuit and the mode setting signal set by the mode setting means 60 and issued when the test is performed is performed.

  Next, the memory cell 301 and the main memory cell peripheral circuit inside the LSI 43 according to the embodiment of the present invention are controlled by the ATPGEN signal, the SCANEN signal, the SYSTEM_CLK signal, and the MEM_BYPASS signal.

  The ATPGEN signal is a signal that controls the operation switching between the test and normal operation in the memory cell peripheral circuit. When the ATPGEN signal is 1 (H), the test state is entered. When the ATPGEN signal is 0 (L), Control to transition to the normal operation state. The ATPGEN signal is applied to the control signal input terminals of the MUXs 308, 312, 315, and 318, to the input terminal of the AND circuit 309, and to the input terminal of the NOT circuit 309.

  The SCANEN signal is a signal for controlling the operation of the memory cell 301. When the SCANEN signal is 1 (H), the data temporarily stored in the memory cell 301 is read from the data output terminals (Do0 to Don). When the SCANEN signal is 0 (L), control is performed so that the data input from the data input terminals (Di0 to Din) is transited to the capture operation state in which the memory cell 301 is temporarily held. The SCANEN signal is applied to the input terminal of the MUX 311.

  The SYSTEM_CLK signal is a system clock signal. The SYSTEM_CLK signal is applied to the input terminal of the MUX 315 and to the input terminal of the NOT circuit 313.

  The MEM_BYPASS signal is issued to each memory cell as a mode setting signal based on the command (mode setting) set in the mode setting signal register 53 by the mode setting means 60, and the memory cell 301 in the bypass path mode and the memory in the transparent mode This signal controls the operation of the cell 301. When the MEM_BYPASS signal is 1 (H), it is operated as a bypass path mode, and when the MEM_BYPASS signal is 0 (L), it is controlled so as to operate as a transparent mode. The MEM_BYPASS signal is applied to the control signal input terminals of the MUXs 308, 311 and 314, and is applied to the input terminal of the OR circuit 304.

  Next, the memory cell peripheral circuit in the LSI 43 includes an address setting unit 61, a selection signal generation unit 62, an operation control signal supply unit 63, a clock inversion unit 64, and a selection unit 65.

  In the transparent mode, the address setting means 61 controls a control signal to the input terminal of the AND circuit 305 provided in the preceding stage of the memory cell 301 so as to set 0 (L) address input data to the address input of the memory cell 301. Apply. The address setting means 61 includes a NOT circuit 303 and an OR circuit 304, and is provided in the previous stage of the AND circuit 305. In the address setting means 61, the ATPGEN signal is applied to the input terminal of the NOT circuit 303, the inverted ATPGEN signal and the MEM_BYPASS signal are applied to the input terminal of the OR circuit 304, and the calculation result is the output terminal of the OR circuit 304. Is output from.

  FIG. 6 shows an example of a time chart of the address setting means 61 according to the embodiment of the present invention.

  FIG. 6A is a time chart in the bypass path mode, in which the ATPGEN signal is indicated by A, the MEM_BYPASS signal is indicated by B, and the output signal is indicated by C. FIG. 6B is a time chart in the transparent mode, in which the ATPGEN signal is indicated by A, the MEM_BYPASS signal is indicated by B, and the output signal is indicated by C.

  In the bypass path mode of FIG. 6A (when the MEM_BYPASS signal is 1 (H)), the address setting means 61, as shown in A and B of FIG. 6A, 1 (H) ATPGEN signal, The MEM_BYPASS signal is applied. As a result, the address setting means 61 is inverted to 0 (L) ATPGEN signal by the NOT circuit 303, and the inverted 0 (L) ATPGEN signal and 1 (H) MEM_BYPASS signal are input to the OR circuit 304. When applied to the terminal, a 1 (H) signal shown in C of FIG. 6 (a) is output. 6A, since the control signal applied to the input terminal of the AND circuit 305 provided in the subsequent stage of the address setting means 61 is 1 (H), it is applied to the scan cell 302. The test signal thus applied is applied as address input data to the address input terminals (A0 to An) of the memory cell 301 via the combinational circuit.

  Further, in the transparent mode of FIG. 6 (b) (when the MEM_BYPASS signal is 0 (L)), the address setting means 61, as shown in A and B of FIG. 6 (b), 1 (H) ATPGEN signal , 0 (L) MEM_BYPASS signal is applied. As a result, the address setting means 61 is inverted to a 0 (L) ATPGEN signal by the NOT circuit 303, and the inverted 0 (L) ATPGEN signal and the 0 (L) MEM_BYPASS signal are input to the OR circuit 304. Applied to the terminal, a 0 (L) signal shown in C of FIG. 6B is output. Therefore, in the transparent mode of FIG. 6B, since the control signal applied to the input terminal of the AND circuit 305 provided in the subsequent stage of the address setting means 61 is 0 (L), the address input of the memory cell 301 is performed. A 0 (L) signal is applied to the terminals (A0 to An) as address input data.

  As described above, the address setting means 61 sets the test signal applied to the scan cell 302 as address input data in the memory cell 301 in the bypass path mode, and 0 ( L) Address input data is set.

  Thereby, the address setting means 61 realizes control of the address input data of the memory cell 301 in the bypass path mode and the transparent mode.

  The selection signal generation means 62 selects output data from the bypass path circuit 317 by the MUX 318 in the bypass path mode, and output data output from the data output terminals (Do0 to Don) of the memory cell 301 in the transparent mode. Is generated by the MUX 318. The selection signal generating means 62 is composed of a MUX 318 and an AND circuit 309 and is provided in the subsequent stage of the scan cell 307. In the selection signal generating means 62, the signal output from the scan cell 307 is applied to the input terminal of the MUX 318, and the 1 (H) signal is applied to the other input terminal. In addition, the selection signal generating means 62 applies the MEM_BYPASS signal to the control signal input terminal of the MUX 318, and selects the signal applied to the input terminal based on the MEM_BYPASS signal. Next, the selection signal generator 62 applies the signal selected and output by the MUX 318 and the ATPGEN signal to the input terminal of the AND circuit 309, and the calculation result is output from the output terminal of the AND circuit 309.

  FIG. 7 shows an example of a time chart of the selection signal generating means 62 according to the embodiment of the present invention.

  FIG. 7A is a time chart in the bypass path mode, in which the test signal applied to the scan cell 307 is indicated by A, the ATPGEN signal is indicated by B, the MEM_BYPASS signal is indicated by C, and the output signal is indicated by D. FIG. 7B is a time chart in the transparent mode, in which the test signal applied to the scan cell 307 is A, the ATPGEN signal is B, the MEM_BYPASS signal is C, and the output signal is D.

  In the bypass path mode shown in FIG. 7 (a) (when the MEM_BYPASS signal is 1 (H)), the selection signal generator 62 generates an ATPGEN signal of 1 (H) as shown in B and C of FIG. 7 (a). , MEM_BYPASS signal is applied. Further, the selection signal generating means 62 applies the address input signals aggregated and output by the combinational circuit 306 provided in the preceding stage of the scan cell 307 to the scan cell 307, and generates a signal as shown in A of FIG. Become. As a result, the selection signal generator 62 selects the 1 (H) signal by the MUX 308 based on the 1 (H) MEM_BYPASS signal, and the 1 (H) ATPGEN signal and the 1 (H) selected by the MUX 308. ) Is applied to the input terminal of the AND circuit 309, and a 1 (H) signal shown at D in FIG. 7A is generated. Therefore, in the bypass path mode of FIG. 7A, a 1 (H) signal is applied to the control signal input terminal of the MUX 318 provided in the subsequent stage of the selection signal generating means 62, and the output data from the bypass path circuit 317 is Selected by MUX 318.

  In the transparent mode of FIG. 7B (when the MEM_BYPASS signal is 0 (L)), the selection signal generating means 62, as shown in B and C of FIG. A 0 (L) MEM_BYPASS signal is applied. Further, since the selection signal generating means 62 has 0 (L) address input data by the address setting means 61, the signal output from the scan cell 307 is 0 as shown in A of FIG. (L) signal. As a result, the selection signal generating means 62 selects the input signal 0 (L) from the scan cell 307 by the MUX 308 based on the 0 (L) MEM_BYPASS signal, and selects the 1 (H) ATPGEN signal and the MUX 308. The 0 (L) signal thus applied is applied to the input terminal of the AND circuit 309, and a 0 (L) signal is generated as indicated by D in FIG. 7 (b). Therefore, in the transparent mode of FIG. 7B, a 0 (L) signal is applied to the control signal input terminal of the MUX 318 provided in the subsequent stage of the selection signal generating means 62, and the data output terminals (Do0 to The output data output from Don) is selected by the MUX 318.

  As described above, the selection signal generator 62 selects the output data from the bypass path circuit 317 in the bypass path mode, and is output from the data output terminals (Do0 to Don) of the memory cell 301 in the transparent mode. A signal is generated to control to select output data.

  As a result, the selection signal generating unit 62 controls the input / output data of the memory cell 301 in the bypass path mode and the transparent mode.

  The operation control signal supply means 63 applies a 1 (H) signal in the bypass path mode and a SCANEN signal for controlling the operation of the memory cell 301 to the WEN terminal and CEN terminal of the memory cell 301 in the transparent mode. Supply a signal to control. The selection signal generating means 62 is composed of a MUX 311 and is provided in the preceding stage of the MUX 312. The selection signal generation means 62 applies a 1 (H) signal to the input terminal of the MUX 311, applies a SCANEN signal to the other input terminal, and outputs a selected signal from the output terminal of the MUX 311.

  FIG. 8 shows an example of a time chart of the operation control signal supply means 63 according to the embodiment of the present invention.

  Fig. 8 (a) is a time chart in the detour path mode. The SCANEN signal is applied to A, the MEM_BYPASS signal is applied to B, the output signal is applied to C, the signal applied to the WEN terminal is applied to D, and the CEN terminal is applied. The signal is shown in E. FIG. 8B is a time chart in the transparent mode. The SCANEN signal is set to A, the MEM_BYPASS signal is set to B, the output signal is set to C, the signal applied to the WEN terminal is set to D, and the CEN terminal is set. The applied signal is shown in E.

  In the bypass path mode of FIG. 8A (when the MEM_BYPASS signal is 1 (H)), the operation control signal supply means 63 is 0 (L) and 1 as shown in A and B of FIG. A SCANEN signal with (H) as one cycle and a MEM_BYPASS signal with 1 (H) are applied. As a result, the operation control signal supply means 63 selects the 1 (H) signal by the MUX 311 based on the MEM_BYPASS signal of 1 (H), and the output terminal of the MUX 311 indicates to C in FIG. 1 (H) signal is output. Therefore, in the bypass path mode of FIG. 8A, a 1 (H) signal is applied to the control signal input terminal of the MUX 312 provided in the subsequent stage of the operation control signal means 63, and is applied to the control signal input terminal of the MUX 312. Based on the 1 (H) ATPGEN signal, the 1 (H) signal indicated by D and E in FIG. 8A is applied to the WEN terminal and CEN terminal of the memory cell 301.

  In the transparent mode shown in FIG. 8B (when the MEM_BYPASS signal is 0 (L)), the operation control signal supply means 63 outputs 0 (L) and 1 (as shown in A and B of FIG. 8B). H) and SCANEN signal for 1 cycle, and 0 (L) MEM_BYPASS signal are applied. As a result, the operation control signal supply means 63 selects the SCANEN signal with 0 (L) and 1 (H) as one cycle by the MUX 311 based on the 0 (L) MEM_BYPASS signal, and from the output terminal of the MUX 311, A SCANEN signal indicated by C in FIG. 8B is output. Therefore, in the transparent mode of FIG. 8B, the SCANEN signal is applied to the control signal input terminal of the MUX 312 provided in the subsequent stage of the operation control signal means 63, and 1 (H) applied to the control signal input terminal of the MUX 312. Based on the ATPGEN signal, the SCANEN signal indicated by D and E in FIG. 8B is applied to the WEN terminal and CEN terminal of the memory cell 301.

  As described above, the operation control signal supply means 63 stores the SCANEN signal in which the 1 (H) signal in the bypass path mode and the 0 (L) and 1 (H) in one cycle in the transparent mode as the memory. A signal for controlling to be applied to the WEN terminal and the CEN terminal of the cell 301 is supplied.

  Accordingly, the operation control signal supply unit 63 stops the memory cell 301 in the bypass path mode, and sequentially applies the data signal applied to the data input terminals (Di0 to Din) of the memory cell 301 in the transparent mode. , And control to output from the data output terminals (Do0 to Don).

  The clock inverting means 64 applies a 0 (L) signal to the CLK terminal of the memory cell 301 in the bypass mode, and an inverted SYSTEM_CLK signal to control the operation of the memory cell 301 in the transparent mode. . The clock inversion means 64 is configured by the MUX 314 and is provided in the previous stage of the MUX 315. In the clock inversion means 64, a 0 (L) signal is applied to the input terminal of the MUX 314, the SYSTEM_CLK signal inverted by the NOT circuit 313 is applied to the other input terminal, and the clock selected from the output terminal of the MUX 314 is selected. A signal is output.

  FIG. 9 shows an example of a time chart of the clock inverting means 64 according to the embodiment of the present invention.

  FIG. 9A is a time chart in the bypass path mode, where the SYSTEM_CLK signal is A, the MEM_BYPASS signal is B, the output signal is C, and the signal applied to the CLK terminal is D. FIG. 9B is a time chart in the transparent mode, where the SYSTEM_CLK signal is A, the MEM_BYPASS signal is B, the output signal is C, and the signal applied to the CLK terminal is D.

  In the bypass path mode shown in FIG. 9A (when the MEM_BYPASS signal is 1 (H)), the clock inverting means 64 outputs 0 (L) and 1 (H) as shown in A and B of FIG. ) Is a SYSTEM_CLK signal and 1 (H) MEM_BYPASS signal is applied. As a result, the clock inversion means 64 selects the 0 (L) signal by the MUX 314 based on the 1 (H) MEM_BYPASS signal, and the 0 (L) shown in C of FIG. L) signal is output. Therefore, in the bypass path mode of FIG. 9A, a 0 (L) signal is applied to the control signal input terminal of the MUX 315 provided in the subsequent stage of the clock inverting means 64, and is applied to the control signal input terminal of the MUX 315. Based on the 1 (H) ATPGEN signal, a 0 (L) signal indicated by D in FIG. 9A is applied to the CLK terminal of the memory cell 301.

  In the transparent mode of FIG. 9B (when the MEM_BYPASS signal is 0 (L)), the clock inverting means 64 is 0 (L) and 1 (H) as shown in A and B of FIG. 9B. Then, the SYSTEM_CLK signal for 1 cycle and the 0 (L) MEM_BYPASS signal are applied. As a result, based on the MEM_BYPASS signal of 0 (L), the clock inversion means 64 is inverted by the NOT circuit 313 of the previous stage by the MUX 314 and the SYSTEM_CLK signal having 1 (H) and 0 (L) as one cycle is selected. An inverted SYSTEM_CLK signal indicated by C in FIG. 9B is output from the output terminal of the MUX 314. Therefore, in the transparent mode of FIG. 9B, the inverted SYSTEM_CLK signal is applied to the control signal input terminal of the MUX 315 provided in the subsequent stage of the clock inverting means 64, and the 1 applied to the control signal input terminal of the MUX 315. Based on the ATPGEN signal in (H), the inverted SYSTEM_CLK signal shown in D of FIG. 9B is applied to the CLK terminal of the memory cell 301.

  In this way, the clock inverting means 64 outputs a signal of 0 (L) in the bypass path mode, and an inverted SYSTEM_CLK signal having 1 (H) and 0 (L) as one cycle in the transparent mode. Applied to the CLK terminal of the memory cell 301.

  Thereby, the clock inversion means 64 stops the memory cell 301 in the bypass path mode, and sequentially applies the data signal applied to the data input terminals (Di0 to Din) of the memory cell 301 in the transparent mode. Control is performed to output from the output terminals (Do0 to Don).

  The selection means 65 selects the data signal from the bypass path circuit 317 in the bypass path mode, and the data signal output from the data output terminals (Do0 to Don) of the memory cell 301 in the transparent mode. The selection means 65 is composed of a MUX 318 and is provided in the subsequent stage of the memory cell 301. In the selection means 65, the data signal from the bypass path circuit 317 is applied to the input terminal of the MUX 318, and the data signal output from the data output terminals (Do0 to Don) of the memory cell 301 is applied to the other input terminal. The selected data signal is output from the output terminal of the MUX 318.

  In the bypass path mode (when the MEM_BYPASS signal is 1 (H)), the selection unit 65 applies the 1 (H) selection control signal generated by the selection signal generation unit 62 to the control signal input terminal of the MUX 318. The As a result, the selection unit 65 selects the data signal from the bypass path circuit 317 by the MUX 318 based on the 1 (H) selection control signal, and outputs the selected data signal from the output terminal of the MUX 318.

  In the transparent mode (when the MEM_BYPASS signal is 0 (L)), the selection unit 65 applies the 0 (L) selection control signal generated by the selection signal generation unit 62 to the control signal input terminal of the MUX 318. . As a result, the selection means 65 selects the data signal output from the data output terminals (Do0 to Don) of the memory cell 301 by the MUX 318 based on the 0 (L) selection control signal, and from the output terminal of the MUX 318, The selected data signal is output.

  As described above, the selection unit 65 selects the data signal from the bypass path circuit 317 in the bypass path mode, and the data signal output from the data output terminals (Do0 to Don) of the memory cell 301 in the transparent mode. Select with MUX 318.

  Accordingly, the selection unit 65 can control the input / output data of the memory cell 301 in the bypass path mode and the transparent mode, and can test the memory cell peripheral circuit related to the input / output data.

  10 and 11 show examples of timing charts when a product test is performed in the memory cell 301 and the memory cell peripheral circuit according to the embodiment of the present invention.

  FIG. 10 is a diagram showing an example of a time chart during a memory cell peripheral circuit test relating to address input according to the embodiment of the present invention. Further, since the test of the memory cell peripheral circuit related to the address input cannot be performed in the transparent mode, 1 (in accordance with the instruction (mode setting) set in the mode setting signal register 53 by the mode setting means 60 so as to operate in the bypass path mode. H) MEM_BYPASS signal is issued, and the memory cell 301 operates as a bypass path mode to perform a test.

  FIG. 10 shows output signals of the combination circuit provided in the subsequent stage of the scan cell 302 to A, B, C and D, and output signals of the AND circuit 305 provided in the previous stage of the memory cell 301 to control the address input data, E, F, In G and H, the output signal of the combinational circuit 306 that aggregates the address input data is shown in I.

  First, a data signal is applied to the scan cell 302 in the test of the memory cell peripheral circuit related to address input. The applied data signal is applied to a combinational circuit provided in the subsequent stage of the scan cell 302. In the test of the memory cell peripheral circuit related to the address input, the address setting means 61 outputs a 1 (H) signal based on the 1 (H) ATPGEN signal and the 1 (H) MEM_BYPASS signal. Therefore, when the test signal applied to the scan cell 302 is applied to the combinational circuit and signals such as A, B, C, and D shown in FIG. 10 are output from the combinational circuit, an AND provided in the subsequent stage of the combinational circuit. The 1 (H) signal applied to the input terminal of the circuit 305 and output from the address setting means 61 is applied to the other input terminal of the AND circuit 305, and E, F, G, and H shown in FIG. The following signal is output.

  Next, the signals output from the AND circuit 305 are applied to the input terminals of the combinational circuit 306 and are collected as address input data. The aggregated signal becomes a signal as shown in I of FIG. 10, is output from the output terminal of the combinational circuit 306, and is applied to the scan cell 307.

  The memory cell peripheral circuit test related to address input is performed in a state where the memory cell 301 is stopped for low power consumption. Therefore, the 1 (H) SCANEN signal is applied to the WEN terminal and CEN terminal of the memory cell 301 by the operation control signal supply means 63 based on the 1 (H) ATPGEN signal and the 1 (H) MEM_BYPASS signal. Then, a 0 (L) SYSTEM_CLK signal is applied to the CLK terminal of the memory cell 301 by the clock inversion means 64 based on the 1 (H) ATPGEN signal and the 1 (H) MEM_BYPASS signal. Stop.

  As described above, in the test of the memory cell peripheral circuit related to the address input, the data signal which is the test pattern of the address input is applied to the scan cell 302, and the signal is output to the scan cell 307 via the memory peripheral circuit related to the address input. Then, by comparing the output value with an expected value that is a normal pattern, it is possible to determine whether or not the memory cell peripheral circuit related to the address input has failed.

  As a result, when testing using the transparent mode, it is possible to test the memory cell peripheral circuit related to the address input that could not be tested by controlling it to operate as a bypass path mode. The failure detection rate can be improved.

  FIG. 11 is a diagram showing an example of a time chart at the time of testing the memory cell peripheral circuit related to input / output data according to the embodiment of the present invention.

  FIG. 11A is a time chart in the detour path mode, in which output signals of the combinational circuit provided in the subsequent stage of the scan cell 316 are output to A, B, C, and D, and output signals of the MUX 318 provided in the subsequent stage of the memory cell 301. Are shown in E, F, G and H.

  First, a data signal is applied to the scan cell 316 in the test of the memory cell peripheral circuit related to input / output data. The applied data signal is applied to a combinational circuit provided in the subsequent stage of the scan cell 316. Therefore, when signals such as A, B, C, and D shown in FIG. 11A are output from the combinational circuit, they are applied to the input terminal of the MUX 318 provided in the subsequent stage of the memory cell 301 via the bypass path circuit 317. Is done. At this time, the 1 (H) MEM_BYPASS issued to the control signal input terminal of the MUX 318 according to the 1 (H) ATPGEN signal and the command (mode setting) set in the mode setting signal register 53 by the mode setting means 60. Based on the signal, 1 (H) selection control signal generated by the selection signal generating means 62 is applied. As a result, the MUX 318 selects the data signal applied from the detour path circuit 317 based on the applied 1 (H) selection control signal, and E, F, G, and E shown in FIG. Outputs a signal such as H.

  Next, the signal output from the MUX 318 is applied to the scan cell 319 via a subsequent combinational circuit.

  Further, the test of the memory cell peripheral circuit related to input / output data is performed in a state where the memory cell 301 is stopped in the bypass path mode in order to cope with low power consumption. Therefore, the 1 (H) SCANEN signal is applied to the WEN terminal and CEN terminal of the memory cell 301 by the operation control signal supply means 63 based on the 1 (H) ATPGEN signal and the 1 (H) MEM_BYPASS signal. Then, a 0 (L) SYSTEM_CLK signal is applied to the CLK terminal of the memory cell 301 by the clock inversion means 64 based on the 1 (H) ATPGEN signal and the 1 (H) MEM_BYPASS signal. Stop.

  As described above, in the test of the peripheral circuit of the memory cell related to the input / output data, the data signal which is the test pattern of the input data is applied to the scan cell 316, and the signal is output to the scan cell 319 via the bypass path circuit 317. By comparing the output value with an expected value that is a normal pattern, it is possible to determine whether or not the memory cell peripheral circuit related to the input / output data has failed.

  As a result, the memory cell peripheral circuit related to the input / output data in the stopped memory cell 301 that caused the failure detection rate reduction of the memory BIST when the test was performed using the transparent mode corresponding to the low power consumption. It is possible to test by controlling to operate as a detour path mode, and to improve the failure detection rate.

  FIG. 11B is a time chart in the transparent mode. A signal applied to the CLK terminal of the memory cell 301 is A, a signal applied to the WEN terminal is B, and a signal applied to the CEN terminal is shown. C, D, E, F, and G are output signals of the combinational circuit provided in the subsequent stage of the scan cell 316, and H, I, J, and K are signals output from the data output terminals (Do0 to Don) of the memory cell 301. Shown in

  First, a data signal is applied to the scan cell 316 in the test of the memory cell peripheral circuit related to input / output data. The applied data signal is applied to a combinational circuit provided in the subsequent stage of the scan cell 316. Therefore, when signals such as D, E, F, and G shown in FIG. 11B are output from the combinational circuit, they are applied to the data input terminals (Di0 to Din) of the memory cell 301.

  In the test of the memory cell peripheral circuit related to input / output data, since the memory cell 301 is operated in the transparent mode, the ATPGEN signal of 1 (H) and 0 (L) are supplied to the WEN terminal and CEN terminal of the memory cell 301. Based on the MEM_BYPASS signal, the operation control signal supply means 63 applies a SCANEN signal with 0 (L) and 1 (H) as one cycle, and the CLK terminal of the memory cell 301 has a 1 (H) ATPGEN signal. Based on the MEM_BYPASS signal of 1 (H), the inverted SYSTEM_CLK signal with 1 (H) and 0 (L) as one cycle is applied by the clock inversion means 64, and the memory cell 301 is set in the transparent mode and scanned. Shift and capture operations operate alternately.

  Therefore, the memory cell 301 sequentially outputs the applied data signal to the data output terminals (Do0 to Don) such as H, I, J, and K shown in FIG. 0 (L) issued to the control signal input terminal of the MUX 318 according to the ATPGEN signal of 1 (H) and the command (mode setting) set in the mode setting signal register 53 by the mode setting means 60. ), A selection control signal of 0 (L) generated by the selection signal generating means 62 is applied. As a result, the MUX 318 selects the data signal applied from the data output terminals (Do0 to Don) of the memory cell 301 according to the applied 0 (L) selection control signal, and the output signal from FIG. The same signals as H, I, J and K shown in FIG.

  Next, the signal output from the MUX 318 is applied to the scan cell 319 via a subsequent combinational circuit.

  As described above, in the test of the memory cell peripheral circuit related to the input / output data, the data signal which is the test pattern of the input data is applied to the scan cell 316, and the data input / output terminals (Di0 to Di0) of the memory cell 301 operating in the transparent mode. Din, Do0 to Don), a signal is output to scan cell 319, and the output value is compared with an expected value that is a normal pattern to determine whether a memory cell peripheral circuit related to input / output data has failed. Can be determined.

  Thus, when the test is performed in the bypass path mode, the output data from the memory cell 301 that could not be tested and the path between the data output terminal (Do0 to Don) of the memory cell 301 and the input terminal of the MUX 318 Then, it becomes possible to test the input terminal of the selection control signal in the MUX 318 by controlling the memory cell 301 to operate in the transparent mode, and the failure detection rate can be improved.

  As described above, according to the embodiment of the present invention, the method of using the bypass path circuit 317 and the method of operating the memory cell 301 in the transparent mode are combined, and the address setting unit 61, the selection signal generating unit 62, and the operation control are combined. A memory cell peripheral circuit having a signal supply unit 63, a clock inversion unit 64, and a selection unit 65 is configured, and each memory cell mounted on the LSI 43 according to an instruction (mode setting) set in the mode setting signal register 53 by the mode setting unit 60 In addition, by issuing the mode setting signal (MEM_BYPASS signal) and setting the bypass path mode and transparent mode, the operation of the memory cell in the bypass path mode and the memory cell in the transparent mode can be controlled, and low power consumption This is a problem of the method using the detour path circuit 317. The output data from the memory cell 301 that cannot be tested, the path between the data output terminal (Do0 to Don) of the memory cell 301 and the input terminal of the MUX 318, and the input terminal of the selection control signal in the MUX 318 Tests can be performed on memory cell peripheral circuits related to address inputs that cannot be tested, which is a problem in the method using the transparent mode. Test rate can be improved and power consumption can be reduced.

  Although the present invention has been described based on each embodiment, the present invention is not limited to the requirements shown here, such as combinations of other elements with the shapes listed in the above embodiments.

  With respect to these points, the present invention can be changed within a range that does not detract from the gist of the present invention, and can be appropriately determined according to the application form.

FIG. 4 is a diagram illustrating a configuration example of a memory cell peripheral circuit using a memory cell and a bypass path circuit in an LSI according to the present invention. FIG. 3 is a diagram showing a configuration example of a memory cell and a transparent mode memory cell peripheral circuit in an LSI according to the present invention. It is a figure which shows the flow of the test using the LSI tester based on the Example of this invention. It is a figure which shows the structural example and flow of operation | movement of the transparent mode setting means based on the Example of this invention. FIG. 3 is a diagram illustrating a configuration example of a memory cell inside an LSI and a main memory cell peripheral circuit according to an embodiment of the present invention. It is a figure which shows the example of the time chart of the address setting means based on the Example of this invention. It is a figure which shows the example of the time chart of the selection signal generation means which concerns on the Example of this invention. It is a figure which shows the example of the time chart of the operation control signal supply means which concerns on the Example of this invention. It is a figure which shows the example of the time chart of the clock inversion means based on the Example of this invention. It is a figure which shows the example of the time chart at the time of the memory cell peripheral circuit test regarding the address input which concerns on the Example of this invention. It is a figure which shows the example of the time chart at the time of the test of the memory cell peripheral circuit regarding the input / output data by the detour path mode which concerns on the Example of this invention. It is a figure which shows the example of the time chart at the time of the test of the memory cell peripheral circuit regarding the input / output data by the transparent mode which concerns on the Example of this invention.

Explanation of symbols

301 memory cell (synchronous SRAM)
302, 307, 310, 316, 319 Scan cell (D-FF)
308, 311, 312, 314, 315, 318 selection circuit (MUX: multiplexer)
305, 309 AND circuit (AND circuit)
304 OR circuit (OR circuit)
306 Combination circuit (Tree-like XOR circuit)
303, 313 Inversion circuit (NOT circuit)
317 Detour path circuit

Claims (6)

A scan cell for applying a test signal;
A scan cell that outputs a test signal;
A semiconductor integrated circuit corresponding to a scan test having a memory cell,
A circuit between an input terminal and an output terminal of the memory cell, and a bypass path circuit provided outside the memory cell;
Mode setting means for setting the memory cell to a transparent mode or a bypass path mode;
A semiconductor integrated circuit corresponding to a scan test, comprising: selection means for selecting an output of the bypass path circuit and an output of the memory cell set by the mode setting means. An instruction register that temporarily holds an instruction code indicating whether the bypass path mode or the transparent mode is set for each memory cell;
An instruction decoder for decoding an instruction code held in the instruction register;
A mode setting signal register that temporarily holds a mode setting signal corresponding to the memory cell, decoded by the instruction decoder;
2. The semiconductor integrated circuit corresponding to a scan test according to claim 1, wherein a signal of the mode setting signal register is read out during a test scan. A selection signal generating means for generating a selection signal for the selection means;
The selection signal generating means includes
3. The semiconductor integrated circuit corresponding to the scan test according to claim 1, wherein the test signal is supplied to the selection unit based on the mode setting signal read from the mode setting signal register. . Address setting means for setting an address for the memory cell;
The address setting means includes
4. The test signal as address input data of the memory cell based on the mode setting signal read from the mode setting signal register. A semiconductor integrated circuit that supports scan testing. An operation control signal supply means for supplying a control signal for controlling the operation of the memory cell to a chip enable terminal of the memory cell;
The operation control signal supply means includes
5. The control signal is supplied to a chip enable terminal of the memory cell based on the mode setting signal read from the mode setting signal register. 6. Integrated circuit that supports the scan test. A clock inversion means for inverting the clock;
The clock inverting means
6. The semiconductor integrated circuit corresponding to the scan test according to claim 1, wherein a clock is inverted based on the mode setting signal read from the mode setting signal register.

Images