JP2004512630A - Built-in self-test of multi-port CsRAM at-speed - Google Patents

Abstract

Built-in self-test (BIST) for multiport compact sRAM (CsRAM) uses a BIST controller that operates at system speed, while CsRAM is tested at memory speed. The inspection circuit allows multiple random access of the CsRAM per system clock cycle. In this way, timing-related defects in the CsRAM can be detected. The CsRAM is virtually divided into "k" partitions, which are tested simultaneously from different ports using the same and complementary test data. A conventional (BIST) controller can be used with the addition of minimal hardware into the collar located around the memory array.

Description

ここで、ｄは、００．．．０００または０１０１．．．０１０１等の任意のｎビットのベクトルである。
ＲｄおよびＲｄ￣は、ｒｅａｄ^{ｄ （ ｄ￣ ）}動作を表す。
ＷｄおよびＷｄ￣は、ｗｒｉｔｅ^{ｄ （ ｄ￣ ）}動作を表す。
（．．．）：（．．．）は、２つのポートにおける２つの並列動作を表す。
添え字ｕｐＳ_０（ｄｎＳ_０）は、区画Ｓ_０に対してのｍａｒｃｈ ｕｐ（ｍａｒｃｈ ｄｏｗｎ）検査を表す。
添え字ｕｐＳ_１（ｄｎＳ_１）は、区画Ｓ_１に対してのｍａｒｃｈ ｕｐ（ｍａｒｃｈ ｄｏｗｎ）検査を表す。
【００４９】
第２の検査セッションは、ステップ７から始まる。ステップ７において、仮想メモリ８６の増加する連続アドレスに（ｗ／２）個の検査データ・ワードが書き込まれ、メモリ８５の減少する連続アドレスに（ｗ／２）個の相補的な検査データ・ワードが書き込まれる。仮想メモリ８５および８６に書き込まれたデータは相補的な値を持ち、上述の第１のセッションで述べたのと同じ規則が適用される。ステップ７の間に実行される読み取り動作は、本検査方法に関連しない。
【００５０】
これは次のように表現できる。
【００５１】
【数２】

【００５２】
上述のように、各マーチング動作は、２ポートＣｓＲＡＭ１０全体のメモリ空間の半分である対応するメモリ区画の全アドレス空間を通して実行される。メモリの分割に応じて、各区画内のマーチングに関するアドレスの順序は連続的であることもそうでないこともある。例えば、行アドレスの最上位ビットを除きＡｄｄ_０がＡｄｄ_１とすべてのビット位置において同一であるような分割であれば、
ａｒ_０［ｒ−１］＝ａｒ_１［ｒ−１］，ａｒ_０［ｒ−２］＝ａｒ_１［ｒ−２］，…，
ａｒ_０［０］＝ａｒ_１［０］，
ａｃ_０［ｃ−１］＝ａｃ_１［ｃ−１］，…，ａｃ_０［０］＝ａｃ_１［０］
であり、各メモリ区画の範囲内のアドレスは連続している。
【００５３】
メモリの分割および検査アドレスの連続性に関係なく、上記アルゴリズムに従った故障検出率は同じである。同様に、検査はメモリ動作速度で実行され、システムはシステム・クロック速度で動作を続ける。
【００５４】
図５は、本発明に従ったパラレルＢＩＳＴを実行するため、従来のＢＩＳＴコントローラ３０を持つ修正カラー２５を２０で示す。太線の接続はバスを表し、バスのサイズは図５に表示されている。灰色で示した領域２５内の回路は、「ＢＩＳＴカラー（ｃｏｌｌａｒ）」として定義される。この例では、ＢＩＳＴコントローラ２０は２ポートＣｓＲＡＭ１０を検査するように適用されている。それにもかかわらず、２ポートＣｓＲＡＭについての動作原理および回路を理解すれば、他のタイプのマルチポートＣｓＲＡＭについてのカラー２５のその他の変型を容易に想定できるであろう。さらに上述のように、カラー２５を使用し、ＢＩＳＴコントローラ３０の動作のわずかな変更で、ＣｓＲＡＭ１０のａｔ−ｓｐｅｅｄでの検査が実現される。
【００５５】
カラー２５は、アドレス・マルチプレクサ２４、２４’、データ・マルチプレクサ２６、２６’およびＷ／Ｒマルチプレクサ２８、２８’を含む。各マルチプレクサは対応するポートｐ_０およびｐ_１においてそれぞれの機能を実行する。カラー２５は、ポートｐ_０のライン５１、５３、５５、６０、およびポートｐ_１のライン６１、６３、６５、７０を経由して、ＡＳＩＣの残り部分に接続している。マルチプレクサが「機能ブロックから」と記された接続を経由してＡＳＩＣの機能ブロックに接続しているときは、ＣｓＲＡＭ１０の両方の通常モードでの動作を可能にし、また、ＢＩＳＴコントローラ３０への接続を経由して接続しているとき、検査モードでのＣｓＲＡＭ１０の動作を可能にするように、複数のマルチプレクサが備えられている。
【００５６】
このように、ｐ_０のアドレス・マルチプレクサ２４は、メモリ１０の区画Ｓ_０においてアクセスされるべきセルの行および列を識別する（ｒ＋ｃ）ビット幅のアドレス信号を受け取る。ポートｐ_１のアドレス・マルチプレクサ２４’も、メモリの行と列の数は両方のポートについて同じであるので、（ｒ＋ｃ）ビット幅のアドレスを受け取る。ＢＩＳＴコントローラ３０は、（ｒ−１）＋ｃビット幅のメモリ１０についてのアドレスをライン３５上に生成し、各区画内の各セル・アドレスを完全に識別する。さらに、ＢＩＳＴコントローラ３０が信号ｍｅｍｓｅｌをライン３４上に提供し、第１の区画Ｓ_０と第２の区画Ｓ_１との間で選択するインバータ４３が用意される。この信号は、本例において、行アドレスの最上位ビットである。言い換えると、ｍｅｍｓｅｌはａｒ_０［ｒ−１］とａｒ_１［ｒ−１］を入れ替える。それぞれのポートについてのｍａｒｃｈ ｕｐまたはｍａｒｃｈ ｄｏｗｎアドレスは、カラー２５に配置されたインバータ４２を通して取得される。インバータ４２は、２つの仮想メモリの同時読み書き動作のためアドレスが反対であることを保証する。インバータ４４は、ＢＩＳＴコントローラ３０が同一の検査応答の組を比較することを可能にする。
【００５７】
データ・マルチプレクサ２６および２６’はｎビットを受け取る（「ｎ」は１ワードのサイズである）。従って、ＢＩＳＴコントローラ３０は、メモリ１０が２つの区画に分割されているのに応じて、ｎビット幅の検査データをライン３７上に生成しなければならない。これは、メモリ１０の２つの区画への仮想的な分割の結果である。ポートｐ_０に関して相補的なｎビット幅の検査データの第２セットをポートｐ_１に常に提供するため、インバータ４１が使用される。Ｒ／Ｗマルチプレクサ２８および２８’は、読取りまたは書込み動作を示す単一ビットの制御信号３８を受け取る。制御信号が「１」であれば、書込み動作が実行される。
【００５８】
図４を参照して述べたように、両方の仮想メモリは読取りまたは書込み動作を同時に実行するが、アドレスは反対方向にマーチングし、データは相補的な値を有する。従って、制御信号は両方のポートについて同じものである。出力ライン６０および７０上の検査応答はｎビット幅であり、この検査応答は、セルに書き込まれたデータがそのセルから読み取られたデータと同一であるか否かを確認するためにＢＩＳＴコントローラ３０によって使用される。ＢＩＳＴコントローラ３０およびＣＳＲＡＭ１０はどちらも、記号３６で示すシステム・クロックｓｙｓＣｌｋで同期される。
【００５９】
上述のように、修正ＢＩＳＴコントローラ２０は、通常モードと検査モードを持つ。ｂｉｓｔ＿ｅｎ＝１が到着すると、ライン３９上の信号ｂｉｓｔｏｎがバッファ／マルチプレクサ（２４、２６、２８）および（２４’、２６’、２８’）からのデータを選択し、ＢＩＳＴが開始される。コントローラ３０は、まずｍｅｍｓｅｌを「０」にセットし、従って、ａｒ_０［ｒ−１］＝０およびａｒ_１［ｒ−１］＝１となる。この場合、ＢＩＳＴコントローラ３０は、ポートｐ_０を介してメモリ空間の下半分Ｓ_０を検査し、ポートｐ_１を介してメモリ空間の上半分Ｓ_１を検査するが、マーチングは反対方向に進む。このセッションの間、ＢＩＳＴは図４のマーチングステップ１−６を実行して、従来のｓＲＡＭの半分についてＭＡＲＣＨ Ｃ―検査を完了する。
【００６０】
第１の検査セッションが完了すると、ＢＩＳＴコントローラ３０はｍｅｍｓｅｌ＝１をセットして、同じＭＡＲＣＨ Ｃ−検査を繰り返す。第２のセッションの間、ａｒ_０［ｒ−１］＝１およびａｒ_１［ｒ−１］＝０であり、ＢＩＳＴコントローラ３０は、ポートｐ_１を介してメモリ空間の下半分Ｓ_０を検査し、ポートｐ_０を介してメモリ空間の上半分Ｓ_１を検査する。第２の検査セッションは、図４とともに説明したステップ７−１２に対応する。この検査が完了すると、ＢＩＳＴコントローラ３０はこれに応じて信号ｂｉｓｔ＿ｄｏｎｅおよびｂｉｓｔ＿ｐａｓｓをセットする。
【００６１】
従来のＢＩＳＴコントローラと比較したソフトウェアの変更の観点からは、この実施形態は、従来のＢＩＳＴコントローラ３０に対して少なくともｎビット幅検査データを生成し、２ｎビット幅の検査応答を確認することを要求する。
【００６２】
ハードウェアの観点からは、ＢＩＳＴコントローラ２５に（２ｎ＋ｒ＋ｃ）個のインバータが追加される。すなわち、ｎ個のインバータ４１、ｎ個のインバータ４４、（ｒ−１＋ｃ）個のインバータ４２および１個のインバータ４３が追加される。従来のＢＩＳＴコントローラが、図５のコントローラ２０と同じ数のマルチプレクサを必要とすることに注意されたい。さらに、ＡＳＩＣにおけるシリコン領域および関連する全般のピーク電源消費量が減少する。なぜなら、本発明が同じ容量の従来のコンパクトｓＲＡＭの検査よりも大幅に少ない量のＣｓＲＡＭの検査を行うように設計されているからである。
【００６３】
検査時間の観点からは、本発明に従ったシリアル検査は、同じサイズの単一ポートｓＲＡＭの従来の検査の場合と同じ時間を必要とする。２ポートｓＲＡＭの従来の検査と比較すると、図５の実施形態に従った検査時間は半分にすぎない。
【００６４】
修正ＢＩＳＴコントローラ２０は、従来のＢＩＳＴ実施形態と比較するとより多くのインバータを必要とする一方、修正ＢＩＳＴコントローラはｎビット幅の使用するべき検査データを提供する。従って、従来方法と比較して２倍の検査データおよび検査応答を使用するので、本発明に従った検査方法ではより高い精度が得られる。さらに、タイミング関連の故障を検出するために、システム・クロックより少なくとも２倍速いメモリ動作速度で検査が実行される。
【００６５】
図６は、本発明の別の実施形態４０を示す。この実施形態では、２ポートＣｓＲＡＭを検査するためにシリアル化された（ｓｅｒｉａｌｉｚｅｄ）ＢＩＳＴコントローラが使用される。この実施形態は、多数のメモリの間で単一のＢＩＳＴコントローラを共有するＡＳＩＣに対して推奨される。多数のメモリがＡＳＩＣ上に広く分散していると、図５に示すような共有のパラレルＢＩＳＴコントローラ２０は、検査データ・バスを全体に配線するコストのため費用がかかる。
【００６６】
図６のシリアルメモリＢＩＳＴコントローラ４０は、すべての仮想メモリに単一ビットの検査入力を提供して、各仮想メモリから単一ビットの検査応答を受け取ることによってこのオーバーヘッドを最小限度にする。配線の節約に加えて、シリアル化は、コントローラがＣｓＲＡＭの両方のポートに対して単一ビットの検査データを生成し、ＣｓＲＡＭの各ポートから単一ビットの検査応答を受け取るので、ＢＩＳＴコントローラのハードウェア要件も低減する。
【００６７】
この例の場合も、検査対象のメモリは、ポートあたりｒ行、ｃ列、ｗ個のワード、１ワードあたりｎビットを持つ２ポートＣｓＲＡＭ１０である。シリアルＢＩＳＴ４０は、本発明と同じ譲受人に譲渡された米国特許第４，９６９，１８４号に記述されているシリアルＭＡＲＣＨ検査（ＳＭＡＲＣＨ）を用いて動作し、参照により本明細書に援用される。
【００６８】
すべての（ＲｄＷｄ￣）および（Ｒｄ￣Ｗｄ）動作を（Ｒ０Ｗ１）^ｎ（Ｒ１Ｗ１）および（Ｒ１Ｗ０）^ｎ（Ｒ０Ｗ０）とそれぞれ置き換えることによって、図４に示したものと同じ原理をシリアル形態の検査方法に適用することが可能である。
【００６９】
図６において、シリアルＢＩＳＴカラー２５’を表している影付き領域は、アドレス・マルチプレクサ（２４、２４’）、データ・マルチプレクサ（２６、２６’）、Ｒ／Ｗマルチプレクサ（２８、２８’）およびインバータ４１−４４を含む。単一ビット検査データｓｉｍｅｍがＢＩＳＴコントローラ３０’からポートｐ_０の最下位ビットＤ_０［０］へライン３７を介して適用され、単一ビット検査データ
【数３】

がポートｐ_１の最下位ビットＤ_１［０］へ適用される。Ｄ_０およびＤ_１の残りの（ｎ−１）ビットは、出力ラインＱ_０およびＱ_１からそれぞれ戻される。換言すれば、
【数４】

である。最上位出力ビットＱ_０［ｎ−１］および反転ビットＱ_１￣［ｎ−１］＝Ｑ_０［ｎ−１］が評価のためＢＩＳＴコントローラ３０へ送り返される。
【００７０】
図６の実施形態において、ＢＩＳＴコントローラ４０は、両方のメモリに単一ビット検査を与え各仮想メモリからの単一ビット検査応答を評価することによって、２つの仮想メモリを同時に検査するはずである。このような構成のため、シリアルＢＩＳＴコントローラ４０は、ＣｓＲＡＭ１０の各出力ポートに対して単一ビットのコンパレータ（図示せず）を備えている。
【００７１】
シリアルＣｓＲＡＭ　ＢＩＳＴコントローラ４０は次のように動作する。ｂｉｓｔ＿ｅｎが受け取られ、ライン３９上にｂｉｓｔｏｎが生成されると、ＢＩＳＴモードがイネーブルにされ、ｍｅｍｓｅｌ＝０をセットして、ポートｐ_０を介してＣｓＲＡＭ１０の下半分Ｓ_０を検査し、ポートｐ_１を介してＣｓＲＡＭ１０の上半分Ｓ_１を検査する。上述したように、単一ビットの検査データｓｉｍｅｍがコントローラ３０によって生成されてｐ_０において供給され、
【数５】

がｐ_１において供給される。Ｑ_０／Ｄ_０およびＱ_１／Ｄ_１が、シリアル検査のシフト動作を実行するためカラー２５’において（ｎ−１）回のフィードバックを行う。最上位出力ビットＱ_０［ｎ−１］およびＱ_１￣［ｎ−１］がＢＩＳＴコントローラ３０によって並列に評価される。入力インバータ４１および出力インバータ４４上での反転のために、両方のポートからの検査応答は常に同一（すなわちＱ_０［ｎ−１］＝Ｑ_１［ｎ−１］）である。この検査が完了すると、ＢＩＳＴコントローラ３０はｍｅｍｓｅｌ＝１をセットして、ポートｐ_１を介してメモリ空間の下半分Ｓ_０を検査する。第２の検査が完了すると、コントローラはこれに応じてｂｉｓｔ＿ｄｏｎｅ＝１およびｂｉｓｔ＿ｐａｓｓをセットする。
【００７２】
従来のＢＩＳＴコントローラと比較すると、ＣｓＲＡＭシリアルＢＩＳＴ４０は、同一値の２つの出力ビットを評価するために、カラー２５’に（ｒ＋ｃ＋２）個の余分のインバータを必要とし、さらにＢＩＳＴコントローラ３０に２、３個のゲートを必要とする。上述のように、最上位出力ビットが比較されるが（Ｑ_０［ｎ−１］＝ Ｑ_１￣［ｎ−１］）、これは従来のＳ−ＭＡＲＣＨ実施形態における１ビット出力とは相違する。
【００７３】
検査時間の観点からは、本発明に従うシリアル検査は、同じサイズの単一ポートｓＲＡＭの従来の検査の場合と同じ時間を必要とする。２ポートｓＲＡＭの従来の検査と比較すると、図６の実施形態に従った検査時間は半分にすぎない。
【００７４】
図７の実施形態は、ｎビット幅の検査データを生成してｎビット幅の検査応答を確認するように設計されたＢＩＳＴコントローラ３０と共に使用されるべき図５のカラー２５の修正を示す。
【００７５】
ライン６０上のｎビット幅検査応答の第１のセットが、図５とともに上述したように、ＢＩＳＴコントローラ３０において比較され、かつ、加算器６６に入力される。ライン７０上のｎビット幅検査応答の他のセットが加算器５６に送られる。加算器５６の出力に接続された検出器５７は、（１；０）検出器であって、検査応答の２つのセットの間に不一致を検出したときその出力を「１」にセットし、「１」のままとなる。
【００７６】
検出器５７の出力はインバータ５９を通ってＡＮＤゲート５８の入力を制御し、一方、信号ｂｉｓｔ＿ｐａｓｓはＡＮＤゲート５８の他の入力を制御する。ＡＮＤゲート５８の出力は、メモリ内に故障が検出されない場合「１」である信号ｂｉｓｔ＿ｐａｓｓ＿ｃｏｍｂｉｎｅｄを提供する。
【００７７】
図７のＢＩＳＴカラー構成は、シリアルＢＩＳＴ実施形態にも使用することができる。
【００７８】
図８は、ＢＩＳＴカラー２５の別の１つの実施形態を示す。このＢＩＳＴカラー２５は、ｏｕｔｐｕｔ−０およびｏｕｔｐｕｔ−１を有する符号器７２、および、図５のインバータ４１および４４をそれぞれ置き換えた２つのＸＯＲゲート６７、６８を含む。図８に示す構成を用いて、ＢＩＳＴコントローラ３０は、２ポート、Ｗワード、１ワードあたりｎビットのＣｓＲＡＭ１０について、次の機能を実行するように設計されている。すなわち、（ａ）（ｗ／２）個のワードを有し１ワードあたり２ｎビットの４つの仮想単一ポート・メモリを検査し、（ｂ）その時に１つの仮想メモリを検査する。従って、４ビット・メモリ選択信号、例えばメモリ１０の各区画８５、８６を４回検査するためのｍｅｍｓｅｌ［３：０］信号が生成される。
【００７９】
符号器７２は、ライン３４上のｍｅｍｓｅｌ［３：０］に接続され、同一または相補的ないずれかの検査データの選択を制御する。同様に、符号器７２は区画８５、８６のどちらを検査するべきか、およびポートｐ_０またはｐ_１のどちらを使用するべきかを制御する。例えば、データ・バスに接続されたｏｕｔｐｕｔ−１が「０」であれば、ｏｕｔｐｕｔ−０を介して選択されるＣｓＲＡＭ１０の２つの区画に対応する２つのセッションにおいて、同一のデータを用いて検査が実行される。符号器７２のｏｕｔｐｕｔ−１が「１」であれば、図５とともに上述したように、相補的な検査データを用いて検査が実行される。
【００８０】
符号器７２のｏｕｔｐｕｔ−０は、メモリ１０のどちらの区画をポートｐ_０、ｐ_１のどちらから検査するべきかを選択するために使用される。ｏｕｔｐｕｔ−０が「０」であると、ｐ_０が区画８５を検査し、ｐ_１が区画８６を検査する。そうでない場合、ｐ_０が区画８６を検査し、ｐ_１が区画８５を検査する。
【００８１】
このようにして、ＣｓＲＡＭ１０の各区画は４回検査されるが、完全な故障検出のために、２回はｏｕｔｐｕｔ−１＝０のときに同一の検査データを用いて、別の２回はｏｕｔｐｕｔ−１＝１のときに相補的な検査データを用いて行われる。表１は符号器７２の機能を示す。
【００８２】
【表１】

【００８３】
図８のＢＩＳＴカラー構成は、シリアルＢＩＳＴ実施形態とともに同様に使用可能である。
【００８４】
本発明によると、システム・クロック生成器１２よりも少なくともｋ倍速い動作速度を持つコンパクトｓＲＡＭ１０に対してのａｔ−ｓｐｅｅｄでの検査品質を達成する新たなＢＩＳＴ手法が提供される。上述のように、ＣｓＲＡＭの検査は、すべての必要な修正をメモリ・カラー２５、２５’に包含させた従来のＢＩＳＴコントローラ３０、３０’を用いて実施することができる。必要とされる唯一のコストは、パラレルまたはシリアル検査を実施するため、検査対象のＣｓＲＡＭ周囲のカラー２５、２５’に関連するもののみである。
【００８５】
ｒ行およびｃ列で、ポートあたりｗ個のワード、１ワードあたりｎビットの２ポートＣｓＲＡＭを検査するため、従来のＢＩＳＴコントローラのカラーを、あたかも（ｒ−１）行およびｃ列で、ポートあたり（ｗ／２）個のワード、１ワードあたりｎビットの２つの仮想単一ポートｓＲＡＭを相補的な検査データを用いて検査するように適用する。分割のモデルに応じて、仮想単一ポートｓＲＡＭはｒ行および（ｃ−１）列で、ポートあたり（ｗ／２）個のワード、１ワードあたりｎビットを有することもできる。ＢＩＳＴカラーは、同一および相補的の両方の検査データを用いて、４つの仮想単一ポート・メモリを検査するように修正することもできる。
【００８６】
ｋポートのＣｓＲＡＭの検査スケジュールは、ｋ個の仮想メモリを同時に検査するものである。好ましくは、仮想メモリは同じサイズである。
【００８７】
添付の請求項に定義された本発明の範囲から逸脱することなく、本発明の特定の実施形態に対し多くの修正、変型および適応を実施することが可能である。
【図面の簡単な説明】
【図１Ａ】２ポートのコンパクトｓＲＡＭ（ＣｓＲＡＭ）のアーキテクチャを示す。
【図１Ｂ】ＣｓＲＡＭについて使用される記号を示す。
【図２】本発明に従って、図１ＡのＣｓＲＡＭを検査するシステム・クロックおよび内部クロックの波形を示す。
【図３Ａ】図１Ａの２ポートＣｓＲＡＭおよび本発明に従った検査方法によって使用される用語を示す。
【図３Ｂ】検査方法の観点から見た簡略化された２ポートＣｓＲＡＭを示す。
【図４】本発明に従った２ポートＣｓＲＡＭに対する検査のステップを示す。
【図５】本発明に従った２ポートＣｓＲＡＭに対するａｔ−ｓｐｅｅｄでのＢＩＳＴのパラレル実施形態を示す。
【図６】本発明に従った２ポートＣｓＲＡＭに対するａｔ−ｓｐｅｅｄでのＢＩＳＴのシリアル実施形態を示す。
【図７】ローカル・コンパレータを備えた図５のＢＩＳＴカラーの別の実施形態を示す。
【図８】故障検出率が改善された検査に対する図５のＢＩＳＴカラーのさらに別の実施形態を示す図である。[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to memory testing methods and apparatus, and more particularly to a built-in self test (BIST) for testing multiport compact static random access memories (ie, CsRAM) at-speed.
[0002]
[Prior art]
A RAM (random access memory) comprises a plurality of storage elements or cells and a number of ports for each cell. In general, one port includes five connections accessible to external devices: data input, data output, clock, address, and control (write / read) connections. In a one-port memory, cells are accessed sequentially according to their addresses, and a data bit (0 or 1) is written to or read from each cell.
[0003]
New generation ASICs for the telecommunications industry require larger and faster memories. To address the increasing demands of data processing, compact sRAM (CsRAM) has been developed. CsRAM reduces the silicon area and peak power consumption of conventional memories. Compact static RAMs are currently used extensively on ASICs due to their high yield, low cost, and fast access time.
[0004]
CsRAM is a method for designing a multiport memory, in which a set of read / write circuits and an address decoding circuit are shared by a plurality of ports in a time slice manner. In other words, in a single system clock cycle, each port is given a portion of the cycle time to access the memory via the same read / write circuits and the same address decoder. CsRAM supporting the same number of ports occupies significantly less silicon area than conventional multiport memories.
[0005]
Conventionally, inspection of a memory element consists of writing a data pattern at a predetermined location, reading data from each location, and comparing the read data with the data that would have been written at that location. I have.
[0006]
In the past, memory elements were tested at the manufacturing site using an external tester that provided control, address and data signals to the memory under test, and their output data was evaluated to determine if the memory passed or failed. Was determined.
[0007]
As the density of memory cells on a single chip has increased, the need has arisen to test circuits after they have been packaged in an ASIC. Defects not detected during manufacturing inspection lead to unexpected failures in the field. However, testing a memory chip is not an easy task. For example, the number of connections to external devices is limited. Simply implementing multiple physical ports throughout the memory is too complex and impractical.
[0008]
Inspection of memory blocks embedded in ASICs is difficult. First, because high speed memories use small differential signal amplitudes, special inspection algorithms must be used, which makes short detection difficult. In addition, the number and types of errors are increasing with the scale of integrated circuits. As a result, the number of test patterns required for inspection of various types of defects, as well as the execution time of the patterns, increases with memory size.
[0009]
Furthermore, if the memory array is deeply embedded in the logic, accessing the memory for writing and reading and comparing the responses can be very difficult. As a result, test patterns required for defect evaluation of high-speed memory become more sophisticated, and as a result, inspection time and chip size further increase. A common solution to this problem is to implement a built-in self-test (BIST) by incorporating additional test circuitry into the chip itself. Incorporating BIST into an ASIC is an excellent way to achieve very high defect coverage with minimal inspection time.
[0010]
Current BIST controllers include a finite state machine (FSM) that provides a specific sequence of read, write, and compare operations. The test can be performed by the user whenever needed, or can be started automatically at startup. In this specification, "BIST" means an actual test, and "BIST controller" means a circuit that executes the BIST.
[0011]
The method of testing the CsRAM includes two partial tests. The first part is a scan test for the control logic of the CsRAM, and the second part is a conventional BIST that tests the memory itself. This method has good detection rates for static defects in both control logic and memory, but fails to detect many of the timing related defects in memory.
[0012]
That is, with the conventional memory inspection technique, when applied to CsRAM, a satisfactory defect detection rate cannot be obtained. This is mainly due to the fact that CsRAM operates with an internal clock that is several times faster than the system clock. At present, CsRAMs are tested at very low system clock speeds, so many of the timing related defects are not detected.
[0013]
[Problems to be solved by the invention]
There is a need for a practical method of inspecting CsRAM at maximum memory speed to detect all timing related defects in memory.
[0014]
[Means for Solving the Problems]
It is an object of the present invention to remedy all or some of the above disadvantages of prior art BIST controllers.
[0015]
It is another object of the present invention to detect most or all of the timing related defects in CsRAM using a standard built-in self test (BIST) controller. The method according to the present invention requires minimal addition of test circuitry around prior art memory arrays and minimal changes to prior art test algorithms. It should also be understood that the invention can be implemented as a one-piece, dedicated BIST controller.
[0016]
According to one aspect of the present invention, there is provided a method for testing a two-port compact static random access memory (CsRAM) at the operating speed of the CsRAM. The method includes a first test session and a second test session. The first session includes generating a first test data set and a second test data set that is the same as or complementary to the first set, wherein the first test is performed on a first partition of a CsRAM. Simultaneously writing a data set and writing the second test data set to a second partition, reading first output data from the first partition and second output from the second partition Reading the data, and comparing the first output and the second output to the first test data set and the second test data set, respectively, wherein the first output differs from the first test data Or if the second output differs from the second test data, declaring a failure.
[0017]
The second session includes simultaneously writing the first test data set to the second partition of the CsRAM and writing the second test data set to the first partition. Reading the first output data and reading the second output data from the first section, and comparing each output again with the first and second test data sets, respectively, such that the first output is the first test data set. If the test data is different or the second output is different from the second test data, a step of declaring a failure is included. This method of testing a two-port CsRAM is also applicable to testing a multiport CsRAM.
[0018]
According to another aspect of the present invention, there is provided a test circuit for a CsRAM having first and second ports. The circuit includes a first address multiplexer unit and a second port for a first port for selecting one of a test address and a system address in each of a first partition and a second partition of the CsRAM. And a first data to a first port for providing one of a test data word and a system data word in the first and second partitions, respectively. A second data multiplexer unit for the multiplexer unit and the second port, and for providing one of a test write / read instruction and a system write / read instruction for both the first and second partitions; , A first write / read multiplexer unit for the first port A second write / read multiplexer unit for the port and the second port, and simultaneously generating a test address, a test data word and a test write / read instruction on the first and second ports, and outputting output data from the CsRAM. A built-in self test (BIST) controller that receives and performs a test of the CsRAM at a memory operating speed faster than the system clock.
[0019]
The method according to the invention has the advantage that most or all of the timing-related defects in the CsRAM that cannot be covered by conventional inspection techniques are detected because the CsRAM is inspected at the operating speed of the memory.
[0020]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1A is a block diagram of the two-port CsRAM 10. In FIG. 1A, sRAM 15 is a conventional single-port static RAM. Latches 17, 19 are used at the input multiplexers 14, 16, 18 and at the output of the sRAM 15 to convert the single port sRAM 15 to a two port CsRAM. 2, the internal clock generator 12 uses the system clock sysClk to generate the internal clock f.₀And f₁Activate Clock f₀And f₁Are added in an adder 22 to obtain a memory clock Ckl. Clock f₁Is used to enable the input multiplexers 14, 16, 18 to select each data address and control signal for a memory cell, and to write / read data to / from that cell. Clock f₀And f₁Is the two ports p of the CsRAM 10₀, P₁Are also used by output latches 17 and 19 to provide a data output to each of them. Buffers 11, 13 and 21, 23 represent appropriate delays, but their configuration is determined by the technology used.
[0021]
FIG. 1B shows the symbols used to represent the inputs and outputs of the two-port CsRAM 10. Signal W₀, D₀, Add₀And Q₀Is the first port p of the CsRAM 10₀Write enable, data input, address and data output. Similarly, the signal W₁, D₁, Add₁And Q₁Is the second port p of the CsRAM 10₁Write enable, data input, address and data output.
[0022]
The operation of the two-port CsRAM 10 will be described with reference to FIGS. 1A, 1B, 2 and 3A. During each sysClk, the signal W₀/ W₁, D₀/ D₁And Add₀/ Add₁Is supplied to the CsRAM 10 after a certain interval a from the rise of sysClk. First, the generator 12 generates a first pulse f as shown in FIG.₀Generate At this point, f₁Is 0, this f₀The pulse is applied to the first port p₀Access to cell 15 'of line W₀, Add₀And D₀Enable W₀Is “1”, the write operation causes Add₀Cell 15 at the address preselected by₀Write. W₀Is "0", the read operation reads the contents of the cell 15 'and latches the result in the corresponding output latch 17.
[0023]
After a certain delay with respect to the rising edge of sysClk (this delay is indicated by b in FIG. 2), the generator 12 outputs a second clock pulse f₁Generate Pulse f₁Is the second port p₁Access to cell 15 'of line W₁, Add₁And D₁Enable f₀Is indicated by Δ. Pulse f₁Is the rising edge of sysClk or pulse f₀Can be generated by the rising edge of.
[0024]
FIG. 2 shows the system clock sysClk and the frequency f used to test a two-port CsRAM in accordance with the present invention.₀And f₁And the timing relationship between the two. As described above, each rising edge of sysClk is f₀Pulse and f₁Trigger pulse. sysClk, f₀And f₁The timing relationship between is fixed. In other words, f₀And f₁Is fixed and f₀And f₁Are also fixed with respect to the rising edge of sysClk, and f₀And f₁Is independent of the cycle time of sysClk. As a result, at each rising edge of sysClk, the CsRAM 10 is accessed twice at a fixed frequency 1 / Δ. Frequency 1 / Δ is typically the highest frequency allowed by sRAM technology and is specific to each type of memory.
[0025]
The use of CsRAM helps to reduce the silicon area of the multiport memory, thus allowing more functions to be implemented in the ASIC. Therefore, the inspection method of the CsRAM becomes more difficult. As mentioned above, the system clock is much slower than the internal clock (cki), so it is difficult to achieve high CsRAM test quality using conventional BIST techniques, especially for timing related faults. .
[0026]
FIG. 3A shows a two-port CsRAM 10 and is shown to define terms and test methods according to the present invention. FIG. 3B is a simplified diagram of the two-port CsRAM 10 from the viewpoint of the inspection method. It is understood that the method can be applied to multiport compact sRAMs as well, and that a two-port example is provided to illustrate the basic concept for testing multiport CsRAM. I want to be.
[0027]
In accordance with the present invention, to test a k-port CsRAM operating at least k times faster than sysClk, the CsRAM is divided into k partitions and accessed k times from k ports during one system clock cycle. ("K" is a positive integer). Preferably, the memory is divided into equal partitions. In the embodiment of FIG. 1, the conventional single-port sRAM 15 is divided into two equal sections and can be accessed from two independent ports using the same system clock generator 12.
[0028]
According to one embodiment of the present invention, CsRAM 10 comprises two equal sized partitions, for example, partition S.₀And S₁Logically divided into Each section S₀And S₁Use the same or complementary test data to generate different port p₀, P₁From the same time.
[0029]
The following notation is used to describe the inspection method. The number of words, that is, the size of the memory is represented by “w”, and “n” represents the number of bits per word per port. An n-bit word is illustrated at symbol 82. The CsRAM 10 is an array composed of c columns 83 and r rows 84. The index "i" is used to indicate the row address of cell 15 ', where i is 0, 1, 2,. . , (R-1). Index "j" is used to indicate the column address of cell 15 ', where j is 0, 1, 2,. . , (C-1).
[0030]
As mentioned above, each cell 15 'in the sRAM 15 has two ports, so there are two different row addresses for one cell. That is, one is port p₁And the other is port p₂It is about. Therefore, ar₀[I] and ar₁[I] is the port p₀And p₁Represents the row address for the same cell in the sRAM 15 when each is accessed. Similarly, each cell 15 'in the sRAM 15 has two different column addresses. That is, one is port p₀And the other is port p₁It is about. Thus, ac₀[J] and ac₁[J] represents a column address for the same cell 15.
[0031]
Port p₀Is accessed, the complete address of cell 15 'in sRAM 15 is
Add₀= ｛Ar₀[R-1],. . . , Ar₀[0], ac₀[C-1],. . . , Ac₀[0]｝
And port p₁Is accessed, the complete address of cell 15 'in sRAM 15 is
Add₁= ｛Ar₁[R-1],. . . , Ar₁[0], ac₁[C-1],. . . , Ac₁[0]｝
It is.
[0032]
FIG. 3B shows the section S₀And S₁FIG. 2 is a conceptual diagram of a CsRAM 10 divided into two sections. For complete fault detection, each port p₀, P₁Is section S₀And S₁Must be inspected once. In other words, two test sessions are required for the two-port CsRAM 10. In the first session, section S₀Is p₀At the same time as being inspected from₁Is p₁Inspected from. This is indicated by the dotted line in FIG. 3B. In this case, Add₀Is section S₀Define the cell location at₁Is section S₁Define the cell position in. In the second session, section S₀Is p₁At the same time as being inspected from₁Is p₀And the inspection of the entire CsRAM 10 is completed. In the second session, Add₀Is section S₁Define the cell location at₁Is section S₀Define the cell position in. This is indicated by the solid line in FIG. 3B.
[0033]
In addition, a parallel inspection of the memory is assumed for this method. That is, words are applied one at a time, and the test response is read one word at a time. Therefore, this method is also called "modified parallel BIST".
[0034]
The exemplary inspection method according to FIG. 3B does not require additional inspection time by using two inspection sessions. This means that each test session will only test half of the memory space, thus each test session will only test half of the test time, as compared to the conventional approach of testing the entire memory space in a single session for a single port sRAM. This is simply because
[0035]
The two sessions of the test method according to the invention can use the BIST used to test the sRAM, but the algorithm of this BIST is, for example, for one-port sRAM, A.I. J. Van de Gool, "Testing semiconductor memories" (Wiley Publishers, April 1996), and for a multiport conventional sRAM, see Wu et al. Proposed.
[0036]
These or other test algorithms are slightly modified to test a multiport CsRAM in accordance with the present invention. For example, this paragraph presents a modified March “C” minor (MARCH C-) inspection algorithm used to inspect CsRAM at-speed in accordance with the present invention. However, the invention is equally applicable to other BIST algorithms with only minimal modifications.
[0037]
FIG. 4 shows the steps of the inspection according to the invention. Steps, also referred to as march steps, intuitively represent that cells are continuously tested and that write and read operations "march" up and down from cell to cell. Accessing (examining) one sRAM at a time using a conventional BIST controller to examine the w-word (r row and c column) 2-port CsRAM 10 with n words of 1 word per port Sequentially examines two virtual single port sRAMs. Each virtual single port RAM has (w / 2) words consisting of 2n bits per word arranged in (r-1) rows and c columns. Alternatively, the single-port virtual memory may have (w / 2) words of 2n bits per word arranged in r rows (c-1) columns.
[0038]
These virtual CsRAMs 85 and 86 are shown in FIG. 4 as a gray area and a white area, respectively. It should be understood that such a separation into two virtual memories is not permanent and can be changed according to the marching steps performed during the test.
[0039]
As a result of this virtual or logical separation, the color of the conventional BIST controller is slightly modified to provide 2n bit wide test data and [(r-1) + c] bit addresses to memory 10. And a 2n bit wide test response must be confirmed. In addition, a conventional BIST controller must generate a memsel signal to select single port virtual memories 85 and 86 of CsRAM 10 for each write / read operation. This memsel is the row address ar of the CsRAM 10₀[R-1] and ar₁Used as the most significant bit of [r-1]. For example, if the first virtual sRAM 85 is p₀, Memsel = 0 and the second virtual sRAM 86₀If memsel = 1.
[0040]
In FIG. 4, the letters R and W represent read and write operations, respectively. The letters d and d￣ represent test data and complementary test data written / read from respective addresses. Arrows represent a March-up or March-down for each step. The direction of marching is represented by an index of "up (up)" and "dn (down)". S₀Or S₁Represents a partition to which a write / read operation is applied. The terms read-up, read-down, write-up, and write-down describe the direction of marching for operations performed in the respective virtual memory.
[0041]
Inspection data is applied at the rising edge of sysClk. Internal clock f₀Is generated first, so D₀The above inspection data is first stored in the address Add of the virtual memory 85.₀Applied to the cell at Within the same sysClk cycle, D₁The inspection data above is f₁Address Add at the rising edge of₁Applied to cells of As described above, Add₀And Add₁Represents two different storage cells, each in a different section of the memory 10.
[0042]
To create a transition to cover timing related faults, in the example of FIG.₀And p₁Have the exact opposite or complementary values. That is, D₁= D₀￣. This is the address Add₀Is written into the cell having the address "Add", the address Add₁Means that a logical value “0” is written in the cell having the same, and so on. In this way, during a read operation, each clock f₀And f₁According to the address Add₀And Add₁The complementary test response is read from.
[0043]
Two ports p₀, P₁And by using two sets of complementary test data for different addresses, the signals on lines D, Add and Q of CsRAM 10 become f₀And f₁Always switches for each pair of. This fast switching places maximum stress on the timing of associated circuits such as the sRAM cell 15 ', input multiplexers 14, 16, 18 and output latches 17, 19 shown in FIG.
[0044]
The method shown in FIG. 4 is performed in two sessions, each of the first and second sessions having six steps.
[0045]
The first test session consists of steps 1-6, each step performing a read / write operation on each virtual memory simultaneously and in opposite directions. As described above, when test data d is read from virtual memory 85 in a particular direction, complementary test data d # is written at that location in the same direction. When test data d is written in one direction in virtual memory 85, complementary test data d # is written in virtual memory 86 in the opposite direction.
[0046]
Step 1 is that the first test session writes (w / 2) test data words with increasing contiguous addresses in virtual memory 85 and has decreasing contiguous addresses in virtual memory 86 (w / 2) indicates that it starts with the writing of two complementary test data words. When Step 1 is completed, the data written in the virtual memories 85 and 86 have complementary values. The reading operation performed during step 1 is not relevant to the present inspection method.
[0047]
This can be expressed as follows.
[0048]
(Equation 1)

Here, d is 00. . . 000 or 0101. . . It is an arbitrary n-bit vector such as 0101.
Rd and Rd￣ are read^{d ( d￣ )}Represents an action.
Wd and Wd￣ are write^{d ( d￣ )}Represents an action.
(...): (...) represents two parallel operations on two ports.
Subscript upS₀(DnS₀) Is the section S₀Represents a march up (march down) test for.
Subscript upS₁(DnS₁) Is the section S₁Represents a march up (march down) test for.
[0049]
The second inspection session starts with step 7. In step 7, (w / 2) test data words are written to increasing consecutive addresses in virtual memory 86 and (w / 2) complementary test data words are written to decreasing sequential addresses in memory 85. Is written. The data written to the virtual memories 85 and 86 have complementary values, and the same rules apply as described in the first session above. The reading operation performed during step 7 is not relevant to the present inspection method.
[0050]
This can be expressed as:
[0051]
(Equation 2)

[0052]
As described above, each marching operation is performed through the entire address space of the corresponding memory partition, which is half the memory space of the entire 2-port CsRAM 10. Depending on the partitioning of the memory, the order of addresses for marching within each partition may or may not be contiguous. For example, Add except for the most significant bit of the row address₀Is Add₁And the division is the same in all bit positions,
ar₀[R-1] = ar₁[R-1], ar₀[R-2] = ar₁[R-2], ...,
ar₀[0] = ar₁[0],
ac₀[C-1] = ac₁[C-1], ..., ac₀[0] = ac₁[0]
And the addresses within the range of each memory section are continuous.
[0053]
Regardless of the division of the memory and the continuity of the inspection address, the fault detection rate according to the above algorithm is the same. Similarly, testing is performed at the memory operating speed and the system continues to operate at the system clock speed.
[0054]
FIG. 5 illustrates at 20 a modified collar 25 having a conventional BIST controller 30 for performing a parallel BIST according to the present invention. Bold connections represent buses, and bus sizes are shown in FIG. The circuits in the gray area 25 are defined as "BIST color". In this example, the BIST controller 20 is adapted to test the two-port CsRAM 10. Nevertheless, if one understands the operating principle and circuit for a two-port CsRAM, one can easily envision other variants of the collar 25 for other types of multiport CsRAM. Further, as described above, the use of the collar 25 enables the CsRAM 10 to be inspected at-speed with a slight change in the operation of the BIST controller 30.
[0055]
The collar 25 includes an address multiplexer 24, 24 ', a data multiplexer 26, 26', and a W / R multiplexer 28, 28 '. Each multiplexer has a corresponding port p₀And p₁Performs the respective functions. Color 25 is port p₀Lines 51, 53, 55, 60 and port p₁Through the lines 61, 63, 65, and 70 of the ASIC. When the multiplexer is connected to a functional block of the ASIC via a connection labeled "From functional block", it allows both normal modes of operation of the CsRAM 10 and also provides a connection to the BIST controller 30. Multiplexers are provided to allow operation of the CsRAM 10 in test mode when connected via
[0056]
Thus, p₀The address multiplexer 24 of the memory 10₀Receives an (r + c) bit wide address signal that identifies the row and column of the cell to be accessed. Port p₁Also receives an (r + c) bit wide address because the number of rows and columns of memory is the same for both ports. The BIST controller 30 generates an address for the (r-1) + c bit wide memory 10 on line 35 to fully identify each cell address in each partition. In addition, the BIST controller 30 provides a signal memsel on line 34 and the first section S₀And the second section S₁And an inverter 43 for selecting between the above. This signal is the most significant bit of the row address in this example. In other words, memsel is ar₀[R-1] and ar₁Replace [r-1]. The march up or march down address for each port is obtained through an inverter 42 located on the collar 25. Inverter 42 ensures that the addresses are opposite for simultaneous read and write operations of the two virtual memories. Inverter 44 allows BIST controller 30 to compare the same set of test responses.
[0057]
Data multiplexers 26 and 26 'receive n bits ("n" is the size of one word). Accordingly, the BIST controller 30 must generate n-bit wide inspection data on line 37 as the memory 10 is divided into two sections. This is the result of a virtual division of the memory 10 into two sections. Port p₀A second set of n-bit wide test data complementary to port p₁, An inverter 41 is used. R / W multiplexers 28 and 28 'receive a single bit control signal 38 indicating a read or write operation. If the control signal is “1”, a write operation is performed.
[0058]
As described with reference to FIG. 4, both virtual memories perform read or write operations simultaneously, but the addresses march in opposite directions and the data has complementary values. Thus, the control signals are the same for both ports. The test response on output lines 60 and 70 is n bits wide, and the test response is used by BIST controller 30 to determine if the data written to the cell is the same as the data read from the cell. Used by Both the BIST controller 30 and the CSRAM 10 are synchronized by a system clock sysClk, indicated by reference numeral 36.
[0059]
As described above, the modified BIST controller 20 has a normal mode and an inspection mode. When bis_en = 1 arrives, the signal biston on line 39 selects the data from the buffers / multiplexers (24, 26, 28) and (24 ', 26', 28 ') and the BIST is started. The controller 30 first sets memsel to “0”,₀[R-1] = 0 and ar₁[R-1] = 1. In this case, the BIST controller 30₀Through the lower half S of the memory space₀And inspect port p₁Through the upper half S of the memory space₁But the marching proceeds in the opposite direction. During this session, the BIST performs the marching steps 1-6 of FIG. 4 to complete the MARCH C-test on half of the conventional sRAM.
[0060]
When the first test session is completed, the BIST controller 30 sets memsel = 1 and repeats the same MARCH C-test. During the second session, ar₀[R-1] = 1 and ar₁[R-1] = 0, and the BIST controller 30₁Through the lower half S of the memory space₀And inspect port p₀Through the upper half S of the memory space₁To inspect. The second inspection session corresponds to steps 7-12 described with reference to FIG. When this test is completed, the BIST controller 30 sets the signals bis_done and bis_pass accordingly.
[0061]
In view of software changes compared to a conventional BIST controller, this embodiment requires the conventional BIST controller 30 to generate at least n-bit wide test data and confirm a 2n-bit wide test response. I do.
[0062]
From a hardware point of view, (2n + r + c) inverters are added to the BIST controller 25. That is, n inverters 41, n inverters 44, (r-1 + c) inverters 42, and one inverter 43 are added. Note that conventional BIST controllers require the same number of multiplexers as controller 20 of FIG. Furthermore, the silicon area and associated overall peak power consumption in the ASIC is reduced. This is because the present invention is designed to test a much smaller amount of CsRAM than a conventional compact sRAM of the same capacity.
[0063]
From a test time point of view, a serial test according to the present invention requires the same time as a conventional test of a single port sRAM of the same size. Compared to a conventional test of a two-port sRAM, the test time according to the embodiment of FIG. 5 is only half.
[0064]
The modified BIST controller 20 requires more inverters as compared to the conventional BIST embodiment, while the modified BIST controller provides n-bit wide test data to be used. Therefore, the inspection method according to the present invention provides higher accuracy because twice the inspection data and the inspection response are used as compared with the conventional method. In addition, tests are performed at a memory operating speed that is at least twice as fast as the system clock to detect timing related faults.
[0065]
FIG. 6 shows another embodiment 40 of the present invention. In this embodiment, a serialized BIST controller is used to test the 2-port CsRAM. This embodiment is recommended for ASICs sharing a single BIST controller among multiple memories. If a large number of memories are widely distributed on the ASIC, a shared parallel BIST controller 20 as shown in FIG.
[0066]
The serial memory BIST controller 40 of FIG. 6 minimizes this overhead by providing a single bit test input to all virtual memories and receiving a single bit test response from each virtual memory. In addition to wiring savings, serialization requires a BIST controller hard drive because the controller generates single-bit test data for both ports of the CsRAM and receives a single-bit test response from each port of the CsRAM. Hardware requirements are also reduced.
[0067]
Also in this example, the memory to be tested is the 2-port CsRAM 10 having r rows, c columns, w words per port, and n bits per word. Serial BIST 40 operates using the Serial MARCH Test (SMARCH) described in US Pat. No. 4,969,184, assigned to the same assignee as the present invention, and is incorporated herein by reference.
[0068]
All (RdWd￣) and (Rd￣Wd) operations are (R0W1)ⁿ(R1W1) and (R1W0)ⁿ(R0W0), the same principle as that shown in FIG. 4 can be applied to the serial inspection method.
[0069]
In FIG. 6, the shaded area representing the serial BIST color 25 'is an address multiplexer (24, 24'), a data multiplexer (26, 26 '), an R / W multiplexer (28, 28') and an inverter. 41-44. The single-bit check data Simem is transmitted from the BIST controller 30 'to the port p.₀Least significant bit D of₀[0] applied via line 37 to the single bit check data
(Equation 3)

Is port p₁Least significant bit D of₁Applied to [0]. D₀And D₁The remaining (n-1) bits of output line Q₀And Q₁Respectively. In other words,
(Equation 4)

It is. Most significant output bit Q₀[N-1] and inverted bit Q₁￣ [n-1] = Q₀[N-1] is sent back to the BIST controller 30 for evaluation.
[0070]
In the embodiment of FIG. 6, the BIST controller 40 should test the two virtual memories simultaneously by giving both memories a single bit test and evaluating the single bit test response from each virtual memory. For such a configuration, the serial BIST controller 40 includes a single-bit comparator (not shown) for each output port of the CsRAM 10.
[0071]
The serial CsRAM @ BIST controller 40 operates as follows. When bis_en is received and biston is generated on line 39, BIST mode is enabled, memsel = 0 is set, and port p₀Through the lower half S of the CsRAM 10₀And inspect port p₁Via the upper half S of the CsRAM 10₁To inspect. As described above, the single-bit inspection data symem is generated by the controller 30 and p₀Supplied in
(Equation 5)

Is p₁Supplied in. Q₀/ D₀And Q₁/ D₁Performs (n-1) feedback on the collar 25 'to perform the shift operation of the serial inspection. Most significant output bit Q₀[N-1] and Q₁￣ [n−1] is evaluated in parallel by the BIST controller 30. Because of the inversion on input inverter 41 and output inverter 44, the test responses from both ports are always the same (ie, Q₀[N-1] = Q₁[N-1]). When this check is completed, the BIST controller 30 sets memsel = 1 and sets the port p₁Through the lower half S of the memory space₀To inspect. When the second test is completed, the controller sets bis_done = 1 and bis_pass accordingly.
[0072]
Compared to a conventional BIST controller, the CsRAM serial BIST 40 requires (r + c + 2) extra inverters in the collar 25 ′ to evaluate two output bits of the same value, and the BIST controller 30 has two, three, Requires two gates. As described above, the most significant output bits are compared (Q₀[N-1] = Q₁{[N-1]), which is different from the one-bit output in the conventional S-MARCH embodiment.
[0073]
From a test time point of view, a serial test according to the present invention requires the same time as a conventional test of a single port sRAM of the same size. Compared to a conventional test of a two-port sRAM, the test time according to the embodiment of FIG. 6 is only half.
[0074]
The embodiment of FIG. 7 illustrates a modification of the collar 25 of FIG. 5 to be used with a BIST controller 30 designed to generate n-bit wide test data and verify an n-bit wide test response.
[0075]
The first set of n-bit wide test responses on line 60 are compared in BIST controller 30 and input to adder 66, as described above in connection with FIG. Another set of n-bit wide test responses on line 70 are sent to summer 56. A detector 57 connected to the output of the adder 56 is a (1; 0) detector, which sets its output to "1" when it detects a mismatch between the two sets of test responses, 1 ".
[0076]
The output of detector 57 controls the input of AND gate 58 through inverter 59, while the signal bis_pass controls the other input of AND gate 58. The output of AND gate 58 provides a signal bis_pass_combined that is "1" if no fault is detected in the memory.
[0077]
The BIST color configuration of FIG. 7 can also be used in a serial BIST embodiment.
[0078]
FIG. 8 shows another embodiment of the BIST collar 25. The BIST collar 25 includes an encoder 72 having output-0 and output-1, and two XOR gates 67, 68 replacing the inverters 41 and 44 of FIG. 5, respectively. Using the configuration shown in FIG. 8, the BIST controller 30 is designed to execute the following functions for the CsRAM 10 having two ports, W words, and n bits per word. That is, (a) four (4) virtual single-port memories having (w / 2) words and 2n bits per word are checked, and (b) one virtual memory is checked at that time. Accordingly, a 4-bit memory select signal, for example, a memsel [3: 0] signal for testing each section 85, 86 of the memory 10 four times is generated.
[0079]
Encoder 72 is connected to memsel [3: 0] on line 34 and controls the selection of either the same or complementary test data. Similarly, encoder 72 determines which of blocks 85, 86 to check, and port p₀Or p₁To control which one should be used. For example, if output-1 connected to the data bus is "0", the test is performed using the same data in two sessions corresponding to two sections of the CsRAM 10 selected via output-0. Be executed. If output-1 of the encoder 72 is "1", the test is performed using the complementary test data as described above with reference to FIG.
[0080]
The output-0 of the encoder 72 determines which partition of the memory 10 is connected to the port p.₀, P₁Used to select from which to test. If output-0 is "0", p₀Inspects parcel 85 and p₁Inspects section 86. Otherwise, p₀Inspects parcel 86 and p₁Inspects section 85.
[0081]
In this manner, each section of the CsRAM 10 is inspected four times. For complete failure detection, the same inspection data is used twice when output-1 = 0, and the output is output twice another time. The test is performed using complementary test data when -1 = 1. Table 1 shows the function of the encoder 72.
[0082]
[Table 1]

[0083]
The BIST color configuration of FIG. 8 can be used with the serial BIST embodiment as well.
[0084]
In accordance with the present invention, a new BIST approach is provided to achieve at-speed inspection quality for a compact sRAM 10 that has at least k times faster operating speed than the system clock generator 12. As described above, the testing of the CsRAM can be performed using a conventional BIST controller 30, 30 'in which all necessary modifications are incorporated into the memory collars 25, 25'. The only costs required are those associated with the color 25, 25 'around the CsRAM to be tested to perform a parallel or serial test.
[0085]
To test a 2-port CsRAM with w words per port and n bits per word at r rows and c columns, the color of the conventional BIST controller is changed as if (r-1) rows and c columns at It is applied to test (w / 2) words, two virtual single-port sRAMs with n bits per word using complementary test data. Depending on the model of partitioning, the virtual single-port sRAM may also have (w / 2) words per port and n bits per word, with r rows and (c-1) columns. The BIST color can also be modified to test four virtual single-port memories using both the same and complementary test data.
[0086]
The inspection schedule of the k-port CsRAM is to inspect k virtual memories simultaneously. Preferably, the virtual memories are of the same size.
[0087]
Many modifications, variations and adaptations may be made to particular embodiments of the invention without departing from the scope of the invention as defined in the appended claims.
[Brief description of the drawings]
FIG. 1A shows the architecture of a two-port compact sRAM (CsRAM).
FIG. 1B shows symbols used for CsRAM.
2 shows waveforms of a system clock and an internal clock for testing the CsRAM of FIG. 1A according to the present invention.
FIG. 3A illustrates terms used by the two-port CsRAM of FIG. 1A and a test method according to the invention.
FIG. 3B shows a simplified two-port CsRAM from a test method perspective.
FIG. 4 shows the steps of testing for a two-port CsRAM according to the invention.
FIG. 5 illustrates a parallel embodiment of a BIST at-speed for a two-port CsRAM according to the present invention.
FIG. 6 illustrates a serial embodiment of a BIST at-speed for a two-port CsRAM according to the present invention.
FIG. 7 illustrates another embodiment of the BIST color of FIG. 5 with a local comparator.
FIG. 8 illustrates yet another embodiment of the BIST collar of FIG. 5 for inspection with improved fault coverage.

Claims (23)

A method for testing a two-port compact static random access memory (CsRAM) at the operating speed of the CsRAM,
(A) generating a first test data set and a second test data set;
(B) writing the first set of test data to a first partition of the CsRAM via a first port, and writing the second test data set to a second partition of the CsRAM via a second port Write the test data set simultaneously,
(C) reading first output data from the first section through the first port, reading second output data from the second section through the second port,
(D) comparing each of the first output and the second output with the first test data set and the second test data set, respectively, wherein the first output is the first test data set and the second test data set; A method comprising declaring a failure if different from test data or if the second output is different from the second test data. (E) writing the first set of test data to the second partition of the CsRAM via the first port, and writing the second test data set to the first partition via the second port Simultaneously writing the test data sets,
(F) reading the first output data from the second partition via the first port, reading the second output data from the first partition via the second port,
(G) comparing each of the first output and the second output again with the first test data set and the second test data set, wherein the first output is the first test data set and the second test data set; The method of claim 1, further comprising declaring a failure if different from test data or if the second output is different from the second test data. The generating step includes:
Generating w / 2 first words for the first set of test data;
The method of claim 1, comprising providing w / 2 second words, each having a binary value complementary to a corresponding first word, for the second set of test data. Performing the writing simultaneously,
Writing the first word to continuously increasing addresses of the first section;
4. The method of claim 3, comprising writing the second word to a continuously decreasing address of the second partition. The reading step includes:
Reading the first word from a continuously increasing address of the first section;
5. The method of claim 4, comprising reading the second word from a continuously decreasing address of the second partition. Performing the writing simultaneously,
Writing the first word to successively decreasing addresses of the first section;
4. The method of claim 3, comprising writing the second word to a continuously increasing address of the second partition. The reading step includes:
Reading the first word from a continuously decreasing address of the first section;
7. The method of claim 6, comprising reading the second word from a continuously increasing address of the second partition. The address in one of the first and second partitions includes a row number and a column number according to the size of the CsRAM, and the most significant bit of the row address is used as a memory partition selection signal. The method described in. The method of claim 1, wherein the writing and reading steps include writing test data one bit at a time and reading test results one bit at a time. The method of claim 1, wherein the writing and reading steps include writing and reading one word at a time. The method of claim 1 for a multiport CsRAM. The method of claim 1, wherein the first partition and the second partition are each half the size of the CsRAM. The method of claim 1, wherein the first test data set includes the same data as the second test data set. A test circuit for a CsRAM having first and second ports,
A first address multiplexer unit for the first port and the second port for selecting one of a test address and a system address in each of a first partition and a second partition of the CsRAM; A second address multiplexer unit for
A first data multiplexer unit for the first port and the first data multiplexer unit for providing one of a test data word and a system data word in each of the first partition and the second partition; A second data multiplexer unit for the two ports;
A first write / read multiplexer unit for the first port for providing one of a test write / read command and a system write / read command for both the first and second partitions; and A second write / read multiplexer unit for the second port;
A test address, a test data word and a test write / read command are simultaneously generated on the first and second ports to receive output data from the CsRAM and to test the CsRAM at a memory operation speed faster than a system clock. A built-in self test (BIST) controller to perform;
Inspection circuit including. Each of the first address multiplexer unit and the second address multiplexer unit has (r + c) address connections with the BIST controller and provides a memory select signal to each respective port. The inspection circuit according to claim 14, wherein the test circuit provides one of (r-1) row addresses and c column addresses, or r row addresses and (c-1) column addresses. The BIST controller is:
N input data connections with each of the first data multiplexer unit and the second data multiplexer unit for providing an n-bit check word to each respective port;
2n output data connections with the CsRAM to receive an n-bit word test response from each respective port;
The test circuit according to claim 14, comprising: The BIST controller is:
N-bit wide input data with each of the first data multiplexer unit and the second data multiplexer unit for providing an n-bit check word to each of the first and second ports Connection and
An n-bit wide output data connection with the CsRAM for receiving an n-bit word response from the first port;
Means for comparing an n-bit word response from the second port with an n-bit word response from the first port;
The test circuit according to claim 14, comprising: The test circuit further comprises an address inverter for each of the address connections for the second port and a partition select inverter for the second port;
The BIST controller generates the test address for the first partition, and the address inverter provides a complementary binary value of the test address for the second partition. Item 17. The inspection circuit according to Item 16. The test circuit further comprises an input data inverter for each of the input data connections to the second port;
The BIST controller generates the test data for the first partition, and the input data inverter provides a complementary binary value of the test data for the second partition. The inspection circuit according to claim 16. The test circuit further comprises an output data inverter for each of the output data connections to the second port;
17. The test circuit of claim 16, wherein the output data received by the BIST controller from the first and second partitions is the same. For each respective port, each of the first data multiplexer unit and the second data multiplexer unit is connected to the corresponding (n-1) output data connections from the CsRAM by (n- 1) having input data connections and input test connections from the BIST controller to provide single-bit test data to the CsRAM;
The BIST controller having an output test connection with the CsRAM for receiving a most significant output bit from the first port and the second port in response to the single bit test data;
The inspection circuit according to claim 16. 22. The test circuit of claim 21, wherein the single bit test data is applied to least significant bits of the first and second ports. The test circuit according to claim 14, wherein the first section and the second section are each half the size of the CsRAM.

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