WO2012070669A1

WO2012070669A1 - Method and system for generating circuit information for programmable logic device, circuit testing device and computer program therefor, device and computer program for creating circuit data, and computer readable storage medium

Info

Publication number: WO2012070669A1
Application number: PCT/JP2011/077284
Authority: WO
Inventors: 粟島　亨
Original assignee: 日本電気株式会社
Priority date: 2010-11-24
Filing date: 2011-11-21
Publication date: 2012-05-31

Abstract

Provided is a system for testing a programmable logic device (PLD) and generating circuit information by which the utilization rate of a partially defective PLD can be improved and the utilization rate can be quantitatively understood. This system for testing and generating circuit information comprises a testing means for testing a failed PLD that has failed a test of PLD programmable resources, and generating information that specifies the defective programmable resources by testing the malfunctioning programmable resources inside the defective PLD, and a generating means for generating circuit information that will avoid the defective malfunctioning programmable resources and, using the PLD, realize the desired logic circuit on the basis of information that represents the desired logic circuit and the information that has been generated by the testing means and that specifies the defective programmable resources.

Description

Circuit information generation method and system for programmable logic device, circuit inspection apparatus and computer program thereof, circuit information generation apparatus and computer program thereof, and computer-readable storage medium

The present invention relates to the technical field of inspection of programmable logic devices and circuit synthesis.

2. Description of the Related Art Programmable logic devices (hereinafter sometimes abbreviated as “PLD”) such as FPGA (Field Programmable Gate Array) in which a user can program a desired logic circuit are in widespread use. According to the PLD, the user can relatively easily realize the logic circuit desired by the user.
However, in order to secure the realization and configuration of the user-desired logic circuit, the manufacturer is required to supply a PLD free from defects (failures) in the manufacturing process. However, in an actual manufacturing process, a defective product (hereinafter sometimes referred to as “defective device”) is generated that includes a part of a programmable resource such as a memory or a register in the PLD that has failed.
Even if such a defective device is not a complete defective product, it should be eliminated before being shipped to the market in order to ensure versatility and flexibility for programming by the user, which is a feature of the PLD. For this reason, manufacturers need to provide complete non-defective products to the market by performing various inspections prior to shipment of PLDs. Performing various inspections is an obstacle and a problem in reducing the cost of PLD.
From such a background, Patent Document 1 (Japanese Patent No. 4317013) performs an inspection based on configuration data that defines a logic circuit for a specific application for a defective device including a failure in at least one place. When it is confirmed that the circuit functions sufficiently, an inspection technique for discriminating the defective device as a good product only for the specific application is disclosed. According to the inspection method disclosed in Patent Document 1, there is a case where a manufacturer can ship even if it is not a completely good product that has passed various inspections.

Japanese Patent No. 4317013

[Problems to be solved by the invention]
However, the inspection method described in Patent Document 1 is an ad hoc because it is a test by trial and error with respect to a defective device targeting logic circuits of different specific uses desired by the user. For this reason, in the inspection method described in Patent Document 1, whether or not the configuration data defining the target specific-use logic circuit uses a failed resource included in the defective device is controlled by chance. ing. That is, since the inspection method is governed by the contingency based on the combination of the PLD including a part of the failure and the contents of the configuration data, the usage rate (yield) of the PLD is quantitatively grasped. I can't.
In the inspection method described in Patent Document 1, it is necessary to add an inspection circuit to the configuration data of the PLD when executing the inspection. For this reason, with this inspection method, it is not possible to inspect the configuration data that is completely identical to the configuration data of the PLD that defines the circuit for the specific application.
In the inspection method described in Patent Document 1, due to the inspection method, the manufacturer of the PLD obtains design information (a netlist or the like) of the logic circuit for a specific application desired by the user from the user in advance. At the same time, it is necessary to handle configuration data that defines a logic circuit for a specific application. For this reason, if the manufacturer mishandles, the confidentiality of design information created by the user may not be maintained.
Therefore, the present invention mainly aims to provide a circuit inspection device, a circuit information generation device, and the like that can realize an improvement in the utilization rate of a programmable logic device partially including a failure and a quantitative grasp of the utilization rate. .

In order to achieve the above object, a circuit information generation method according to the present invention has the following configuration.
In other words, the circuit information generation method according to the present invention avoids the failed programmable resource based on the information indicating the desired logic circuit and the information specifying the failed programmable resource inside the programmable logic device, and the programmable information generation method. Circuit information for realizing the logic circuit is generated using a logic device.
Further, for example, the information for identifying the failed programmable resource may be determined for the failed programmable logic device that has failed in the inspection of the programmable resource included in the programmable logic device prior to the generation of the circuit information. It may be obtained by inspecting a faulty programmable resource within a passing programmable logic device.
In the above case, for example, the information specifying the programmable resource may include at least position information regarding the programmable resource that has failed in the failed programmable logic device.
In order to achieve the above object, the circuit inspection apparatus for a programmable logic device according to the present invention targets a failed programmable logic device that has failed in the inspection of the programmable resource of the programmable logic device. By checking the failed programmable resource inside the acceptable programmable logic device, information identifying the failed programmable resource is generated.
Moreover, in order to achieve the said objective, the circuit information generation device of the programmable logic device which concerns on this invention is based on the information which specifies the desired programmable logic device, and the information which identifies the programmable resource inside the programmable logic device. The faulty programmable resource is avoided and circuit information for realizing the logic circuit is generated using the programmable logic device.
In addition, the computer program which implement | achieves the circuit information generation method of the programmable logic device which has each said structure, a circuit test | inspection apparatus, or a circuit information generation apparatus with a computer, and the computer program are stored for the same purpose. It is also achieved by a computer-readable storage medium.
Furthermore, for the same purpose, information for specifying a failed programmable resource inside the failed programmable logic device was stored for the failed programmable logic device that failed in the inspection of the programmable resource of the programmable logic device. This is also achieved by a computer-readable storage medium.
According to the present invention described above, it is possible to provide a circuit inspection device, a circuit information generation device, and the like that can improve the utilization rate of a programmable logic device partially including a failure and quantitatively grasp the utilization rate. .

It is a block diagram which shows the structure of the circuit inspection apparatus of the programmable logic device which concerns on exemplary 1st Embodiment of this invention. It is a block diagram which shows the structure of the circuit information generation apparatus of the programmable logic device which concerns on 1st exemplary embodiment of this invention. It is a block diagram which shows the structure of the test | inspection of the programmable logic device which concerns on 2nd exemplary embodiment of this invention, and a circuit synthesis system. It is a flowchart which shows the test | inspection and circuit synthesis | combination procedure using the test | inspection of a programmable logic device and circuit synthesis system which concern on 2nd exemplary embodiment of this invention. In exemplary 2nd Embodiment of this invention, it is a figure explaining the relationship between the pattern of the failure position (failure location) of a programmable logic device, and composition data for specific uses. In exemplary 2nd Embodiment of this invention, it is a figure explaining the relationship between the pattern of the failure position (failure location) of a programmable logic device, and composition data for specific uses. It is a figure explaining the test | inspection of the programmable logic device which concerns on the modification of 2nd exemplary embodiment of this invention, and operation | movement of a circuit synthesis system. It is a block diagram which illustrates the composition of the comprehensive inspection device of the programmable logic device concerning the exemplary 3rd embodiment of the present invention, the circuit synthesis device for specific uses, and the inspection device for specific uses.

Next, embodiments of the present invention will be described in detail with reference to the drawings.
<First Embodiment>
FIG. 1A is a block diagram showing a configuration of a circuit inspection apparatus for a programmable logic device according to the first exemplary embodiment of the present invention. FIG. 1B is a block diagram showing a configuration of a circuit information generation device for a programmable logic device according to the first exemplary embodiment of the present invention.
The PLD circuit inspection device 51 shown in FIG. 1A examines a failed programmable resource inside the failed PLD for a PLD that has failed in a comprehensive inspection of the programmable resources of the PLD (failed PLD). By doing so, information 61 specifying the failed programmable resource is generated.
The PLD circuit information generation device 52 shown in FIG. 1B is based on information 61 that identifies the failed programmable resource and information (design information such as a netlist) 62 that represents a desired logic circuit. By avoiding (not using) resources, the PLD is used to generate circuit information 63 for realizing the logic circuit represented by the design information 62.
Here, the circuit information 63 is, for example, configuration data that defines a logic circuit represented by the design information 62. Moreover, the information 61 specifying the failed programmable resource may include, for example, at least position information regarding the programmable resource that has failed in the failed PLD. Then, by writing the circuit information 63 to the rejected PLD by a general device (not shown in FIG. 1), the application is specified for the logic circuit represented by the design information 62. It can be used as a good product.
In the present embodiment, the information 61 for specifying the failed programmable resource is, for example, various portable computer-readable storage media (CD-R, USB (Universal Serial Bus) memory, etc.), or general such as the Internet What is necessary is just to provide suitably from the user of the circuit test | inspection apparatus 51 to the user of the circuit information generation apparatus 52 via a general communication line.
According to the PLD circuit inspection apparatus 51 and the circuit information generation apparatus 52 according to the present embodiment as described above, an improvement in the utilization ratio and utilization ratio of the PLD that has failed in the comprehensive inspection due to a partial failure. Can be quantitatively grasped.
<Second Embodiment>
Next, a second embodiment based on the above-described first embodiment will be described. First, the configuration and operation procedure of the PLD inspection and circuit synthesis system according to this embodiment will be described with reference to FIGS. FIG. 2 is a block diagram showing the configuration of a programmable logic device inspection and circuit synthesis system according to the second exemplary embodiment of the present invention. FIG. 3 is a flowchart showing a test and circuit synthesis procedure using the programmable logic device test and circuit synthesis system according to the second exemplary embodiment of the present invention.
The inspection and circuit synthesis system shown in FIG. 2 roughly includes a processing device 110 and a storage device 120. The processing device 110 and the storage device 120 are connected by general communication means (not shown). The processing device 110 can write information into or read information from the storage device 120 by a general method.
The processing apparatus 110 includes a comprehensive inspection unit 111, an application specific circuit synthesis unit 112, and an application specific inspection unit 113. The storage device 120 includes failure position data (failure position list) 121, a special purpose netlist 122, and special purpose configuration data 123.
Here, the comprehensive inspection unit 111 includes the function of the circuit inspection apparatus 51 in the first embodiment described above. The failure position data 121 corresponds to the information 61 that identifies the failed programmable resource in the first embodiment described above. The application specific circuit synthesis unit 112 corresponds to the circuit information generation device 52 in the first embodiment described above. The application specific netlist 122 corresponds to the design information 62 representing the desired logic circuit in the first embodiment described above. The application-specific configuration data 123 corresponds to the circuit information 63 in the first embodiment described above. In other words, the configuration data 123 for a specific application is circuit information that defines the logic circuit for realizing the logic circuit for the specific application inside the PLD.
(Comprehensive inspection unit 111)
The comprehensive inspection unit 111 performs a comprehensive inspection on a PLD (device to be inspected) to be inspected, and determines whether or not the device to be inspected passes the comprehensive inspection (step S1, FIG. 3). Step S2). In the comprehensive inspection, it is inspected whether all the various programmable resources constituting the PLD operate according to a predetermined specification without any problem.
Here, various programmable resources are, for example, various circuit elements such as input / output elements, resistors, transistors, logic gates, memories, and registers, and wirings. Such various programmable resources include not only these single resources but also blocks composed of a plurality of types of elements such as logic gates, memories, and CPUs.
Each programmable resource included in the device to be inspected is previously assigned identification information RP that can specify the type of resource (resource attributes such as wiring and circuit elements) and the position of the resource in the device. The comprehensive inspection unit 111 determines whether the reason for the failure is a fatal defect for the device to be inspected that has failed the comprehensive inspection (NO in step S2 in FIG. 3, step S4).
Here, as the “fatal defect”, for example, when the PLD does not operate at all due to a failure in the power line of the PLD, or the ratio of the failed programmable resources to the whole is a predetermined value. As described above, a serious failure state is assumed such as when it is difficult to avoid the failed programmable resource in the circuit synthesis process.
Then, the comprehensive inspection unit 111 determines that an inspected device having a fatal defect is a discard candidate (YES in step S4 in FIG. 3, step S5).
Then, the comprehensive inspection unit 111 determines that the device to be inspected that has passed the comprehensive inspection is “non-defective product (completely good product)” (YES in step S2 in FIG. 3, step S3).
On the other hand, in the case of an inspected device that is determined not to be a fatal defect among the inspected devices that have failed the comprehensive inspection (NO in step S4 in FIG. 3), the comprehensive inspection unit 111 Generates failure location data 121 in which identification information RP corresponding to the location of the defective programmable resource (failure location, failure location) is associated with the identification information (hereinafter referred to as “device ID”) of the found device to be inspected To do. The comprehensive inspection unit 111 stores the generated failure position data 121 in the storage device 120 (step S6 in FIG. 3).
Here, an example of a procedure for generating the failure position data 121 will be described. General failure inspection (general inspection) for a device under test includes (1) input of a test data sequence to the device under test, (2) observation of output from the device under test for that input, and (3) This is performed by collating the output result with an expected value prepared in advance.
In such a general comprehensive inspection, it is important to shorten the inspection time by compressing or omitting the inspection data series. That is, in a general comprehensive inspection, the main purpose is to detect the presence or absence of a failure in the entire PLD, and it is not always necessary to specify the location of the failed programmable resource.
However, each inspection data series guarantees at least the detection of a single failure of the programmable resource. For this reason, if the failure inspection for each programmable resource in the PLD (device to be inspected) to be inspected is performed in detail, the position of the failed programmable resource can be specified.
That is, the comprehensive inspection unit 111 according to the present embodiment applies a more detailed failure inspection (secondary inspection) to the PLD that has failed in the comprehensive inspection performed as the primary inspection, It is assumed that the fault location is specified. Examples of such secondary inspection are not limited to inspection by a semiconductor tester. For example, as a secondary inspection, an embodiment in which an inspection program is executed in a state mounted on a substrate is also assumed.
(Application-specific circuit synthesis unit 112)
The storage device 120 stores a special purpose netlist 122 prepared in advance for a specific purpose. Since this net list is data generated by a general method at present, detailed description in this embodiment will be omitted. The application specific circuit synthesis unit 112 refers to the failure position data 121 and the application specific netlist 122 stored in the storage device 120, thereby configuring the configuration data 123 that defines the logic circuit for the application. Is generated (step S7 in FIG. 3).
That is, at the time of circuit synthesis in this embodiment, the circuit synthesis unit 112 for specific applications refers to the device ID of the PLD to be synthesized among the failure position data 121 stored in the storage device 120 as a search key. Fault location data associated with the device ID is obtained. The application-specific circuit synthesis unit 112 generates configuration data that is not adversely affected by the failed resource included in the PLD by referring to the acquired failure position data.
More specifically, the circuit synthesizer 112 for specific applications avoids the programmable resources corresponding to the identification information RP by referring to the identification information RP included in the failure position data 121 and the net list 122 for specific applications. Then, place and route (do not use). As a result, the circuit synthesis unit 112 for the specific application generates configuration data for the specific application in which the programmable resource causing the malfunction is not activated.
Then, the application specific circuit synthesis unit 112 stores the generated configuration data 123 in the storage device 120.
(Special purpose inspection unit 113)
The application-specific inspection unit 113 refers to the configuration data 123 stored in the storage device 120 to identify the programmable resources used by the target application-specific logic circuit. It is checked that the programmable resource operates correctly (step S8 in FIG. 3). The application-specific inspection unit 113 determines that the device to be inspected that has passed this inspection is a non-defective product limited to the specific application (YES in step S9 in FIG. 3, step S11). On the other hand, the application-specific inspection unit 113 stores the device to be inspected that has been rejected in preparation for a discard candidate or other specific application (NO in step S9 in FIG. 3, step S10).
Next, the relationship between the failure position data 12 and the application-specific configuration data 123 will be described with reference to FIGS.
FIGS. 4 and 5 are diagrams for explaining the relationship between the pattern of the failure position (failure location) of the programmable logic device and the application-specific configuration data in the second exemplary embodiment of the present invention.
First, in FIG. 4, a lattice-like matrix virtually represents programmable resources such as logic and wiring included in the PLD (300, 330, 340) or configuration data 123 (310, 320). In FIG. 4, the failure positions (failure points) of these PLDs are indicated by “x” marks as indicated by reference numeral 301.
Further, in FIG. 4, hatched

portions

311 and 321 shown in the

configuration data

310 and 320 conceptually represent portions (patterns) that actually use programmable resources in the configuration data. The hatched

portions

331 and 342 shown in the

PLDs

330 and 340 conceptually represent programmable resources actually used in the PLD based on the configuration data.
That is, the configuration data 310 and the configuration data 320 illustrated in FIG. 4 exemplify configuration data that defines logic circuits for different specific applications. The use patterns (311 and 321) of the programmable resources that define these logic circuits are different.
In the PLD inspection and circuit synthesis system according to this embodiment described above, a case where the comprehensive inspection unit 111 generates information indicating the failure position 301 of the PLD 300 illustrated in FIG. In this case, the application specific circuit synthesis unit 112 performs logic synthesis (placement and routing) in consideration of the failure location data 121. For this reason, even if the PLD 300 having the failure location 301 is employed, the configuration data 310 generates a programmable resource pattern 311 where the failure location is avoided. Therefore, when a PLD 330 for a specific application, which is the final product, is generated based on the configuration data 310, the pattern 331 of the programmable resource used in the PLD overlaps with the failure location 301 that the PLD 300 has. There is no.
On the other hand, in the case of logic synthesis for general specific applications such as Patent Document 1 described above, if it is a PLD having a defect (failure) in part and is intended to be used for specific applications, There is no relationship between the failure location of the PLD and the configuration data that defines a logic circuit for a specific application. For this reason, when the failure location 301 in the PLD used for logic synthesis and the pattern 321 in the configuration data 320 overlap, the PLD having the defect cannot be used. The PLD 340 illustrated in FIG. 4 exemplifies such a case. As a result of the programmable resource (301) being included in the programmable resource to be used, the PLD 340 Even if it is intended for use, it cannot be used. In other words, in the case of logic synthesis for general specific applications such as Patent Document 1, whether or not a PLD having a defect can be used as a non-defective product limited to a specific application is determined as “a problem to be solved by the invention”. As described above in the column, it is not possible to quantitatively grasp the utilization rate of the PLD which is governed by the contingency of the combination of the PLD having the defect and the configuration data and partially includes a failure.
Next, attention is focused on FIG. 5 expressed in the same manner of expression as FIG. 5, the lattice-like matrix virtually represents the programmable resources or configuration data 123 (410, 420) included in the PLD (400, 430, 440) as in FIG. Also in FIG. 5, the failure positions (failure points) 401 of these PLDs are represented by “x” marks. In the example shown in FIG. 5,

configuration data

410 and 420 having different specific uses are generated for the PLD 400 including a partially failed resource (401), and the final product is further generated based on the configuration data. A case where

PLDs

430 and 440 for a specific application are generated is schematically shown.
That is, according to the PLD inspection and circuit synthesis system according to the present embodiment, the

configuration data

410 and 420 including the

patterns

411 and 421 in which the failure position 401 included in the PLD 400 is taken into account even when the specific application is different. Is generated. In this embodiment,

PLDs

430 and 440 for different specific applications can be generated based on the

configuration data

410 and 420.
Therefore, according to the present embodiment, even if a PLD partially includes a failure location, the configuration data itself generated for the PLD takes into account the failure location, so that there are multiple types with different specifications. The final product corresponding to the specific application can be obtained. That is, according to the PLD inspection and circuit synthesis system according to the present embodiment, it is possible to improve the utilization rate of the PLD partially including a failure and to quantitatively grasp the utilization rate.
(Modification of the second embodiment)
Here, a modification of the above-described second embodiment will be described with reference to FIG. FIG. 6 is a diagram for explaining the operation of the programmable logic device inspection and circuit synthesis system according to the modification of the second exemplary embodiment of the present invention, and the display is substantially the same as that shown in FIGS. 4 and 5 described above. Illustrated in the embodiment. In this modification, the system configuration is the same as that in FIG. 2, and the operation flow is also substantially the same as the flowchart shown in FIG. For this reason, the duplicate description in this modification is abbreviate | omitted. However, this modification differs in the points described below.
In other words, in this modification, the circuit synthesis unit 112 for specific applications does not target a single PLD as a PLD partially including a failure when performing circuit synthesis (step S7) in consideration of the failure position. Instead, circuit synthesis is performed for a plurality of PLDs. More specifically, in step S7, the circuit synthesizer 112 for specific applications reads the failure location data 121 related to a plurality of PLDs from the storage device 120, and performs a logical sum (AND) of the failure location data 121 related to the plurality of read PLDs. ). In the example illustrated in FIG. 6,

PLDs

500 and 510 represent two PLDs having different failure locations, and reference numeral 520 schematically represents a result of logical OR of information regarding the failure positions of the two PLDs (500 and 510). Expressly.
Then, the specific application circuit synthesis unit 112 refers to the specific logical position and the common failure position data (520) relating to the plurality of PLDs and the specific application netlist 122, thereby specifying the specific application. Configuration data 530 that defines the logic circuit to be generated. In other words, the configuration data 530 exemplifies a result of placement and wiring while avoiding individual failure points in the two

PLDs

500 and 510.
According to this modified example in which such processing is performed, when a PLD for a specific application is generated by taking a logical sum as described above, the failure position is individually different as a PLD partially including a failure. A plurality of possible defective devices can be targeted at once. That is, according to the present modification, it is possible to more reliably grasp the utilization rate of a PLD (defective device) partially including a failure, although it is limited to a specific application.
As another modification, instead of generating the failure location data 121 representing the failure location by the comprehensive inspection unit 111, a failure occurs from the list of all programmable resources included in the target PLD. A method of using a list from which information that can identify resources is deleted is assumed. Also by such a method, substantially the same effect as that of the above-described embodiment can be realized.
<Third Embodiment>
Next, a third embodiment based on the first and second embodiments described above will be described. In the following description, the characteristic part according to the present embodiment will be mainly described. At this time, the same reference numerals are assigned to the same configurations as those in the second embodiment described above, and the duplicate description is omitted.
The PLD inspection and circuit synthesis system (FIG. 2) according to the second embodiment described above is a system configuration that consistently performs all of the comprehensive inspection, circuit synthesis for specific applications, and inspection for specific applications. . On the other hand, in this embodiment, a case will be described in which comprehensive inspection, circuit synthesis for a specific application, and inspection for a specific application are performed individually.
FIG. 7 is a block diagram exemplifying configurations of a programmable logic device comprehensive inspection device, a special purpose circuit synthesis device, and a special purpose inspection device according to a third exemplary embodiment of the present invention. In this embodiment, the comprehensive inspection device 111A, the application specific circuit synthesis device 112A, the application specific inspection device 113A, and the storage device 120 are the PLD inspection and circuit synthesis system (FIG. 2) in the second embodiment. Corresponds to the set of subsystems that make up
That is, in FIG. 7, the comprehensive inspection apparatus 111A performs substantially the same operation as the comprehensive inspection unit 111 described above. The application specific circuit synthesis apparatus 112A performs substantially the same operation as the application specific circuit synthesis unit 112 described above. The application-specific inspection apparatus 113A performs substantially the same operation as the application-specific inspection unit 113 described above. That is, the comprehensive inspection apparatus 111A, the application specific circuit synthesis apparatus 112A, and the application specific inspection apparatus 113A substantially constitute the processing apparatus 110 in the second embodiment as a whole. In other words, referring to FIG. 3 in the second embodiment, the comprehensive inspection apparatus 111A performs the processing from step S1 to step S6 shown in FIG. The application specific circuit synthesis apparatus 112A performs the process of step S7 shown in FIG. Then, the application-specific inspection apparatus 113A performs the processing from step S8 to step S11 shown in FIG.
However, in this embodiment, these devices (111A, 112A, 113A) may be realized as individual subsystems as shown in FIG. 7, or any two devices are physically realized as one device. May be. The storage device 120 illustrated in FIG. 7 stores various data (121, 122, 123) similar to the storage device 120 illustrated in FIG.
In the present embodiment, the comprehensive inspection device 111A, the application specific circuit synthesis device 112A, and the application specific inspection device 113A include a CPU (Central Processing Unit) 1111, 1112, 1113, and a PLD tester unit and storage device 120. Hardware including a communication interface (both not shown) for performing the above communication. The CPU 1111 controls the overall operation of the comprehensive inspection apparatus 111A by executing the comprehensive inspection program 11. The CPU 1112 controls the overall operation of the circuit synthesis apparatus 112A for specific applications by executing the circuit synthesis program 12 for specific applications. The CPU 1113 controls the entire operation of the inspection apparatus for specific application 113A by executing the inspection program for specific application 13.
That is, in the present invention described by taking this embodiment as an example, the

computer program

11, 12, 13 is supplied to the

devices

111A, 112A, 113A, and then the computer program is transferred to the

devices

111A, 111A, 113A. This is achieved by reading out to the

CPUs

1111, 1112, and 1113 of the 112A and 113A and executing them. The computer program is supplied to the apparatus by, for example, an external apparatus, or a non-volatile storage device (1117, 1118, 1119) such as a computer-readable / writable temporary storage memory (1114, 1115, 1116) or a hard disk drive. ) Or the like. In such a case, the present invention can be considered to be configured by a code of the computer program or a storage medium in which the code is recorded.
As a specific example of adopting this embodiment, the PLD manufacturer side (PLD manufacturer itself, the manufacturer's service department, agency, technology trading company, etc.) and the PLD supply from the manufacturer side, A user configured as a desired PLD for a specific application is assumed.
That is, in such an application example, the manufacturer uses the comprehensive inspection apparatus 111A to select a PLD partially including a failure, and the failure position data 121 of the selected PLD has been described in the second embodiment. As shown in FIG. Then, the manufacturer distributes the PLD corresponding to the failure position data 121 to the user as a PLD that may be used as a PLD for a specific application, distinguishing it from a complete non-defective product.
On the other hand, the user now stores a desired application-specific netlist 122 generated in advance by a general method in the storage device 120. Then, the user uses the circuit synthesizer 112 </ b> A for specific application to configure the configuration data 123 that defines the logic circuit for the desired specific application based on the failure position data 121 and the desired specific application netlist 122. Is generated. In this example, the manufacturer can browse the desired specific-use netlist 122 and the generated specific-use configuration data 123 using the general security function of the storage device 120. It cannot be obtained. Then, the user manufactures a PLD in which the desired specific application logic circuit is configured by using the configuration data 123 using a general manufacturing apparatus (not shown). Thereafter, the user uses the application-specific inspection apparatus 113A to inspect the function of the desired application-specific PLD manufactured.
In the second embodiment described above, since a series of processes from comprehensive inspection to inspection for specific applications are performed collectively in the system shown in FIG. 2, such a series of processes is generally performed by the manufacturer. It is assumed that it will be done. In this case, in order to obtain the desired specific application PLD, the user must provide the manufacturer with the netlist 122 for the desired specific application in advance. Furthermore, it is expected that the generated application-specific configuration data 123 is stored on the manufacturer side.
On the other hand, according to the adoption example according to the present embodiment, the user does not need to provide the desired specific-use netlist 122 to the manufacturer. In other words, the user himself / herself uses the application-specific circuit synthesis device 112A or the like based on the PLD that may be used as the application-specific PLD provided by the manufacturer and the failure position data 121. Can produce the desired application specific PLD.
Therefore, according to the adoption example according to the present embodiment, in addition to the same effects as those of the second embodiment, the desired specific use netlist 122 that is a trade secret for the user, and It is possible to maintain confidentiality with the corresponding configuration data 123. And a user can obtain the product excellent in cost merit compared with the case where the said PLD for specific uses is obtained using PLD which is a perfect quality product, maintaining confidentiality.
In the third embodiment described above, for the convenience of explanation, as shown in FIG. 7, a configuration in which the comprehensive inspection device 111A and the storage device 120 are communicably connected is illustrated. However, the present invention described using the third embodiment as an example is not limited to such a configuration. That is, the failure position data 121 generated by the comprehensive inspection device 111A is provided to the administrator side of the storage device 120 (corresponding to the above-described user) via various computer-readable storage media offline. Good.
Moreover, the modification in 2nd Embodiment mentioned above can also be applied to 3rd Embodiment. In this case, the comprehensive inspection apparatus 111A takes a logical sum regarding a failure position (failure location) of each PLD for a plurality of PLDs that may be used as a PLD for a specific application. For this reason, for example, in the case of the above-mentioned adoption example, the manufacturer can provide the user with common fault location data regarding the PLDs even though the fault locations included in the individual PLDs to be provided differ in the individual PLDs. . In this case, since the user can use the common failure location data, the configuration data generated by the application specific circuit synthesis apparatus 112A is common to individual PLDs if the specifications of the desired application specific logic circuit are the same. To do. For this reason, it is also possible to facilitate the quality management by the user of the desired specific application PLD that is the final product for the user.
Note that each of the above-described embodiments and modifications thereof can also be applied to devices that cannot be rewritten (such as a fuse type or one-time type). For example, an antifuse-type PLD can identify the location of a failed resource in its interior by performing a nondestructive inspection while suppressing an applied voltage. Therefore, even for this type of PLD, according to the procedure according to each of the above-described embodiments and modifications thereof, the application is limited to one time, but the composition data of the logic circuit that avoids the failure portion is synthesized. And writing are feasible.
Thus, according to the present invention described as a specific example of each of the above-described embodiments and modifications thereof, it is possible to improve the utilization rate of a programmable logic device partially including a failure and quantitatively grasp the utilization rate. Possible provision of a circuit inspection device, a circuit information generation device, and the like is realized.
Note that a part or all of the above-described embodiment and its modifications can be described as the following supplementary notes. However, the present invention described by way of example with the above-described embodiment and its modifications is not limited to the following.
(Appendix 1)
In order to realize the logic circuit using the programmable logic device by avoiding the failed programmable resource based on the information representing the desired logic circuit and the information specifying the failed programmable resource inside the programmable logic device A circuit information generation method for a programmable logic device, wherein the circuit information is generated.
(Appendix 2)
Prior to the generation of the circuit information, the information for identifying the failed programmable resource is a failed programmable logic device for a failed programmable logic device that has failed in the inspection of the programmable resource of the programmable logic device. Obtain by examining the faulty programmable resources inside the device
The circuit information generation method for the programmable logic device according to appendix 1, wherein:
(Appendix 3)
The information identifying the programmable resource includes at least location information regarding a programmable resource that has failed within the failed programmable logic device.
The circuit information generation method for the programmable logic device according to appendix 2, wherein the circuit information is generated.
(Appendix 4)
The information identifying the failed programmable resource is the location of the failed programmable resource within each failed programmable logic device for a plurality of failed programmable logic devices that have failed the inspection. Obtained by taking the logical OR,
When generating circuit information for realizing the logic circuit, refer to information indicating the desired logic circuit and information specifying the failed programmable resource where the OR is taken. Generates common circuit information for the plurality of defective programmable logic devices.
The circuit information generation method for a programmable logic device according to any one of Supplementary Note 1 to Supplementary Note 3, wherein:
(Appendix 5)
Targeting a failed programmable logic device that has failed in the inspection of a programmable resource included in the programmable logic device, the failed programmable resource inside the failed programmable logic device is identified to identify the failed programmable resource. Generate information
A circuit inspection apparatus for a programmable logic device.
(Appendix 6)
The information identifying the programmable resource includes at least location information regarding a programmable resource that has failed within the failed programmable logic device.
The circuit inspection apparatus for a programmable logic device according to appendix 5, wherein:
(Appendix 7)
In order to realize the logic circuit using the programmable logic device by avoiding the failed programmable resource based on the information representing the desired logic circuit and the information specifying the failed programmable resource inside the programmable logic device Generate circuit information for
A circuit information generating device for a programmable logic device.
(Appendix 8)
Targeting the failed programmable logic device that has failed in the inspection of the programmable resource that the programmable logic device has, the failed programmable resource inside the failed programmable logic device is identified to identify the failed programmable resource. Inspection means for generating information;
Based on information representing a desired logic circuit and information identifying the failed programmable resource generated by the inspection means, the failed programmable resource is avoided, and the logic circuit is configured using the programmable logic device. Generating means for generating circuit information for realizing
A programmable logic device inspection and circuit information generation system.
(Appendix 9)
The inspection means, for a plurality of failed programmable logic devices that have failed in the inspection, by taking the logical sum of the locations of the failed programmable resources inside each failed programmable logic device Generating information identifying the failed programmable resource;
The generation means refers to information indicating a desired logic circuit and circuit information for realizing the logic circuit by referring to information specifying the failed programmable resource where the logical sum is taken. Common circuit information is generated for the plurality of defective programmable logic devices.
9. The programmable logic device inspection and circuit information generation system according to appendix 8.
(Appendix 10)
A computer program for controlling the operation of a circuit inspection apparatus for a programmable logic device, and for a failed programmable logic device that has failed in the inspection of a programmable resource of the programmable logic device by the computer program The computer implements a function of generating information for identifying the failed programmable resource by inspecting the failed programmable resource inside the failed programmable logic device.
A computer program characterized by the above.
(Appendix 11)
A computer program for controlling the operation of a circuit information generation device of a programmable logic device, the computer program,
In order to realize the logic circuit using the programmable logic device by avoiding the failed programmable resource based on the information representing the desired logic circuit and the information specifying the failed programmable resource inside the programmable logic device The computer to realize the function to generate circuit information
A computer program characterized by the above.
(Appendix 12)
Targeting a failed programmable logic device that has failed in the inspection of the programmable resource that the programmable logic device has, information that identifies a failed programmable resource inside the failed programmable logic device is stored, A computer-readable storage medium.
(Appendix 13)
The information identifying the programmable resource includes at least location information regarding a programmable resource that has failed within the failed programmable logic device.
The computer-readable storage medium according to Supplementary Note 12, wherein
The present invention has been described above using the above-described embodiment as an exemplary example. However, the present invention is not limited to the above-described embodiment. That is, the present invention can apply various modes that can be understood by those skilled in the art within the scope of the present invention.
This application claims the priority on the basis of Japanese application Japanese Patent Application No. 2010-260789 for which it applied on November 24, 2010, and takes in those the indications of all here.

DESCRIPTION OF SYMBOLS 11 Comprehensive inspection program 12 Application-specific circuit synthesis program 13 Application-specific inspection program 51 Circuit inspection apparatus 52 Application-specific circuit information generation apparatus 61 Information which identifies the faulty programmable resource 62 Design information of desired logic circuit 63 Circuit information DESCRIPTION OF SYMBOLS 110 Processing apparatus 111 Comprehensive test | inspection part 111A Comprehensive test | inspection apparatus 112 Application specific circuit synthesis | combination part 112A Application specific circuit synthesis | combination apparatus 113 Application specific test | inspection part 113A Application specific test | inspection apparatus 120 Storage device 121 Fault position data (fault position list )
122 Application

Specific Net List

123, 310, 320, 530 Application

Specific Configuration Data

300, 330, 340, 500, 510 Programmable Logic Device (PLD)
311, 321, 331, 342, 411, 421, 431, 442 Programmable resource pattern used inside

PLD

301, 401 Failed programmable resource 520 Common failure location data for

PLD

500 and 510 1111, 1112, 1113 CPU
1114, 1115, 1116

Memory

1117, 1118, 1119 Storage device

Claims

In order to realize the logic circuit using the programmable logic device by avoiding the failed programmable resource based on the information representing the desired logic circuit and the information specifying the failed programmable resource inside the programmable logic device A circuit information generation method for a programmable logic device, wherein the circuit information is generated.
Prior to the generation of the circuit information, the information for identifying the failed programmable resource is a failed programmable logic device for a failed programmable logic device that has failed in the inspection of the programmable resource of the programmable logic device. The circuit information generation method for a programmable logic device according to claim 1, wherein the circuit information is acquired by checking a failed programmable resource inside the device.
The method for generating circuit information of a programmable logic device according to claim 2, wherein the information for specifying the programmable resource includes at least position information regarding a programmable resource that has failed in the failed programmable logic device.
The information identifying the failed programmable resource is the location of the failed programmable resource within each failed programmable logic device for a plurality of failed programmable logic devices that have failed the inspection. Obtained by taking the logical OR,
When generating circuit information for realizing the logic circuit, refer to information indicating the desired logic circuit and information specifying the failed programmable resource where the OR is taken. 4. The circuit information generation method for a programmable logic device according to claim 1, wherein common circuit information is generated for the plurality of defective programmable logic devices.
Targeting the failed programmable logic device that has failed in the inspection of the programmable resource that the programmable logic device has, the failed programmable resource inside the failed programmable logic device is identified to identify the failed programmable resource. A circuit inspection apparatus for a programmable logic device, characterized by generating information.
In order to realize the logic circuit using the programmable logic device by avoiding the failed programmable resource based on the information representing the desired logic circuit and the information specifying the failed programmable resource inside the programmable logic device A circuit information generation device for a programmable logic device, characterized in that the circuit information is generated.
Targeting the failed programmable logic device that has failed in the inspection of the programmable resource that the programmable logic device has, the failed programmable resource inside the failed programmable logic device is identified to identify the failed programmable resource. Inspection means for generating information;
Based on information representing a desired logic circuit and information identifying the failed programmable resource generated by the inspection means, the failed programmable resource is avoided, and the logic circuit is configured using the programmable logic device. A programmable logic device inspection and circuit information generation system, comprising: generation means for generating circuit information to be realized.
A computer program for controlling the operation of a circuit inspection apparatus for a programmable logic device, and for a failed programmable logic device that has failed in the inspection of a programmable resource of the programmable logic device by the computer program A computer program for causing a computer to realize a function of generating information for identifying a failed programmable resource by inspecting the failed programmable resource in the failed programmable logic device.
A computer program for controlling the operation of a circuit information generating device for a programmable logic device, which is used to specify information representing a desired logic circuit and information for identifying a faulty programmable resource inside the programmable logic device. A computer program for causing a computer to realize a function of generating circuit information for realizing the logic circuit using the programmable logic device while avoiding the failed programmable resource.
Targeting a failed programmable logic device that has failed in the inspection of a programmable resource that the programmable logic device has, information that identifies a failed programmable resource inside the failed programmable logic device is stored, A computer-readable storage medium.