CN102841305A

CN102841305A - System and method for debugging FPGA (field programmable gate array) in real time

Info

Publication number: CN102841305A
Application number: CN2011101924412A
Authority: CN
Inventors: 朱旭; 杨龙; 张东晓
Original assignee: BEIJING UPTOPS DESIGN TECHNOLOGIES Inc
Current assignee: BEIJING UPTOPS DESIGN TECHNOLOGIES Inc
Priority date: 2011-07-11
Filing date: 2011-07-11
Publication date: 2012-12-26

Abstract

The invention discloses a system for debugging FPGA (field programmable gate array) in real time, comprising an SPI (serial peripheral interface) transceiving module, an SFR (special function register) decoding module, a data storing unit and a logic detection unit, wherein the SPI transceiving module is used for receiving external data to form a detection command and detection data and sending an internal detection result and internal storage data; the SFR decoding module is used for decoding a register command with special functions; the data storing unit is used for storing specified sampled data; and the logic detection unit is used for being connected with at least one group of logic units to be detected and carrying out real-time verification to obtain a verification result; and the modules and the units are sequentially connected for carrying out data communication. A real-time debugging method of the system comprises the following steps that: the SPI transceiving module receives data of a monitoring system, the data received by the SPI transceiving module is converted into a detection instruction or detection data by virtue of the SFR module, is stored by the data storing unit and then is sent to the logic detection unit, the logic detection unit judges the logic units to be detected, and judgement data and result are stored and then are transmitted by the SPI transceiving module. The system disclosed by the invention takes an SPI bus protocol as a protocol used for realizing data interaction between a basic debugging device and equipment, and high-speed product debugging and verifying design and dynamic check debugging are realized.

Description

A kind of system and method to the FPGA real-time debug

Technical field

Invention relates to the technical field of FPGA design being carried out real-time debug and dynamic authentication, specifically belong to a kind of through SPI (Serial Peripheral Interface) interface to the system and method for FPGA real-time debug purpose with the realization design verification.

Background technology

FPGA (Field-Programmable Gate Array), i.e. field programmable gate array, it is the product that on the basis of programming devices such as PAL, GAL, CPLD, further develops.It occurs as a kind of semi-custom circuit in special IC (ASIC) field, has both solved the deficiency of custom circuit, has overcome the limited shortcoming of original programming device gate circuit number again.

FPGA has adopted the notion of logical cell array LCA (Logic Cell Array), and inside comprises configurable logic blocks CLB (Configurable Logic Block), output load module IOB (Input Output Block) and three parts of interconnector (Interconnect).The basic characteristics of FPGA: 1) adopt FPGA ASIC design circuit (special IC), the user need not throw sheet production, the chip that just can obtain share; 2) FPGA can do the middle coupons of other full customization or semi-custom ASIC circuit; 3) there are abundant trigger and I/O pin in FPGA inside; 4) FPGA is one of device that the design cycle is the shortest in the ASIC circuit, development cost are minimum, risk is minimum; 5) FPGA adopts high speed CHMOS technology, and is low in energy consumption, can be compatible with CMOS, Transistor-Transistor Logic level.Therefore, fpga chip is one of optimal selection of short run system raising level of integrated system, reliability.

FPGA is provided with its duty by the program that leaves in the ram in slice, need the RAM in the sheet be programmed during work.The user can adopt the different programming mode according to different configuration modes.When powering up, fpga chip reads in data among the EPROM among the RAM that programmes in the sheet, and after configuration was accomplished, FPGA got into duty.After the power down, FPGA reverts to white, and the internal logic relation disappears, and therefore, FPGA can use repeatedly.The programming of FPGA need not be special-purpose the FPGA programmable device, need only use general EPROM, PROM programmable device to get final product.When needs are revised the FPGA function, only need change a slice EPROM and get final product.Like this, with a slice FPGA, the different programming data can produce the different circuits function.Therefore, the use of FPGA is very flexible.

FPGA has the various configurations pattern: parallel holotype adds the mode of a slice EPROM for a slice FPGA; Master slave mode can be supported a slice PROM programming multiple FPGA; Serial mode can adopt serial PROM programming FPGA; The peripheral hardware pattern can be programmed by microprocessor the peripheral hardware of FPGA as microprocessor to it.

Before the FPGA system design is accomplished, arranged: design phase and debugging, testing stage 2 different stages.The main task of design phase is input, emulation and realization; The main task of debugging, testing stage is the check design, proofreaies and correct the mistake of finding.

Because modern science and technology has higher requirement to system reliability, and that the FPGA technology is used in electronic system is very extensive, so the Easy Test property of FPGA just becomes very important.The FPGA internal signal that obtains is very limited, and the particularly existence of FPGA encapsulation and printed circuit board (PCB) (PCB) electrical noise makes debugging, check become a most difficult flow process in the total system design.On the other hand; Current nearly all bus as high-speed chips such as CPU, DSP, ASIC; Except the high speed parallel bus interface was provided, the direction to HSSI High-Speed Serial Interface developed just rapidly, and these technical progresses force the designer that the overwhelming majority time is placed in debugging, the check design.

Comparatively common debugging, the method for inspection of FPGA has: use the external logic analyser, in this method, useful internal signal is routed to FPGA not to be had to be connected on the logic analyser then on the stitch of use.This method provides very dark internal memory, and suitable debugging is broken down and the actual reason that causes this fault problem of wide apart in time; The designer who carries out post analysis for needs collection mass data is also very necessary.In addition, it can also associate other activity times in inner FPGA signal and the Circuits System.External logic analyser method adopts considerably less logical resource, does not use the FPGA memory source.It has discharged these resources, realizes required function.Its contradiction is, like 1 pair 1 connection and measurement: the corresponding internal signal node of each FPGA debugging pin; The stationary inner signal node will change new measured node, must design again, not only wastes time and energy but also can change original sequential of signal thus; Each change measured signal and all will stop and connect instrument again, the pin positions of definition signal and title again, this is very loaded down with trivial details work.And the pin of FPGA is valuable resource, and the pin that is exclusively used in debugging is considerably less usually, generally is several to about 32, and this port becomes the critical piping that route output internal signal is measured.Be exclusively used in each pin of debugging, only corresponding inner single measured signal.If will increase or change tested signal, need to change design, synthesize again, rearrange the position of pin, rewiring not only can consume great amount of time, also may change original sequential of circuit.

Another kind of debugging, the method for inspection are to use embedded logic analyzer; Common main FPGA manufacturer all provides the embedded logic analyzer kernel, like SignalTap

II of Altera and the ChipScopeTM ILA of Xilinx.These modules are inserted in the FPGA design, provide simultaneously to trigger function and memory function.The fpga logic resource is used for realizing trigger circuit, and the FPGA memory module then is used for realizing memory function.JTAG is used for disposing core operation, is used in addition the data transmission that captures to PC, so that check.Because embedded logic analyzer uses inner FPGA resource, they can use with the large-scale FPGA that can absorb the core expense better usually.In the ordinary course of things, the resource that takies of core had better not be higher than 5% of available FPGA resource.Yet only rely on JTAG to come the data transmission that captures to PC, can not satisfy of the requirement of present complication system, in a plurality of FPGA system, be subject to the JTAG agreement, also can not realize the configuration and the debugging of full duplex for debugging speed.

Summary of the invention

The present invention is directed to the defective in existing FPGA debugging, the checkout procedure, propose a kind of system and method the FPGA real-time debug.

The technical scheme that realizes the foregoing invention purpose does, a kind of system to the FPGA real-time debug, and this system comprises:

The SPI transceiver module forms sense command and detects data thereby be used to receive external data, sends inner testing result and storage inside data;

The SFR decoding module is used for the register command of specific function is deciphered;

Data storage cell is used for preserving the appointment sampled data;

The logic detection unit is used to connect at least one group logical block to be measured and carry out real-time verification, obtains check results;

Above-mentioned module, unit connect successively and carry out data communication.

Said data storage cell comprises order register, data register and storage unit.

The logical block to be measured that is connected with the logic detection unit can be directly and storage unit carry out data communication.

The signal that the SPI transceiver module receives is that SDI is the inputs of main equipment data, the output of slave unit data; SCLK is by the main equipment clocking; CS is by the enable signal of main equipment control slave unit; The signal that sends is SDO, the output of main equipment data, the input of slave unit data.

The invention still further relates to a kind of method to the FPGA real-time debug; Said method comprising the steps of: the SPI transceiver module receives the supervisory system data; Through the SFR module SPI is accepted data conversion for detecting instruction or detection data and through being sent to the logic detection unit after the data storage cell storage, through the logic detection unit judgement of logical block to be measured being stored the back with decision data, result and send through the SPI transceiver module.

System of the present invention is the agreement of basic debugging apparatus and equipment interaction data with SPI (Serial Peripheral Interface) bus protocol, thereby has realized debugging checking product design at a high speed, dynamic check debugging.

Description of drawings

Fig. 1 is the system architecture diagram of FPGA real-time debug of the present invention;

Fig. 2 is a FPGA real-time debug schematic flow sheet of the present invention.

Embodiment

For ease of the understanding of technical scheme of the present invention, introduce below in conjunction with concrete embodiment.Like Fig. 1 is the system architecture diagram of FPGA real-time debug; As shown in the figure; This system comprises the SPI transceiver module, forms sense command and detects data thereby be used to receive external data, sends inner testing result and storage inside data; The signal of its reception is that SDI is the inputs of main equipment data, the output of slave unit data; SCLK is by the main equipment clocking; CS is by the enable signal of main equipment control slave unit; The signal that sends is SDO, the output of main equipment data, the input of slave unit data; The SFR decoding module is used for the register command of specific function is deciphered; Data storage cell is used for preserving and specifies sampled data, and in the present embodiment, this unit is made up of command register, data register, storage element; The logic detection unit is used to connect at least one group logical block to be measured and carry out real-time verification, obtains check results; Above-mentioned module, unit connect successively and carry out data communication.

Fig. 2 is a FPGA real-time debug schematic flow sheet; Like figure; The SPI transceiver module receives the outside monitor data that sends through SPI; Through the SFR module with SPI accept data conversion for detect instruction or detect data and order register through data storage cell or data register storage after be sent to the logic detection unit, through the RAM of logic detection unit to data sampling, debugging, to after the judgement of logical block to be measured with decision data, result's storage and send through the SPI transceiver module once more.

The above; Be preferable case study on implementation of the present invention; Be not that the present invention is done any restriction, every technical spirit changes any simple modification, change and the equivalent structure that above embodiment did according to the present invention, all still belongs in the protection domain of technical scheme of the present invention.

Claims

1. the system to the FPGA real-time debug is characterized in that, this system comprises:

Data storage cell is used for preserving the appointment sampled data;

2. the system to the FPGA real-time debug according to claim 1 is characterized in that data storage cell comprises order register, data register and storage unit.

3. the system to the FPGA real-time debug according to claim 2 is characterized in that, the logical block to be measured that is connected with the logic detection unit can be directly and storage unit carry out data communication.

4. the system to the FPGA real-time debug according to claim 1 is characterized in that, the signal that the SPI transceiver module receives is that SDI is the inputs of main equipment data, the output of slave unit data; SCLK is by the main equipment clocking; CS is by the enable signal of main equipment control slave unit; The signal that sends is SDO, the output of main equipment data, the input of slave unit data.

5. method to the FPGA real-time debug; It is characterized in that; Said method comprising the steps of: the SPI transceiver module receives the supervisory system data; Through the SFR module SPI is accepted data conversion for detecting instruction or detection data and through being sent to the logic detection unit after the data storage cell storage, through the logic detection unit judgement of logical block to be measured being stored the back with decision data, result and send through the SPI transceiver module.