CN102103186A - Debug method of FPGA and equipment thereof - Google Patents

Abstract

The invention discloses a debug method of a field-programmable gate array (FPGA) and equipment thereof, wherein the method comprise the steps of: using a complex programmable logic device (CPLD) to store FPGA configuration data in a flash memory before the starting of a central processing unit (CPU); and using the CPLD to establish an effective channel between the FPGA and the flash memory to ensure that the FPGA can obtain the configuration data for debug through the effective channel. According to the above technical proposal, the FPGA can fast obtain the configuration data, required by the debug thereof, through the CPLD before the starting of the CPU so as to start the debug at a faster speed without waiting for the completeness of the CPU starting.

Description

A kind of FPGA adjustment method and equipment thereof

Technical field

The present invention is broadly directed to the debugging field of hardware, more specifically, relates to a kind of FPGA adjustment method and equipment thereof.

Background technology

Generally speaking, in hardware development, the developer starts the back at CPU and uses this CPU burning flash memory (flash).Fig. 4 shows the synoptic diagram of this adjustment method, as shown in Figure 4, after CPU410 starts, flash memory 420 is fired, and then the configuration data in the flash memory 420 is written into field programmable gate array (FPGA) 430, thereby can debugs FPGA.Often need long time yet CPU is started, thereby have influence on the debugging progress of system.

Therefore need a kind of method of accelerating system debug.

Summary of the invention

Embodiments of the present invention disclose a kind of FPGA adjustment method and equipment thereof, to address the above problem.

According to an aspect of the present invention, proposed a kind of on-site programmable gate array FPGA adjustment method, having comprised: before CPU starts, the FPGA configuration data has been stored in the flash memory by complex programmable logic device (CPLD); Described CPLD sets up the effective passage between FPGA and the described flash memory, is used for debugging so that described FPGA can obtain described configuration data by described effective passage.

According to a further aspect in the invention, proposed the system of a kind of FPGA of being used for debugging, having comprised: flash memory is used to store the configuration data of FPGA; CPLD is used to set up the effective passage between FPGA and the described flash memory, is used for debugging so that described FPGA can obtain described configuration data by described effective passage.

By above-mentioned technical scheme, before CPU started, FPGA obtained the required configuration data of its debugging soon by CPLD, thereby can begin debugging quickly, and needn't the waiting for CPU startup finish.

Description of drawings

In conjunction with the accompanying drawings embodiments of the present invention are described in detail, can understand the present invention better, wherein:

Fig. 1 shows the block scheme according to the FPGA debug system of embodiment of the present invention;

Fig. 2 shows the process flow diagram according to the FPGA adjustment method of embodiment of the present invention;

Fig. 3 shows according to embodiment of the present invention, and JTAG is to the realization synoptic diagram of parallel flash.

Fig. 4 shows the process flow diagram according to the FPGA adjustment method of prior art.

Embodiment

To a preferred embodiment of the present invention will be described in detail, having omitted in the description process is unnecessary details and function for the present invention with reference to the accompanying drawings, obscures to prevent that the understanding of the present invention from causing.

Fig. 1 shows a kind of system that FPGA is debugged of being used for, and comprises flash memory 110, is used to store the configuration data of FPGA 140; CPLD (CPLD) 120 is used for setting up the effective passage between FPGA 140 and the flash memory 110 before CPU 130 starts, so that FPGA 140 can obtain the used configuration data of debugging by this effective passage.

Wherein, CPLD 120 inner parsings and buffer memory FPGA configuration data.

CPLD 120 also can have parallel or SPI flash controller function, is used for flash memory 110 is connected and controls.

This debug system also can comprise computing machine 150 (as, PC (PC)), is used for by being loaded in CPLD120 under the configuration data of JTAG (JTAG) cable with FPGA 140.In addition, PC 150 also is used to dispose CPLD 120.

Though above with the formal description of the functional module of separating the message processing apparatus of the embodiment of the invention, but each assembly shown in Fig. 1 can realize with a plurality of devices in actual applications, and a plurality of assemblies that illustrate also can be integrated in chip piece or the equipment in actual applications.This message processing apparatus also can comprise any unit and the device that is used for other purpose.

Be described below in conjunction with the process flow diagram of Fig. 2 workflow FPGA debug system shown in Figure 1.

In step 210, before the CPU 130 of veneer started, PC 150 downloaded CPLD configuration data and FPGA configuration data to CPLD 120 by the JTAG cable.

In step 220, CPLD 120 is configured according to the CPLD configuration data, and the valid data of inner parsing and buffer memory JTAG chain, promptly is written into the valid data of JTAG chain, to extract the configuration data of FPGA 140.

In step 230, after being written into successfully, the parallel or SPI flash memory control function in the CPLD 120 writes flash memory 110 with the configuration data of FPGA 140.

Fig. 3 shows the realization synoptic diagram of JTAG to parallel flash memory 110.As shown in Figure 3, the JTAG chain that 121 couples of PC of state machine among the CPLD 120 150 send is resolved, the FPGA configuration data that parses is deposited with in the data register 122, and under the control of control signal state machine 124, this FPGA configuration data (FLASH_DATA) is write in the indicated flash memory 110 of address date (FLASH_ADDR) in the address register 123.In addition, FLASH_WE, FLASH_OE and FLASH_CE are the control signals to flash memory 110, and its concrete function is conventionally known to one of skill in the art.

In step 240, FPGA 140 reads FPGA configuration data in the flash memory 110 by CPLD.

At this moment, CPLD 120 disposes FPGA 140 with subordinate serial or the parallel mode of subordinate.

In step 250, FPGA 140 debugs based on this configuration data.

Can be by the parallel of CPLD 120 or Serial Peripheral Interface (SPI) (SPI) flash controller function visit flash memory 110.Between has bridge joint to come data speed is carried out self-adaptation.

After CPLD 120 was written into successfully, FPGA 140 obtained configuration data via CPLD 120 from flash memory 110, finished and need not waiting for CPU 130 startups, and this has greatly quickened the process of system debug.

After CPU 130 starts, also use this method to visit flash memory 110 with the repeatedly startup of support CPU130 and subordinate serial or the parallel configuration of subordinate of FPGA 140.The configuration speed of this method depends on the characteristic of CPLD 120 and flash memory 110.Its detailed calculated is as follows:

${\mathrm{CCLK}}_{\max }={\left(\frac{t_{\mathrm{co}}+t_{\mathrm{su}}+t_{\mathrm{flash}}}{16}\right)}^{-1}$

Wherein, t _CoThe clock that is the register of CPLD 120 arrives the time of output, t _SuBe the register Time Created of CPLD120, t _FlashIt is the access time of flash memory 110.The typical rate of standard paralleling flash memory equipment be 60ns to 120ns, t _CoAnd t _SuCan use producer's instrument of FPGA 140 to obtain.

In the present embodiment, can realize this solution by Lattice MachXO equipment.It is the Virtex-6 of Xilinx company that flash memory 110 adopts S29GL512P, the FPGA 140 of Spansion company.Before CPU 130 starts, use the Isp VM System instrument among the PC to download two set of configuration data, one group of configuration that is used for CPLD MachXO, another group is the bit file that is used for flash memory 110 configurations.Before CPU 130 started, all other subsystems began debugging by the configuration data that obtains from flash memory 110.

In embodiments of the present invention, before CPU 130 started, FPGA 140 obtained the required configuration data of its debugging soon by CPLD120, thereby can begin debugging quickly, and needn't waiting for CPU 130 startups finish.

Those skilled in the art should be easy to recognize, can realize the different step of said method by programmed computer.At this, some embodiments comprise equally machine readable or computer-readable program storage device (as, digital data storage medium) and the coding machine can carry out or the executable programmed instruction of computing machine, wherein, some or all steps of said method are carried out in this instruction.For example, program storage device can be number storage, magnetic storage medium (as Disk and tape), hardware or the readable digital data storage medium of light.Embodiment comprises the programmed computer of the described step of carrying out said method equally.

Description and accompanying drawing only illustrate principle of the present invention.Therefore should be appreciated that those skilled in the art can advise different structures,, embodied principle of the present invention and be included within its spirit and scope though these different structures are not clearly described herein or illustrated.In addition, all examples of herein mentioning mainly only are used for teaching purpose clearly helping the design of reader understanding's principle of the present invention and promotion this area that the inventor was contributed, and should be interpreted as not being the restriction to these specific examples of mentioning and condition.In addition, all statement and specific examples thereof of mentioning principle of the present invention, aspect and embodiment comprise its equivalent interior herein.

Top description only is used to realize embodiments of the present invention; it should be appreciated by those skilled in the art; the any modification or partial replacement that is not departing from the scope of the present invention; all should belong to claim of the present invention and come restricted portion; therefore, protection scope of the present invention should be as the criterion with the protection domain of claims.

Claims (6)

1. on-site programmable gate array FPGA adjustment method comprises:

Before CPU starts, the FPGA configuration data is stored in the flash memory by complex programmable logic device (CPLD);

Described CPLD sets up the effective passage between FPGA and the described flash memory, is used for debugging so that described FPGA can obtain described configuration data by described effective passage.

2. method according to claim 1, wherein, store the FPGA configuration data in the flash memory into by CPLD and to comprise:

By JTAG JTAG cable CPLD configuration data and described FPGA configuration data are downloaded to described CPLD;

Described CPLD is configured according to described CPLD configuration data, and inner the parsing and the described FPGA configuration data of buffer memory; And

Described FPGA configuration data is write described flash memory.

3. method according to claim 2 also comprises:

Described FPGA reads described FPGA configuration data in the flash memory by CPLD;

Described CPLD disposes described FPGA with subordinate serial or the parallel mode of subordinate;

Described FPGA debugs according to the configuration data that is obtained.

4. one kind is used for the system that FPGA debugs, and comprising:

Flash memory is used to store the configuration data of FPGA;

CPLD is used to set up the effective passage between FPGA and the described flash memory, is used for debugging so that described FPGA can obtain described configuration data by described effective passage.

5. system according to claim 4 also comprises:

Computing machine is used for will being loaded in described CPLD under the FPGA configuration data by the JTAG cable;

Described CPLD also is used for being configured according to described CPLD configuration data, the inner parsing and the described FPGA configuration data of buffer memory, and described FPGA configuration data is write described flash memory.

6. system according to claim 4, wherein, described CPLD also comprises parallel or SPI flash controller function, is used for flash memory is connected and controls.

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