CN110968539A - FPGA pin expansion method for multi-channel flash memory device - Google Patents
FPGA pin expansion method for multi-channel flash memory device Download PDFInfo
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- CN110968539A CN110968539A CN201811136982.1A CN201811136982A CN110968539A CN 110968539 A CN110968539 A CN 110968539A CN 201811136982 A CN201811136982 A CN 201811136982A CN 110968539 A CN110968539 A CN 110968539A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/387—Information transfer, e.g. on bus using universal interface adapter for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
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Abstract
The application discloses a method for expanding FPGA (field programmable gate array) pins, which is used for a multi-channel flash memory device and is directly connected with each memory chip by adding an external CPLD (complex programmable logic device); the FPGA is connected with the CPLD through a CPLD interface, the CPLD comprises chip selection interfaces connected with chip selection pins of each flash memory chip, and sends chip selection signals to each flash memory chip; the flash memory chip further comprises a state interface which is connected with the state pins of the flash memory chips and receives the state signals sent from the flash memory chips. Therefore, only a small number of pins are occupied, the FPGA can be connected with a plurality of flash memory chips without quantity limitation and exchange data, so that each channel can be mounted with as many flash memory chips as possible, and the storage capacity of the multi-channel flash memory device can be greatly increased.
Description
Technical Field
The application relates to the technical field of computers and data storage, in particular to an FPGA pin expansion method for a multi-channel flash memory device.
Background
An FPGA (Field-Programmable Gate Array) is a high-density Programmable Logic Device, and is used to implement basic Logic functions, interconnection between chips, signal processing, and embedded processing, and is a product of further development on the basis of Programmable devices such as PAL (Programmable Array Logic), GAL (general Array Logic), CPLD (complex Programmable Logic Device), and the like. The FPGA chip mainly includes three parts, i.e., an IOE (input output unit), an LAB (logic array block, called as a configurable logic block CLB for Xilinx), and an Interconnect (internal connection line), where the IOE is connected to the outside through a series of pins to exchange data. The pin of FPGA mainly includes: user I/O (User I/O), configuration pins, power supplies, clocks, and application specific pins, among others.
With the development of computers and data storage technologies, flash memory devices have been increasingly used for data storage. Compared with the traditional mechanical hard disk for storing data, the flash memory device has the advantages of higher reading and writing speed, higher shock resistance and falling resistance, lower power consumption, no noise during working, larger working temperature range and lighter and thinner appearance than the traditional mechanical hard disk.
Inside the large-capacity flash memory device, a control circuit is formed by a CPU and an FPGA chip through the design of an FPGA embedded system and is responsible for flash memory array control logic, data transmission control and the like. An FPGA typically includes 4 channels (channel 0, channel 1, channel 2, channel 3), each of which mounts a large number of flash chips. The channel is usually an 8-bit (8-bit) bus (bus). When the Flash Memory device performs read/write operations on internal Flash Memory chips, first, a Flash Memory Controller (Flash Memory Controller) of the channel sends a Chip Enable Signal (Chip Enable Signal), usually a low level Signal, to the Flash Memory Chip select pin of each Flash Memory Chip connected in the channel through an FPGA Chip select Signal pin of an FPGA, so as to select the Flash Memory Chip to be subjected to data read/write, and each Flash Memory Chip must send a Status Signal (Status Signal) to another FPGA Status Signal pin of the FPGA through another Flash Memory Status pin to feed back the working Status of the Flash Memory Chip. In other words, in each channel, each flash memory chip must connect and occupy at least two pins of the FPGA for receiving chip select signals and sending status signals.
It is considered that the capacity and the number of mounted flash chips in one flash memory device determine the capacity of the flash memory device. Usually, a plurality of flash memory chips are mounted in one channel, and if N flash memory chips are mounted, 2N pins are allocated to the FPGA to connect the memory chips, and this is only used for transmitting chip select signals and status signals. Considering that the pin resources of an FPGA are limited, and a large number of pins are wasted in transmitting only chip select signals and status signals, the number of memory chips that can be mounted in each channel is also limited. This is very disadvantageous for increasing the storage capacity of the flash memory device.
Accordingly, the prior art is yet to be improved and developed.
Disclosure of Invention
In view of the foregoing defects of the prior art, an object of the present application is to provide an FPGA pin expansion method for a multi-channel flash memory device, a flash memory chip management method in the multi-channel flash memory device, and a multi-channel flash memory system, so that the FPGA can mount as many flash memory chips as possible, thereby increasing the storage capacity of the multi-channel flash memory device.
The technical scheme of the application is as follows:
the application discloses an FPGA pin expansion method which is used for a multi-channel flash memory device, wherein the FPGA is connected with a CPLD through a CPLD interface; the CPLD comprises a chip selection interface and a state interface, wherein the chip selection interface is connected with a chip selection pin of each flash memory chip and sends a chip selection signal to each flash memory chip; the status interface is connected with the status pins of the flash memory chips and receives status signals sent by the flash memory chips.
Preferably, the CPLD interface includes a chip select frame pin and a chip select data pin for transmitting a chip select signal, and a status frame pin and a status data pin for accepting a status signal.
The chip selection frame pin outputs high level in one or more clock cycle ranges to show that the data in the one or more clock cycle ranges are effective, and the CPLD judges the data to be effective after receiving the high level output and performs serial conversion and processing.
The state data pin transmits the states of the N chips in sequence by N clock cycles according to the number of the chips on the transmission channel being N (N is a natural number), and the state data pin circulates once every N clock cycles; the status frame pin outputs a high level only during the clock cycle that conveys the first chip status, and the others are low to indicate the starting position.
In the digital logic circuit, the high level indicates 1, and the low level indicates 0, and in general, the low level is defined to be 0 to 0.25V, and the high level is defined to be 3.5 to 5V.
More preferably, the CPLD interface further includes a CPLD interface logic module, which is used for respectively encoding and decoding the chip select signal and the state signal.
More preferably, the CPLD interface logic module includes a chip select coding module, which is disposed inside the FPGA and is configured to code a chip select number of the valid flash memory into serial data, and send the serial data to a chip select data pin of the CPLD interface; and generating a chip selection frame signal, and sending the chip selection frame signal to a chip selection frame pin of the CPLD interface, wherein the chip selection frame signal is used for identifying the validity of the serial data.
More preferably, the CPLD interface logic module further includes a chip select decoding module, which is disposed inside the CPLD and is configured to decode the serial data signal into a parallel chip select number, and send the parallel chip select number to the chip select pin of the flash memory chip.
Preferably, the CPLD interface logic module includes a state encoding module, which is disposed inside the CPLD and is configured to sequentially send the state signals of the state pins of each flash memory chip to the state data pins; generating a state frame signal and sending the state frame signal to the state frame pin; the status frame signal is used for marking the position of the first flash memory chip in the status signal.
More preferably, the CPLD interface logic module further includes a state decoding module, disposed inside the FPGA, for decoding and recovering the state signal of each flash memory chip according to the position of the first flash memory chip indicated by the state frame signal after reading the state frame pin and the state data pin.
The application also discloses a flash memory chip management method in the multi-channel flash memory device, and the FPGA pin expansion method is adopted.
The application also discloses multichannel flash memory system, including that the FPGA chip passes through the CPLD chip and connects a plurality of flash memory chips, wherein: the FPGA chip is connected with the CPLD chip through a CPLD interface; the CPLD chip comprises a chip selection interface and a state interface, wherein the chip selection interface is connected with a chip selection pin of each flash memory chip and is used for sending a chip selection signal to each flash memory chip; the state interface is connected with the state pins of the flash memory chips and used for receiving the state signals sent by the flash memory chips.
The invention has the advantages that: the application discloses a method for expanding FPGA (field programmable gate array) pins, which is used for a multi-channel flash memory device and is directly connected with each memory chip by adding an external CPLD (complex programmable logic device); the FPGA sends chip selection signals including a chip selection frame signal and a chip selection data signal to the CPLD through two pins, and receives state signals including a state frame signal and a state data signal from the CPLD through the other two pins, so that the FPGA can be connected with a plurality of flash memory chips and exchange data without quantity limitation only by occupying 4 pins, each channel can be mounted with as many flash memory chips as possible, and the storage capacity of the multi-channel flash memory device can be greatly increased.
Drawings
Fig. 1 is a schematic diagram of a connection structure of the FPGA, the CPLD and the flash memory chips according to the present application.
In the figure, 1, an FPGA chip, 2, a CPLD chip, 3, a flash memory chip, 10, a channel, 11, a chip selection signal encoder, 21, a chip selection signal decoder, 12, a state signal decoder, 22 and a state signal encoder are arranged.
Detailed Description
The present application provides an FPGA pin expansion method, and in order to make the purpose, technical scheme, and effect of the present application clearer and clearer, the present application is further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
The method for expanding the FPGA pin is applied to a multi-channel flash memory device, a preferred embodiment is as shown in FIG. 1, wherein 4 channels 10 are preferably arranged in one FPGA chip 1, each channel 10 is connected and sends a chip selection signal to a chip selection signal encoder 11 on the FPGA chip 1 through a flash memory controller, and the chip selection signal encoder 11 encodes the chip selection signal and sends the chip selection signal to a chip selection signal decoder 21 on one CPLD chip 2 through a CPLD interface connection to decode the chip selection signal. The chip selection signal decoder 21 is further connected to the chip selection pins of the flash memory chips 3 through the chip selection interface, and sends the decoded chip selection signals to the flash memory chips 3 to select the flash memory chips to be activated. Meanwhile, each flash memory chip 3 also sends a status signal back to the status signal encoder 22 on the CPLD chip 2 through a status pin to feed back the operating status thereof. The state signal encoder 22 transmits the state signal to the state signal decoder 12 on the connected FPGA chip 1 through the CPLD interface, and after decoding and restoring, the state signal is connected to the flash memory controller of each channel 10 to feed back the working state of each flash memory chip. For example, there are 16 chips in each channel 10, the status data pin passes the status of the 16 chips in sequence with 16 clock cycles, once every 16 clock cycles. In the clock period for transmitting the first chip state, the state frame pin outputs high level to indicate the initial position, and the others are low level.
The chip selection signal comprises a chip selection frame signal and a chip selection data signal, the state signal also comprises a state frame signal and a state data signal, correspondingly, the CPLD interface comprises a chip selection frame pin and a chip selection data pin which are respectively used for sending the chip selection frame signal and the chip selection data signal; the CPLD interface also comprises a state frame pin and a state data pin which are respectively used for receiving the state frame signal and the state data signal. The chip selection data pin transmits parallel chip selection numbers in a serial mode, for example, the chip selection number with the number of 15, the chip selection data pin is serialized into binary number 01111, and the chip selection data pin is transmitted according to bits in 5 clock cycles; the chip selection frame pin outputs high level in the 5 clock cycles, which indicates that the data of the 5 clock cycles are effective, and the subsequent CPLD receives the effective data signal and then carries out serial conversion and processing on the effective data.
The chip selection signal encoder 11, the chip selection signal decoder 21, the state signal decoder 12, and the state signal encoder 22 connected to the CPLD interface all belong to logic modules, and are configured to encode and decode the chip selection signal and the state signal, respectively. It should be noted that the CPLD interface logic module is not required. In theory, it is only necessary to connect the CPLD and the FPGA and transmit data to each other.
The chip select signal encoder 11 is a chip select encoding module, and is configured to encode a chip select number of the effective flash memory into serial data, i.e., chip select data, so as to conveniently send the serial data to the chip select data pin. And simultaneously, generating a chip selection frame signal and sending the chip selection frame signal to a chip selection frame pin of the CPLD interface, wherein the chip selection frame signal is used for identifying the validity of the serial data. The chip selection frame signal cooperates with the chip selection data signal to form a complete chip selection signal for selecting the flash memory chip 3 to be operated.
Correspondingly, the CPLD interface logic module further includes a chip select signal decoder 21, which is a chip select decoding module, disposed inside the CPLD chip 2, and configured to decode the serial data signal into a parallel chip select number, and send the parallel chip select number to the chip select pin of the flash memory chip 3.
Similar to the chip select signal, for the status signal, the CPLD interface logic module also sets a status signal encoder 22, that is, a status encoding module, which is disposed inside the CPLD chip 2 and is used for sequentially sending the status signal of the status pin of each flash memory chip 3 to the status data pin; generating a state frame signal and sending the state frame signal to the state frame pin; the status frame signal is used for marking the position of the first flash memory chip in the status signal.
Correspondingly, the CPLD interface logic module further includes a status signal decoder 12, which belongs to a status decoding module, is disposed inside the FPGA chip 1, and decodes and restores the status signal sent by each flash memory chip 3 according to the position of the first flash memory chip indicated by the status frame signal after reading the data information sent by the status frame pin and the status data pin.
On the basis of the FPGA pin expansion method disclosed by the application, a flash memory chip management method in a multi-channel flash memory device can be formed, namely the FPGA pin expansion method disclosed by the application is adopted.
The application also discloses multichannel flash memory system, including FPGA chip 1 passes through CPLD chip 2 and connects a plurality of flash memory chips 3, wherein: the FPGA chip 1 is connected with the CPLD chip 2 through a CPLD interface; the CPLD chip 2 comprises a chip selection interface and a state interface, and the chip selection interface is connected with the chip selection pins of the flash memory chips 3 and is used for sending chip selection signals to the flash memory chips 3; the status interface is connected to the status pin of each flash memory chip 3, and is configured to receive the status signal sent from each flash memory chip.
The method for expanding the FPGA pin is used for a multi-channel flash memory device, and is directly connected with each memory chip 3 by adding an external CPLD chip 2; the FPGA chip 1 sends chip selection signals including a chip selection frame signal and a chip selection data signal to the CPLD chip 2 through two chip selection signal pins, and receives state signals including a state frame signal and a state data signal from the CPLD chip 2 through the other two state signal pins, so that the FPGA can be connected with a plurality of flash memory chips 3 without quantity limitation and exchange data, each channel can be provided with as many flash memory chips 3 as possible, and the storage capacity of the multi-channel flash memory device can be greatly increased.
It should be understood that the application of the present application is not limited to the above examples, and that modifications or changes may be made by those skilled in the art based on the above description, and all such modifications and changes are intended to fall within the scope of the appended claims.
Claims (9)
1. The FPGA pin expansion method is characterized by being used for multi-channel flash memory equipment, wherein the FPGA is connected with a CPLD through a CPLD interface; the CPLD comprises a chip selection interface and a state interface, wherein the chip selection interface is connected with a chip selection pin of each flash memory chip and sends a chip selection signal to each flash memory chip; the status interface is connected with the status pins of the flash memory chips and receives status signals sent by the flash memory chips.
2. The FPGA pin expansion method of claim 1, wherein the CPLD interface comprises a chip select frame pin and a chip select data pin for sending chip select signals, and a status frame pin and a status data pin for accepting status signals.
3. The FPGA pin expansion method of claim 2, wherein the CPLD interface further comprises a CPLD interface logic module for encoding and decoding the chip select signal and the state signal, respectively.
4. The FPGA pin expansion method according to claim 3, wherein the CPLD interface logic module comprises a chip select coding module, which is arranged inside the FPGA and used for coding chip select numbers of the effective flash memory into serial data and sending the serial data to the chip select data pins of the CPLD interface; and generating a chip selection frame signal, and sending the chip selection frame signal to a chip selection frame pin of the CPLD interface, wherein the chip selection frame signal is used for identifying the validity of the serial data.
5. The FPGA pin expansion method according to claim 4, wherein the CPLD interface logic module further comprises a chip select decoding module, which is disposed inside the CPLD and used for decoding the serial data signal into parallel chip select numbers and sending the parallel chip select numbers to the chip select pins of the flash memory chip.
6. The FPGA pin expansion method according to claim 3, wherein the CPLD interface logic module comprises a status encoding module, which is disposed inside the CPLD and is used for sequentially transmitting status signals of status pins of the flash memory chips to the status data pins; generating a state frame signal and sending the state frame signal to the state frame pin; the status frame signal is used for marking the position of the first flash memory chip in the status signal.
7. The FPGA pin expansion method according to claim 6, wherein the CPLD interface logic module further comprises a status decoding module, disposed inside the FPGA, for decoding and restoring the status signals of the respective flash memory chips according to the position of the first flash memory chip indicated by the status frame signal after reading the status frame pin and the status data pin.
8. A method of flash chip management in a multi-channel flash memory device, characterized by using the FPGA pin expansion method of any one of claims 1 to 7.
9. The multichannel flash memory system is characterized by comprising an FPGA chip and a plurality of flash memory chips which are connected through a CPLD chip, wherein: the FPGA chip is connected with the CPLD chip through a CPLD interface; the CPLD chip comprises a chip selection interface and a state interface, wherein the chip selection interface is connected with a chip selection pin of each flash memory chip and is used for sending a chip selection signal to each flash memory chip; the state interface is connected with the state pins of the flash memory chips and used for receiving the state signals sent by the flash memory chips.
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| CN201811136982.1A CN110968539A (en) | 2018-09-28 | 2018-09-28 | FPGA pin expansion method for multi-channel flash memory device |
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| US20160139811A1 (en) * | 2013-06-12 | 2016-05-19 | Nec Corporation | Configuration control system and configuration control method |
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2018
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Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN2911791Y (en) * | 2005-12-31 | 2007-06-13 | 北京中星微电子有限公司 | Multi-channel flashmemory transmission controller, chips and memory device |
| CN101488364A (en) * | 2009-02-10 | 2009-07-22 | 成都市华为赛门铁克科技有限公司 | Flash memory control method, apparatus and system |
| CN102103186A (en) * | 2009-12-18 | 2011-06-22 | 上海贝尔股份有限公司 | Debug method of FPGA and equipment thereof |
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Application publication date: 20200407 |