CN2911791Y - Multi-channel flashmemory transmission controller, chips and memory device - Google Patents
Multi-channel flashmemory transmission controller, chips and memory device Download PDFInfo
- Publication number
- CN2911791Y CN2911791Y CN 200520038194 CN200520038194U CN2911791Y CN 2911791 Y CN2911791 Y CN 2911791Y CN 200520038194 CN200520038194 CN 200520038194 CN 200520038194 U CN200520038194 U CN 200520038194U CN 2911791 Y CN2911791 Y CN 2911791Y
- Authority
- CN
- China
- Prior art keywords
- control module
- flash memory
- bus
- data
- bus control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 230000005540 biological transmission Effects 0.000 title claims abstract description 39
- 230000015654 memory Effects 0.000 claims abstract description 106
- 230000000694 effects Effects 0.000 claims description 6
- 230000009131 signaling function Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 2
- 244000233952 Polygonum bistorta Species 0.000 description 1
- 230000006399 behavior Effects 0.000 description 1
- 230000008676 import Effects 0.000 description 1
- 230000005055 memory storage Effects 0.000 description 1
Images
Landscapes
- Read Only Memory (AREA)
Abstract
The utility model discloses a multi-channel flash memory transmission controller, and a chip and a memory device comprising the controller. The controller comprises a control bus control unit and a data bus control unit, wherein the control bus control unit sends a control signal to a plurality of flash memories through a group of diplex control buses, status signals of a plurality of flash memories are inputted into the control bus control unit with a wire and moduses through the diplex control bus, a plurality of flash memories pass through multiple groups of independent data bus under the control signal function at the circumstance of the effective status signal of a wire and a post, and at the same time transmit data to the data bus control unit. The utility model greatly improves the read-write speed of the flash memory.
Description
Technical field
The utility model relates to a kind of storage medium management devices, in particular to the flash memory management device; More specifically, relate to a kind of multi-channel flash memory transmission controller and comprise the chip and the memory device of this controller.
Background technology
As the main storage medium of USB flash disk, the transmission speed of Sheffer stroke gate flash memory (Nand Flash) itself is not high, moreover the operations such as reading and writing of flash memory are also needed the extra stand-by period.So in the high speed USB flash disk was used, in order to improve the transmission speed of USB flash disk, state-of-the-art technology was to adopt the binary channels transmission mechanism.
The transmission of binary channels transmission mechanism and single channel is similar, and it is equivalent to have two independent single channels, and each passage all has one group of independently data address instruction bus and one group control bus independently.The binary channels transmission mechanism is controlled two flash reading and writings simultaneously, thereby transmission speed is doubled.Under the situation of using flash memory, the binary channels transmission mechanism can reach the reading speed of 20MB/s and the writing speed of 12MB/s, and wherein, the difference of read or write speed comes from the difference of flash reading and writing additional wait time.
In the application of USB flash disk, raising speed and capacity are fundamental purposes.Because the definition of USBmass-storage Class bulk-only agreement, read-write can not take place simultaneously, and the read or write speed that the USB2.0 agreement is supported is all up to 480Mbps.The part of deduction usb protocol expense, actual read or write speed are also all up to nearly 48MB/s, and therefore, the read or write speed of existing binary channels transmission mechanism is the bottleneck that USB flash disk speed improves.
Summary of the invention
At the problems referred to above, the purpose of this utility model is, a kind of hyperchannel such as four-way flash memory high-speed transfer scheme are provided, thereby improves the read or write speed of flash memory.
According to first aspect of the present utility model, a kind of multi-channel flash memory transmission controller is provided, described controller comprises control bus control module and data bus control module, described control bus control module transmits control signal to a plurality of flash memories by one group of multiplexing control bus, the status signal of a plurality of flash memories is imported the control bus control module with line and mode by multiplexing control bus, online with after the effective situation of status signal under, a plurality of flash memories transmit data with the data bus control module simultaneously by many groups independent data bus under the effect of control signal.
In first aspect, preferably, described line and mode realize like this: described a plurality of flash memory status signals link together, and link to each other with an end of a pull-up resistor, and the other end of described pull-up resistor links to each other with power supply.Further preferably, the resistance of described pull-up resistor is between 20 kilo-ohms to 30 kilo-ohms.
Preferably, described controller also comprises the major state machine, described control bus control module to the major state machine line of return with after status signal, described major state machine transmits control signal by the control bus control module, and transmits data by data bus control module and a plurality of flash memory.
Preferably, described flash memory is the Sheffer stroke gate flash memory, and described data bus is a data address instruction multiplex bus; By described data address instruction multiplex bus, described data bus control module sends address, command information to a plurality of Sheffer stroke gate flash memories.
Preferably, described hyperchannel is a four-way, and described a plurality of flash memories are four flash memories, and described many group independent data buses are four groups of independent data buses.
According to second aspect, a kind of chip is provided, it is characterized in that, comprise the multi-channel flash memory transmission controller described in the above-mentioned first aspect.
According to the third aspect, a kind of memory device is provided, comprise multi-channel flash memory transmission controller and a plurality of flash memory, described controller comprises control bus control module and data bus control module, described control bus control module transmits control signal to a plurality of flash memories by one group of multiplexing control bus, the status signal of a plurality of flash memories is imported the control bus control module with line and mode by multiplexing control bus, online with after the effective situation of status signal under, a plurality of flash memories transmit data with the data bus control module simultaneously by many groups independent data bus under the effect of control signal.
In the third aspect, preferably, described line and mode realize like this: described memory device comprises a pull-up resistor, and an end of described pull-up resistor links to each other with power supply, and the other end links to each other with a plurality of flash memory status signals that are connected together.Further preferably, the resistance of described pull-up resistor is between 20 kilo-ohms to 30 kilo-ohms.
Preferably, described controller also comprises the major state machine, described control bus control module to the major state machine line of return with after status signal, described major state machine transmits control signal by the control bus control module, and transmits data by data bus control module and a plurality of flash memory.
Preferably, described flash memory is the Sheffer stroke gate flash memory, and described data bus is a data address instruction multiplex bus; By described data address instruction multiplex bus, described data bus control module sends address, command information to a plurality of Sheffer stroke gate flash memories.
According to the utility model, because multiplexing one group of control bus, multi-channel flash memory transmission controller can be controlled a plurality of flash memories simultaneously, and data bus and a plurality of flash memory transmit data simultaneously more by organizing independently, thereby have improved the read or write speed of flash memory greatly.
Description of drawings
For understanding the utility model better, only the utility model is described in further detail in conjunction with the accompanying drawings with an embodiment below.In the accompanying drawing:
Fig. 1 is the structured flowchart of the four-way flash memory transmission controller of an embodiment of the utility model;
Fig. 2 shows the demultiplex control signal of this embodiment of the utility model;
Fig. 3 reads flash memory sequence figure for this embodiment's of the utility model;
Fig. 4 is the flash memory management synoptic diagram of this embodiment of the utility model.
Embodiment
With reference to Fig. 1, Fig. 1 is the structured flowchart of the four-way flash memory transmission controller of an embodiment of the utility model.Four-way flash memory transmission controller 10 is arranged in application chip, and application chip can be used in the memory device such as USB flash disk.Controller 10 comprises major state machine 11, data bus control module 12 and control bus control module 13.Identical with traditional single-channel flash memory transmission control unit (TCU), by other two unit 12,13 of major state machine 11 control, other two unit 12,13 return required information to major state machine 11.For realizing the four-way transmission, in this embodiment, control bus control module 13 links to each other with four Sheffer stroke gate flash memories (hereinafter to be referred as flash memory) by one group of multiplexing control bus 14, data bus control module 12 pass through four groups separately independently data bus I01-I04 link to each other with four flash memories respectively.
With reference to Fig. 2, Fig. 2 shows the demultiplex control signal of this embodiment of the utility model.This group demultiplex control signal comprises that instruction sends that enable signal CLE, address send enable signal ALE, chip selection signal CE, write enable signal WEN, read enable signal REN, write protect signal WP and R/B (ready/busy) (being ready to/hurry) signal.Wherein, CLE, ALE, CE, WEN, REN, WP are the output signals of controller 10, and R/B is the input signal of controller 10, and it has reflected the state of flash memory.Control bus control module 13 is being controlled the behavior of each control signal.Here, the status signal R/B1-R/B4 of four flash memories imports control bus control module 13 with line and mode.
Especially, the line that can realize signal R/B1-R/B4 in the following ways with.The status signal R/B1-R/B4 of four flash memories is linked together, again by a pull-up resistor R and power supply V
CCLink to each other, pull-up resistor R is positioned on the circuit version at application chip place.Consider and will reduce quiescent current, the resistance of pull-up resistor R can not be too little, preferably between 20 kilo-ohms to 30 kilo-ohms.Like this, according to the standard of Sheffer stroke gate flash memory, under the state of being ready to, R/B is output as high resistant, and therefore, when four signals of R/B1-R/B4 all are in when being ready to state, total R/B is drawn high to 1 by pull-up resistor R; When flash memory was in busy condition, R/B was output as 0, therefore, when any one is output as 0 among four signal R/B1-R/B4, power supply V
CCTo the path that forms between the ground by pull-up resistor R and R/B output resistance.Because the output resistance of R/B is very little, the result of dividing potential drop is that the R/B output valve is 0.Therefore, the logic between four signal R/B1-R/B4 be with relation.Like this, realize a pin of R/B1-R/B4 multiplex controller 10 by adopting line and mode, controller 10 just can learn when four flash memories all are in the state of being ready to.
Especially, for the Sheffer stroke gate flash memory, data bus is actually data address instruction multiplex bus.Referring again to Fig. 1, major state machine 11 control data bus control units 12 are to four flash memory transport addresses, command information, and read and write data to four flash memories.Elementary instruction comprises reading and writing, wipes, return to copy and read (copybackread), return and copy instructions such as writing (copybackwrite).Receive at control bus control module 13 under the situation of effective R/B signal, promptly all be in when being ready to state when four flash memories, controlling under the control signal effect that control bus control module 13 sends at major state machine 11, by four groups of data address instruction multiplex bus I01-I04, data bus control module 12 transmits data with four flash memories simultaneously.
Data bus control module 12 returns to major state machine 11 and reads or whether write activity is finished, control bus control module 13 to major state machine 11 lines of return with after R/B.Major state machine 11 input, the output of control bus 14 and data address instruction multiplex bus I01-I04 respectively according to the different operating to flash memory by these two unit controls.For example, suppose that flash memory is the little page or leaf type of Samsung, to read a page or leaf from flash memory, major state machine 11 sends required control signal by control bus control module 13 to four flash memories, and send to four groups of data addresses instruction multiplex buss by data bus control module 12 and to read instruction and the address, the data that need to read in four Hash memory pages with the address appointment are read, and deliver to other unit (not shown) of application chip.Read sequential chart accordingly with reference to Fig. 3.
With reference to Fig. 4, Fig. 4 is the flash memory management synoptic diagram of this embodiment of the utility model.The unit of flash memory storage structure is a page or leaf (page), is example with big page or leaf flash memory, and every page comprises the data field of 2kB and redundancy (spare) district of 64 bytes.These pages or leaves are divided into group, and one group of 64 pages or leaves is called as piece.According to the utility model, realized being that 8kB, redundant area are the page or leaf of 256 bytes thereby form a data field with the address same page of four flash memories and management together.And four flash memories such as are read and write, wipe simultaneously at operation, the same with flash memory of control.Like this, the four-way transmission mechanism can be regarded as the page or leaf size is become original four times, data bus figure place also becomes four times original single channel transmission mechanism.Therefore, reading and writing, the time of a page or leaf of routine operation such as wiping, can operate 4 pages or leaves simultaneously, speed is single pass 4 times, twin-channel 2 times, thereby near the maximum transmitted ability of USB2.0 agreement.
Preamble is an example with four-way Sheffer stroke gate flash memory transmission controller, to the description of being described property of the utility model.In addition, the utility model also can extend to the hyperchannel transmission control to flash memories such as two, eight, 16; The utility model is not limited to the Sheffer stroke gate flash memory, such as, for the rejection gate flash memory, its data bus separates with address bus, similarly, and can a shared group address bus, one group of control bus, and adopt the multi-group data bus to realize the multi-channel data transmission.This is obvious to those skilled in the art.
Obviously, the utility model described here can have many variations, and this variation can not be thought and departs from spirit and scope of the present utility model.Therefore, the change that all it will be apparent to those skilled in the art all is included within the covering scope of these claims.
Claims (12)
1, a kind of multi-channel flash memory transmission controller, comprise control bus control module and data bus control module, it is characterized in that, the data bus control module links to each other by a plurality of flash memories of many group independent data buses, described control bus control module is connected with a plurality of flash memories by one group of multiplexing control bus, described control bus control module transmits control signal to a plurality of flash memories, the status signal of a plurality of flash memories is imported the control bus control module with line and mode by multiplexing control bus, online with after the effective situation of status signal under, a plurality of flash memories transmit data with the data bus control module simultaneously by many groups independent data bus under the effect of control signal.
2, multi-channel flash memory transmission controller as claimed in claim 1, it is characterized in that, described line and mode realize like this: described a plurality of flash memory status signals link together, and link to each other with an end of a pull-up resistor, and the other end of described pull-up resistor links to each other with power supply.
3, multi-channel flash memory transmission controller as claimed in claim 2 is characterized in that, the resistance of described pull-up resistor is between 20 kilo-ohms to 30 kilo-ohms.
4, multi-channel flash memory transmission controller as claimed in claim 1, it is characterized in that, also comprise the major state machine, described control bus control module to the major state machine line of return with after status signal, described major state machine transmits control signal by the control bus control module, and by data bus control module and a plurality of flash memory transmission data.
5, multi-channel flash memory transmission controller as claimed in claim 1 is characterized in that, described flash memory is the Sheffer stroke gate flash memory, and described data bus is a data address instruction multiplex bus; By described data address instruction multiplex bus, described data bus control module sends address, command information to described a plurality of Sheffer stroke gate flash memories.
6, multi-channel flash memory transmission controller as claimed in claim 1 is characterized in that, described hyperchannel is a four-way, and described a plurality of flash memories are four flash memories, and described many group independent data buses are four groups of independent data buses.
7, a kind of chip is characterized in that, comprises each described multi-channel flash memory transmission controller in the claim 1 to 6.
8, a kind of memory device, comprise multi-channel flash memory transmission controller and a plurality of flash memory, described multi-channel flash memory transmission controller comprises control bus control module and data bus control module, it is characterized in that, the data bus control module links to each other by a plurality of flash memories of many group independent data buses, described control bus control module is connected with a plurality of flash memories by one group of multiplexing control bus, described control bus control module transmits control signal to a plurality of flash memories, the status signal of a plurality of flash memories is imported the control bus control module with line and mode by multiplexing control bus, online with after the effective situation of status signal under, a plurality of flash memories transmit data with the data bus control module simultaneously by many groups independent data bus under the effect of control signal.
9, memory device as claimed in claim 8 is characterized in that, described line and mode realize like this: described memory device comprises a pull-up resistor, and an end of described pull-up resistor links to each other with power supply, and the other end links to each other with a plurality of flash memory status signals that are connected together.
10, memory device as claimed in claim 9 is characterized in that, the resistance of described pull-up resistor is between 20 kilo-ohms to 30 kilo-ohms.
11, as each described memory device in the claim 8 to 10, it is characterized in that, described multi-channel flash memory transmission controller also comprises the major state machine, described control bus control module to the major state machine line of return with after status signal, described major state machine transmits control signal by the control bus control module, and by data bus control module and a plurality of flash memory transmission data.
As each described memory device in the claim 8 to 10, it is characterized in that 12, described flash memory is the Sheffer stroke gate flash memory, described data bus is a data address instruction multiplex bus; By described data address instruction multiplex bus, described data bus control module sends address, command information to described a plurality of Sheffer stroke gate flash memories.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200520038194 CN2911791Y (en) | 2005-12-31 | 2005-12-31 | Multi-channel flashmemory transmission controller, chips and memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200520038194 CN2911791Y (en) | 2005-12-31 | 2005-12-31 | Multi-channel flashmemory transmission controller, chips and memory device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN2911791Y true CN2911791Y (en) | 2007-06-13 |
Family
ID=38133655
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200520038194 Expired - Fee Related CN2911791Y (en) | 2005-12-31 | 2005-12-31 | Multi-channel flashmemory transmission controller, chips and memory device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN2911791Y (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101930798A (en) * | 2009-06-25 | 2010-12-29 | 联发科技股份有限公司 | The method of flash memory device, storage arrangement and control flash memory device |
| CN101587740B (en) * | 2008-05-23 | 2011-11-30 | 承奕科技股份有限公司 | Multi-channel solid-state memory system |
| TWI473116B (en) * | 2008-03-07 | 2015-02-11 | A Data Technology Co Ltd | Multi-channel memory storage device and control method thereof |
| CN108932204A (en) * | 2018-06-13 | 2018-12-04 | 郑州云海信息技术有限公司 | A kind of multi-channel flash memory storage system |
| CN110968539A (en) * | 2018-09-28 | 2020-04-07 | 方一信息科技（上海）有限公司 | FPGA pin expansion method for multi-channel flash memory device |
-
2005
- 2005-12-31 CN CN 200520038194 patent/CN2911791Y/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI473116B (en) * | 2008-03-07 | 2015-02-11 | A Data Technology Co Ltd | Multi-channel memory storage device and control method thereof |
| CN101587740B (en) * | 2008-05-23 | 2011-11-30 | 承奕科技股份有限公司 | Multi-channel solid-state memory system |
| CN101930798A (en) * | 2009-06-25 | 2010-12-29 | 联发科技股份有限公司 | The method of flash memory device, storage arrangement and control flash memory device |
| CN101930798B (en) * | 2009-06-25 | 2014-04-16 | 联发科技股份有限公司 | Flash memory device, memory device and method for controlling flash memory device |
| CN108932204A (en) * | 2018-06-13 | 2018-12-04 | 郑州云海信息技术有限公司 | A kind of multi-channel flash memory storage system |
| CN110968539A (en) * | 2018-09-28 | 2020-04-07 | 方一信息科技（上海）有限公司 | FPGA pin expansion method for multi-channel flash memory device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100397380C (en) | Multi-channel flash memory transmission controller, chip and storage device | |
| CN105474319B (en) | For configuring the device and method of the I/O of the memory of mixing memory module | |
| EP1929482B1 (en) | Portable data storage using slc and mlc flash memory | |
| CN101853207B (en) | Storage device | |
| CA2740511A1 (en) | A composite memory having a bridging device for connecting discrete memory devices to a system | |
| KR100875978B1 (en) | Memory card and memory system including it | |
| CN2911791Y (en) | Multi-channel flashmemory transmission controller, chips and memory device | |
| US10789172B2 (en) | Memory device | |
| CN102999452A (en) | Memory device | |
| CN101656096A (en) | Registered dimm memory system | |
| US10032494B2 (en) | Data processing systems and a plurality of memory modules | |
| JP5533963B2 (en) | Memory module with configurable input / output ports | |
| CN101740102A (en) | Multi-channel flash memory chip array structure and write-in and read-out methods thereof | |
| CN110069443B (en) | UFS storage array system based on FPGA control and data transmission method | |
| US9514790B2 (en) | Data transmission circuit | |
| CN115904254B (en) | Hard disk control system, method and related components | |
| CN109213687A (en) | Data storage device, memory operation method and operation instruction execution method | |
| CN102622191A (en) | High-speed mass storage plate | |
| US10365834B2 (en) | Memory system controlling interleaving write to memory chips | |
| KR102596491B1 (en) | Semiconductor device | |
| JPWO2008038647A1 (en) | RAID system and data transfer method in RAID system | |
| CN101571790A (en) | Flash memory controller | |
| CN101751982B (en) | Connection method between flesh memory controller and flesh memory chip in flesh memory storing device | |
| JP4760778B2 (en) | Flash memory system and flash memory module incorporated in the system | |
| KR102242957B1 (en) | High speed NAND memory system and high speed NAND memory package device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20070613 Termination date: 20111231 |