JP4760778B2 - Flash memory system and flash memory module incorporated in the system - Google Patents

Description

  The present invention relates to a flash memory system for providing a storage area to a host system, and a flash memory module incorporated in the system.

Equipped with multiple flash memory cards with parallel interface such as ATA (Advanced Technology Attachment), so that the host device can read and write data to and from these multiple flash memory cards, such as SCSI, USB or E-IDE A storage device connected to a host device via an interface is known (see, for example, Patent Document 1).
Japanese Patent Laid-Open No. 2000-207137 (FIGS. 1 to 3)

  In recent years, in order to increase the data transfer speed, the serial interface rather than the parallel interface is preferred in that there is no problem such as crosstalk. SATA (Serial ATA), a higher-speed serial interface that appeared after ATA, is a good example.

  Even in a storage device using a flash memory, it is desired to take advantage of the high speed by using such a high speed interface. In that case, since the data transfer speed of the flash memory itself is not so high, it is preferable to adopt a structure in which a large number of flash memories can be accessed in parallel from the high-speed interface side in order to take advantage of the high-speed interface.

  However, the interface of the flash memory itself is usually a parallel interface, and the number of signal lines is considerably large. Therefore, if a large number of flash memories are connected in parallel, the total number of signal lines becomes very large, making it difficult to design the arrangement of the large number of signal lines.

  Accordingly, an object of the present invention is to make it possible to easily design a flash memory system capable of accessing a large number of flash memories in parallel.

According to the present invention, a flash memory system for providing a storage area to a host system includes:
One or more flash memory modules;
A flash memory controller connected to the one or more flash memory modules and relaying and controlling communication between the host system and the one or more flash memory modules; Each of the flash memory modules
A plurality of flash memories each having a predetermined parallel interface;
A serial-parallel conversion circuit connected to the flash memory controller via a predetermined serial interface and connected to the plurality of flash memories via the parallel interface; And the serial-parallel conversion circuit is
Instruction information and user data in the serial signal format for the flash memory are transferred to the flash memory controller via the serial interface,
Instruction information and user data in parallel signal format for the flash memory are transferred to and from the flash memory via the parallel interface, and instruction information and user data in serial signal format for the flash memory and the flash memory The signal format is converted between the parallel signal format instruction information and user data.

  In a preferred embodiment of the flash memory system of the present invention, the number of the flash memory modules connected to the flash memory controller is variable. The number of flash memory modules can be selected according to the desired storage capacity of the flash memory system. Even if the number of flash memory modules is increased in order to increase the storage capacity, the number of signal lines of the serial interface of the flash memory module is smaller than that of the parallel interface, so that the design of signal line arrangement is easy.

  In a preferred embodiment, each flash memory module is configured as one module or one package, and the number of the flash memories connected to the serial / parallel conversion circuit is a constant value. Even if the flash memory system designer increases the number of flash memory modules to increase the storage capacity, the design of the flash memory module itself, for example, the layout of the signal lines of the parallel interface of the flash memory, etc. No need to be bothered.

  In a preferred embodiment, the serial interface has one serial input / output signal line. The serial / parallel conversion circuit and the flash memory controller sequentially transfer instruction information and user data in the serial signal format to the flash memory through the serial input / output signal line. This minimizes the number of signal lines of the serial interface for transferring instruction information (for example, commands and addresses) to the flash memory and user data.

  In a preferred embodiment, the serial / parallel conversion circuit and the flash memory controller are configured to transmit not only the serial signal format instruction information and user data but also the serial / parallel to the flash memory through the serial input / output signal line. Instruction information in the serial signal format for the conversion circuit is also transferred sequentially. As a result, the number of signal lines of the serial interface for transferring instruction information and user data to each of the flash memory and the serial / parallel conversion circuit is minimized.

  In a preferred embodiment, the serial interface further includes one command signal line. The serial / parallel conversion circuit and the flash memory controller indicate whether the serial signal transferred through the serial input / output signal line is instruction information for the serial / parallel conversion circuit through the command signal line. Transfer command signals. As a result, the number of serial interface signal lines for controlling the operation of the serial / parallel conversion circuit is minimized.

  In a preferred embodiment, the parallel interface includes a plurality of parallel input / output signal lines for sequentially transferring instruction information and user data in a parallel signal format to the flash memory, and a plurality of types of the flash memory. A plurality of control signal lines for transferring control signals. The serial-to-parallel converter circuit is directed to the flash memory transferred through the parallel interface in accordance with an instruction by the instruction information to the serial-to-parallel converter circuit transferred from the flash memory controller through the serial input / output signal line. Manipulate user data and control signals.

The instruction information for the serial / parallel converter circuit includes, for example, the following four types of signals:
(1) An address identification signal for instructing to supply the subsequent serial signal as an address to the flash memory,
(2) A command identification signal for instructing to supply a serial signal subsequent thereto as a command to the flash memory,
(3) a data identification signal instructing to supply the subsequent serial signal as user data to the flash memory; and
(4) a read identification signal for instructing to read user data from the flash memory by operating a predetermined control signal for the flash memory;
Can be included. The serial / parallel conversion circuit operates the instruction information, user data, and control signals for the flash memory in accordance with the instruction information.

  The present invention also provides a flash memory module for incorporation into the flash memory system described above.

  According to the present invention, a flash memory system capable of accessing a large number of flash memories in parallel can be easily designed.

  FIG. 1 shows the overall configuration of a flash memory system according to an embodiment of the present invention.

  As shown in FIG. 1, the flash memory system 10 according to one embodiment may be connected to a host system via an arbitrary host interface 18 such as SATA (Serial ATA), USB, or ATA. For example, a high-speed interface such as SATA may be selected as the host interface 18.

  The flash memory system 10 includes at least one flash memory controller 12 and one or more (typically, a power of 2 such as 4 or 8) connected to the flash memory controller 12. The flash memory modules 14, 14,. The flash memory controller 12 relays and controls communication between the host system and the flash memory modules 14, 14,... Each flash memory module 14, 14,... Functions like one flash memory as viewed from the flash memory controller 12.

  Each flash memory module 14 includes at least one serial-parallel (S / P) conversion circuit 30 and one or more, preferably a plurality (typically 2 (typically 2)) connected to the S / P conversion circuit 30. , Etc. (for example, 4 or 8).

  Preferably, the flash memory system 10 includes a flash memory controller 12 and flash memory modules 14, 14,... Mounted on a single circuit board or housed in a single IC housing. State Drive / Solid State Disk). Further, preferably, each flash memory module 14 has the IC chip of the S / P conversion circuit 30 and the IC chips of the flash memories 32, 32,... Mounted on one circuit board or in one IC housing. It may be configured as a single module or a single package.

  Preferably, the number of flash memory modules 14, 14,... Connected to the flash memory controller 12 may be variable for the designer of the flash memory system 10. Accordingly, the designer can increase or decrease the number of flash memory modules 14, 14,... Connected to the flash memory controller 12 according to a desired value of the storage capacity of the flash memory system 10.

  On the other hand, the number of flash memories 32, 32,... In each flash memory module 14 may be fixed (for example, four), and the number of flash memories 32 cannot be changed for the designer of the flash memory system 10. It's okay. For example, each flash memory module 14 may be provided to the designer of the flash memory system 10 as one module or one package of a predetermined design, and for each designer of the flash memory system 10, each flash memory module 14 The design of can be immutable.

  A predetermined serial interface 16 is employed as a communication interface between the flash memory controller 12 and each flash memory module 14 (details will be described later). On the other hand, a predetermined parallel interface 34 is adopted as a communication interface between the S / P conversion circuit 30 and each flash memory 32 in each flash memory module 14 (details will be described later). The S / P conversion circuit 30 in each flash memory module 14 performs conversion between the serial interface 16 and the parallel interface 34 described above. The conversion performed by the S / P conversion circuit 30 is physical conversion of signals such as conversion of serial and parallel signal formats between the serial interface 16 and the parallel interface 34 and adjustment of transfer timing associated therewith. On the other hand, the flash memory controller 12 performs conversion and operation of the actual contents of transfer information such as address conversion, defective book management, and wear leveling.

  Instruction information such as commands and addresses for the flash memories 32, 32,... Is supplied from the flash memory controller 12 to the flash memories 32, 32,. A signal supplied from the flash memory controller 12 to each flash memory module 14 is a serial signal through the serial interface 16. The serial signal is converted into a parallel signal by the S / P conversion circuit 30, and the parallel signal is supplied to the flash memories 32, 32,.

  The user data written to the flash memories 32, 32,... Or the user data read from the flash memories 32, 32,... Are sent from the flash memory controller 12 to the flash memories 32, 32,. ,... Are supplied as serial signals to the flash memory controller 12.

  FIG. 2 shows signal configurations of the serial interface 16 and the parallel interface 34 of the S / P conversion circuit 30.

  As shown in FIG. 2, the serial interface 16 has three signal lines 20, 22, and 24. That is, they are a timing clock (CLK) signal line 20, a command destination (CMD) signal line 22, and a serial input / output (S_I / O) signal line 24.

  The CLK signal line 20 transfers a timing clock (CLK) signal for determining the operation timing of the entire flash memory module 14. The S_I / O signal line 24 is written to / from instruction information (described later) for the S / P conversion circuit 30, instruction information such as commands and addresses for the flash memories 32, 32, and so on, and the flash memories 32, 32, and so on. User data to be read is transferred serially and sequentially as a serial input / output (S_I / O) signal.

  The CMD signal line 22 transfers a command (CMD) signal for identifying whether or not the S_I / O signal transferred by the S_I / O line 24 is instruction information for the S / P conversion circuit 30 described above. To do. That is, when the CMD signal is active (low level because of negative logic), it means that the S_I / O signal is instruction information for the S / P conversion circuit 30, and when it is inactive (high level), S_I / O This means that the O signal is not instruction information for the S / P conversion circuit 30 (in other words, information such as commands, addresses, and user data for the flash memories 32, 32,...).

  On the other hand, the parallel interface 34 has more signal lines 40 to 50 than the serial interface 16. That is, they include a plurality of chip enable (CE) signal lines 40, 40,..., A command latch enable (CLE) signal line 42, an address latch enable (ALE) signal line 44, a write enable (WE) signal line 46, A read enable (RE) signal line 48 and a parallel input / output (P_I / O) signal bus 50.

  .. Of each of the plurality of flash memories (IC chips) 32, 32,... Connected to the S / P conversion circuit 30 is connected in a one-to-one relationship. Each CE signal line 40 supplies a chip enable (CE) signal to one flash memory (IC chip) 32 to which the CE signal line 40 is connected (in FIG. 2, there are four flash memories 32, 32,...). The case of doing is illustrated). When each CE signal is active (low level because of negative logic), the corresponding flash memory 32 is enabled, and when it is inactive (high level), the corresponding flash memory 32 is disabled.

  All of the signal lines 42 to 50 in the parallel interface 34 other than the CE signal lines 40, 40,... Described above are connected to all of the plurality of flash memories 32, 32,. And are shared by all the flash memories 32, 32,... Actually, only the flash memory enabled by the above-described CE signal among the flash memories 32, 32,... Uses the shared signal lines 42 to 50.

  The P_I / O bus 50 is composed of a predetermined number of signal lines (eight in this embodiment), and parallel input / output (P_I / O) in units of a predetermined number of bits (in this embodiment, 8 bits (1 byte)). O) Transfer the signal. The P_I / O bus 50 uses the command information and address information for the flash memories 32, 32,... And the user data written to / read from the flash memories 32, 32,. Forward to.

  The CLE signal line 42 transfers a command latch enable (CLE) signal indicating whether or not the P_I / O signal transferred by the P_I / O bus 50 is a command. That is, if the CLE signal is active (high level because of positive logic), it means that the P_I / O signal is a command. The ALE signal line 44 transfers an address latch enable (ALE) signal indicating whether or not the P_I / O signal transferred by the P_I / O bus 50 is an address. That is, if the ALE signal is active (high level because of positive logic), it means that the P_I / O signal is an address. When user data is transferred on the P_I / O bus 50, both the CLE signal and the ALE signal are inactive (low level).

  The WE signal line 46 provides the flash memories 32, 32,... With a write enable (WE) signal for causing the flash memories 32, 32,... To take in the P_I / O signal on the P_I / O bus 50. The flash memories 32, 32,... Fetch the P_I / O signal from the P_I / O bus 50 in synchronization with the rising edge of the WE signal. The RE signal line 48 provides the flash memories 32, 32,... With a read enable (RE) signal for causing the flash memories 32, 32,... To output a P_I / O signal to the P_I / O bus 50. The flash memories 32, 32,... Output a P_I / O signal to the P_I / O bus 50 in response to the rising edge of the RE signal.

  The S / P conversion circuit 30 receives instruction information such as commands and addresses in the form of S_I / O signals for the flash memories 32, 32,... Supplied from the flash memory controller 12 through the S_I / O line 24 of the serial interface 16. The data is converted into a parallel P_I / O signal format in byte units and transferred to the flash memories 32, 32,... Via the P_I / O bus 50 of the parallel interface 34. When the transferred command is a write command, the S / P conversion circuit 30 similarly converts the user data in the format of the S_I / O signal supplied after the address from the flash memory controller 12 through the S_I / O line 24 to P_I. The data is converted into the / O signal format and transferred to the flash memories 32, 32,... Via the P_I / O bus 50. On the other hand, when the transferred command is a read command, the S / P conversion circuit 30 is a user in the format of the P_I / O signal read out from the flash memories 32, 32,... Onto the P_I / O bus 50 after the address transfer. The data is converted into the format of the S_I / O signal and transferred to the flash memory controller 12 through the S_I / O line 24.

  When writing / reading user data as described above, the S / P conversion circuit 30 also controls a plurality of types of control necessary for controlling the flash memories 32, 32,. Generate signals (ie, CE signal, CLE signal, ALE signal, WE signal, and RE signal) and supply the control signals to the flash memories 32, 32,... Via the corresponding signal lines 40 to 48 of the parallel interface 34. To do.

  The S / P conversion circuit 30 generates the above-described control signal based on minimum instruction information for the S / P conversion circuit 30 supplied from the flash memory controller 12 through the S_I / O line 24. The S / P conversion circuit 30 is configured such that the signal supplied from the flash memory controller 12 through the S_I / O line 24 is information such as a command, an address, and user data to be transferred to the flash memory, or S / P conversion. Whether the signal is instruction information for the circuit 30 is identified based on the CMD signal supplied from the flash memory controller 12 through the CMD signal line 22.

  In this embodiment, the instruction information for the S / P conversion circuit 30 supplied from the flash memory controller 12 through the S_I / O line 24 includes the following four types of signals.

  (1) Address identification (ADD_ID) signal. This signal instructs the S / P conversion circuit 30 to supply a signal immediately following this signal to the designated flash memory 32, 32,... As an address.

  (2) Command identification (CMD_ID) signal. This signal means an instruction to supply a signal immediately following this signal to the designated flash memory 32 as a command.

  (3) Data identification (DAT_ID) signal. This signal means an instruction to supply the signal immediately following this signal to the designated flash memory 32 as user data.

  (4) Lead identification (RED_ID) signal. This signal indicates an instruction that data can be read from the flash memory 32 by operating a read enable (RE) signal.

  The four types of instruction information described above all include memory designation information for designating the flash memory 32 that is the destination of the instructed operation. The S / P conversion circuit 30 controls the chip enable (CE0 to CE3) signals for the plurality of flash memories 32, 32,... Based on the memory designation information so that only the designated flash memory 32 is enabled. To do.

  Further, the above-described three types of identification signals, that is, an address identification (ADD_ID) signal, a command identification (CMD_ID) signal, and a data identification (DAT_ID) signal include information on the flash memories 32, 32,. Signal type information for specifying the type (command, address or user data).

  In addition, the read identification (RED_ID) signal includes the number of times of toggling, that is, user data read at a time (including not only net user data but also auxiliary data such as ECC data attached to pure user data) Byte number information indicating the number of bytes in one unit is also included. Since the number of bytes of data to be read is determined in advance, for example, 512 bytes for user data and a predetermined number of bytes for ECC data, the byte number information only needs to be able to specify the determined number of bytes.

  The operation of the S / P conversion circuit 30 in the flash memory system 10 having the above configuration will be described below.

  First, the operation of the S / P conversion circuit 30 when writing data to the designated flash memory 32 will be described. 3 to 5 are timing charts showing input / output signals of the S / P conversion circuit 30 at the time of writing (by connecting them in the order of the drawings). 3 to 5, the three types of signals shown at the top are signals transferred through the serial interface 16 between the flash memory controller 12 and the S / P conversion circuit 30, and a number of signals shown below the signals are transferred. Is a signal transferred through the parallel interface 34 between the S / P conversion circuit 30 and the flash memories 32, 32,.

  Various operations described below of the S / P conversion circuit 30 are performed in synchronization with the CLK signal from the flash memory controller 12. The S / P conversion circuit 30 transfers the S_I / O signal in units of 1 bit and transfers the P_I / O signal in units of 1 byte in response to the rising edge and the falling edge of the CLK signal.

  In the data read process, as shown in FIG. 3, first, in the section P1, the CMD signal is activated by the flash memory controller 12, and the write command immediately follows as the S_I / O signal. A DAT_ID signal (for example, 1-byte data) is supplied. The S / P conversion circuit 30 inputs the DAT_ID signal in bit units in synchronization with the rising edge and falling edge of the CLK signal. The S / P conversion circuit 30 treats the input DAT_ID signal as instruction information for the S / P conversion circuit 30 according to the CMD signal, and decodes it. The S / P conversion circuit 30 identifies the flash memory 32 as the write destination from the decoding result of the input DAT_ID signal.

  In a section P2 immediately after the section P1, the CMD signal is deactivated by the flash memory controller 12, and a command data (CMD_DAT) signal (for example, 1 byte data) that is a write command to the flash memory 32 is used as the S_I / O signal. ) Is supplied. The S / P conversion circuit 30 inputs a subsequent CMD_DAT signal, that is, a write command, according to the decoding result of the DAT_ID signal input in the section P1. The S / P conversion circuit 30 treats the input CMD_DAT signal, that is, the write command as instruction information for the flash memory 32 according to the CMD signal, and converts it into a parallel signal in units of bytes so that it can be output as a P_I / O signal. Convert (only the format is converted into a parallel signal, and the actual content of the write command is not changed).

  In a section P3 immediately following the section P2, the CMD signal is activated again by the flash memory controller 12, and an ADD_ID signal (for example, 1-byte data) means that an address immediately follows as an S_I / O signal. Is supplied. The S / P conversion circuit 30 receives the ADD_ID signal. The S / P conversion circuit 30 treats the input ADD_ID signal as instruction information for the S / P conversion circuit 30 according to the CMD signal, and decodes it. The S / P conversion circuit 30 specifies the write destination flash memory 32 from the decoding result of the input ADD_ID signal.

  In the section P5 immediately after the section P3, the CMD signal is deactivated again by the flash memory controller 12, and an address data (ADD_DAT) signal (for example, a predetermined address) as a write destination address for the flash memory 32 is used as the S_I / O signal. Multi-byte data) is provided. The S / P conversion circuit 30 inputs a subsequent ADD_DAT signal, that is, an address, according to the decoding result of the ADD_ID signal input in the section P3. The S / P conversion circuit 30 treats the input ADD_DAT signal, that is, the address, as instruction information for the flash memory 32 according to the CMD signal, and converts it into a parallel signal in units of bytes so that it can be output as a P_I / O signal. (Only the format is converted into a parallel signal, and the actual contents of the address are not changed.)

  In addition, when a CMD_DAT signal, that is, a write command is input in the above-described section P2, in the subsequent section P4, the S / P conversion circuit 30 stores the flash memory 32 of the write destination specified from the CMD_ID signal input in the section P1. The corresponding CE signal (CE0 signal in the illustrated example) is activated to enable it. At the same time, the S / P conversion circuit 30 outputs, as a P_I / O signal, the CMD_DAT signal, that is, the write command input in the period P2 and converted into the parallel signal in accordance with the decoding result of the CMD_ID signal. At the same time, the S / P conversion circuit 30 activates the CLE signal according to the result of decoding the CMD_ID signal, and informs the write destination flash memory 32 that the output P_I / O signal is a command. Further, the S / P conversion circuit 30 lowers the WE signal to a low level and then raises it to a high level according to the result of decoding the CMD_ID signal. Thereby, the flash memory 32 of the write destination inputs the CMD_DAT signal, that is, the write command supplied as the P_I / O signal in synchronization with the rising edge of the WE signal.

  In addition, when the ADD_DAT signal, that is, the first byte of the address is input in the interval P5, in the subsequent interval P6, the S / P conversion circuit 30 stores the flash memory 32 of the write destination specified from the ADD_ID signal input in the interval P3. The corresponding CE signal (CE0 signal in the illustrated example) is activated to enable it. At the same time, the S / P conversion circuit 30 outputs, as a P_I / O signal, the ADD_DAT signal, that is, the address input in the interval P5 and converted into the parallel signal according to the decoding result of the ADD_ID signal. At the same time, the S / P conversion circuit 30 activates the ALE signal in accordance with the decoding result of the ADD_ID signal, and informs the write destination flash memory 32 that the output P_I / O signal is an address. Furthermore, the S / P conversion circuit 30 lowers the WE signal to a low level and raises it to a high level every time each byte of an address is output according to the decoding result of the ADD_ID signal. Thereby, the flash memory 32 at the write destination inputs the ADD_DAT signal supplied as the P_I / O signal, that is, each byte of the address, in synchronization with the rising edge of the WE signal. The S / P conversion circuit 30 continues this operation until the last byte of the ADD_DAT signal has been input to the flash memory 32.

  As shown in FIG. 4, in the section P7 immediately after the section P5 described above, the flash memory controller 12 activates the CMD signal again, and the user data immediately follows as the S_I / O signal. Meaning DAT_ID signal (eg 1 byte data) is supplied. The S / P conversion circuit 30 inputs the DAT_ID signal. The S / P conversion circuit 30 treats the input DAT_ID signal as instruction information for the S / P conversion circuit 30 according to the CMD signal, and interprets it. The S / P conversion circuit 30 identifies the flash memory 32 as the write destination from the decoding result of the input DAT_ID signal.

  In a section P8 immediately after the section P7, the CMD signal is deactivated again by the flash memory controller 12, and a data (DATA) signal (for example, user data to be written to the flash memory 32 as an S_I / O signal (for example, A predetermined number of bytes of data) is supplied. The S / P conversion circuit 30 inputs the subsequent DATA signal, that is, user data, according to the decoding result of the DAT_ID signal input in the section P7. The S / P conversion circuit 30 treats the DAT signal as user data for the flash memory 32 in accordance with the CMD signal, and converts this into a parallel signal in units of bytes so that it can be output as a P_I / O signal (its format). Are converted into parallel signals, and the actual contents of the user data are not changed).

  In addition, when the DAT signal, that is, the first byte of user data is input in the above-described section P8, in the subsequent section P9, the S / P conversion circuit 30 flashes the write destination specified by the DAT_ID signal input in the section P7. The memory 32 is enabled by activating a corresponding CE signal (CE0 signal in the illustrated example). At the same time, the S / P conversion circuit 30 converts the DATA signal input in the interval P8 and converted into the parallel signal, that is, the user data into the flash memory 32 to be written as the P_I / O signal according to the decoding result of the DAT_ID signal. Output. At the same time, the S / P conversion circuit 30 makes both the CLE signal and the ALE signal inactive according to the decoding result of the DAT_ID signal, and writes that the output P_I / O signal is neither a command nor an address. The previous flash memory 32 is notified. Furthermore, the S / P conversion circuit 30 lowers the WE signal to a low level and raises it to a high level each time a DATA signal, that is, each byte of user data, is output according to the decoding result of the DAT_ID signal. Thereby, the flash memory 32 of the write destination inputs the DAT signal output as the P_I / O signal, that is, each byte of user data in synchronization with the rising edge of the WE signal (at this time, in the flash memory 32, User data is written to a register in flash memory 32, but not yet written to a memory cell). The S / P conversion circuit 30 continues this operation until the DATA signal, that is, the last byte of user data is completely input to the flash memory 32.

  As shown in FIG. 5, the CMD signal is activated again by the flash memory controller 12 in the section P10 immediately after the section P8 described above, and the program command immediately follows as the S_I / O signal. Meaning DAT_ID signal (eg 1 byte data) is supplied. The S / P conversion circuit 30 inputs the DAT_ID signal. The S / P conversion circuit 30 treats the DAT_ID signal as instruction information for the S / P conversion circuit 30 according to the CMD signal, and decodes it. The S / P conversion circuit 30 identifies the flash memory 32 as the write destination from the decoding result of the DAT_ID signal.

  In the section P11 immediately after the section P10, the CMD signal is deactivated again by the flash memory controller 12, and a program command for the flash memory 32 (instruction to write data from the register to the memory cell is given as the S_I / O signal. Command data (CMD_DAT) signal (for example, 1-byte data). The S / P conversion circuit 30 inputs a subsequent CMD_DAT signal, that is, a program command, according to the decoding result of the DAT_ID signal input in the section P10. The S / P conversion circuit 30 treats the CMD_DAT signal, that is, the program command, as instruction information for the flash memory 32 in accordance with the CMD signal, and converts it into a parallel signal in units of bytes so that it can be output as a P_I / O signal (that Only the signal format is converted, and the actual contents of the program command are not changed.)

  In addition, when a CMD_DAT signal, that is, a program command is input in the above-described section P11, in the subsequent section P12, the S / P conversion circuit 30 stores the flash memory 32 of the write destination specified by the CMD_ID signal input in the section P10. The corresponding CE signal (CE0 signal in the illustrated example) is activated to enable it. At the same time, the S / P conversion circuit 30 outputs, as a P_I / O signal, a CMD_DAT signal, that is, a program command, input in the section P11 and converted into a parallel signal according to the decoding result of the DAT_ID signal. At the same time, the S / P conversion circuit 30 activates the CLE signal according to the result of decoding the DAT_ID signal, and informs the write destination flash memory 32 that the output P_I / O signal is a command. Further, the S / P conversion circuit 30 lowers the WE signal to a low level and then raises it to a high level according to the result of decoding the DAT_ID signal. Thereby, the flash memory 32 at the write destination inputs the CMD_DAT signal, that is, the program command output as the P_I / O signal in synchronization with the rising edge of the WE signal. In response to the input program command, the flash memory 32 of the writing destination designates the user data held in the register (written in the register in the section P9) by the address (input in the section P6) To a location in the designated memory cell.

  The above is the operation of the S / P conversion circuit 30 when writing data to the designated flash memory 32. Next, the operation of the S / P conversion circuit 30 when reading data from the designated flash memory 32 will be described. 6 to 8 are timing charts showing input / output signals of the S / P conversion circuit 30 at the time of writing (by connecting them in the order of the drawings).

  The operation in the first half of the data reading process, that is, the operations in the sections P1 to P6 shown in FIGS. 6 to 7 are the following two differences from the operations in the sections P1 to P6 shown in FIG. Other than that, the same applies.

  The first difference is that the DAT_ID signal (for example, 1-byte data) supplied from the flash memory controller 12 to the S / P conversion circuit 30 as the S_I / O signal in the first section P1 is immediately followed by the read command. It is a point that it means to do. This DAT_ID signal includes information for specifying the read-out flash memory 32.

  The second difference is that the CMD_DAT signal (for example, 1-byte data) supplied from the flash memory controller 12 to the S / P conversion circuit 30 as the S_I / O signal in the section P2 is a read command for the flash memory 32. It is. Naturally, the CMD_DAT signal supplied from the S / P conversion circuit 30 to the flash memory 32 as the P_I / O signal in the section P4 is also a read command for the flash memory 32.

  When the ADD_DAT signal, that is, the entire address is supplied to the flash memory 32 in the section P6 shown in FIGS. 6 to 7, the CMD signal is again activated by the flash memory controller 12 in the section P7 shown in FIG. At the same time, as the S_I / O signal, a RED_ID signal (for example, 1-byte data), which is an instruction to read data from the flash memory 32 by operating the RE signal, is supplied. The S / P conversion circuit 30 receives the RED_ID signal. The S / P conversion circuit 30 treats the input RED_ID signal as instruction information for the S / P conversion circuit 30 according to the CMD signal, and decodes it. The S / P conversion circuit 30 specifies the flash memory 32 from which data is read from the decoding result of the RED_ID signal.

  In the section P8 after the section P7, the S / P conversion circuit 30 sets the write destination flash memory 32 specified from the RED_ID signal input in the section P7, and the corresponding CE signal (CE0 signal in the illustrated example). Enable by activating. At the same time, the S / P conversion circuit 30 deactivates both the CLE signal and the ALE signal according to the decoding result of the RED_ID signal input in the section P7, and neither the command nor the address is output as the P_I / O signal. This is notified to the flash memory 32 of the reading source. Furthermore, the S / P conversion circuit 30 outputs the RE signal at a predetermined timing suitable for the reading source flash memory 32 to read each byte of user data to the P_I / O signal line 50 according to the result of decoding the RED_ID signal. Repeat the operation of raising to high level after lowering to level.

  Thereby, in the section P9, the read-out flash memory 32 reads user data as a P_I / O signal from the storage location designated by the ADD_DAT signal, that is, the address, in synchronization with the rising edge of the WE signal. The S / P conversion circuit 30 inputs the user data read out as the P_I / O signal in the section P9 according to the decoding result of the RED_ID signal input in the section P7, and converts this into the format of the S_I / O signal Then, it is supplied to the flash memory controller 12 as an S_I / O signal in section P10. After that, although not shown in the figure, the S / P conversion circuit 30 supplies a status read command to the read-out flash memory 32 to confirm that the user data has been normally read into the register. .

  The above is the operation of the S / P conversion circuit 30 in the data reading process.

  According to the flash memory system 10 according to the embodiment of the present invention described above, a large-capacity flash memory system 10 is configured by increasing the number of flash memory modules 14, 14,... Connected to the flash memory controller 12. it can. The interface between the flash memory controller 12 and the flash memory module 14 is the serial interface 16 and the number of signal lines is small. In particular, with one S_I / O signal line 24, instruction information for the S / P conversion circuit 30, instruction information for the flash memories 32, 32,..., And writing / reading to / from the flash memories 32, 32,. Since the user data to be transmitted is transferred sequentially, the number of signal lines of the serial interface 16 is only three. As a result, even when the number of flash memory modules 14, 14,... Is increased, the total number of signal lines between the flash memory controller 12 and the flash memory module 14 is significantly smaller than when the parallel interface is used. Thus, the layout design of a small number of signal lines is easy for the designer.

  Further, each flash memory module 14 can be provided to the designer of the flash memory system 10 as one module or one package of a predetermined design. No matter how the total number of flash memories 32, 32,... In the flash memory system 10 is increased in order to increase the capacity of the flash memory system 10, the designer of the flash memory system 10 can design each flash memory module 14 itself. For example, the design of the signal line arrangement of the parallel interface 34 between the S / P conversion circuit 30 and the flash memories 32, 32,.

  Further, since the flash memory controller 12 can access a large number of flash memories 32, 32,... In parallel, high-speed data transfer is possible.

  Further, the operations on the information (command, address, user data, etc.) for the flash memories 32, 32,... Performed by the S / P conversion circuit 30 are only conversion of serial and parallel signal formats and adjustment of transfer timing associated therewith. Since the actual content of the information is not changed, the configuration of the S / P conversion circuit 30 can be relatively simple.

  Such a flash memory system according to the above-described embodiment can be easily designed by a designer of the system, and has a large capacity and a high transfer speed by parallel access to a large number of flash memories 32, 32,. Excellent performance can be demonstrated. As a result, when a high-speed interface such as SATA is used for the host interface 18, high-speed data transfer that fully utilizes the high-speed property of the host interface 18 is possible.

  In the flash memory system according to the above-described embodiment, when a problem such as failure or frequent errors occurs in a certain flash memory module 14, the abnormal flash memory module 14 is replaced with another normal flash memory module 14. It can also be configured to be replaced with. For example, all user data stored in the abnormal flash memory module 14 is read to the flash memory controller 12 or the host system, and all of the read user data is transferred to another normal flash memory module 14. This can be realized by performing a copying operation of writing. A dedicated command set for executing such a copy operation is used as instruction information supplied from the host system to the flash memory controller 12 and / or S / P conversion in the flash memory module 14 from the flash memory controller 12. The instruction information supplied to the circuit 30 may be provided in addition to the above-described instruction information for normal access operations such as writing and reading.

  The embodiment described above is merely an example for explaining the present invention, and is not intended to limit the scope of the present invention to this embodiment. The present invention can be implemented in various modes other than the above-described embodiments without departing from the gist thereof.

1 is a block diagram showing an overall configuration of a flash memory system according to an embodiment of the present invention. The block diagram which shows the signal structure of the serial interface of a S / P conversion circuit, and a parallel interface. 4 is a timing chart showing input / output signals of the S / P conversion circuit 30 when data is written to the flash memory. 4 is a timing chart showing input / output signals of the S / P conversion circuit 30 when data is written to the flash memory. 4 is a timing chart showing input / output signals of the S / P conversion circuit 30 when data is written to the flash memory. 6 is a timing chart showing input / output signals of the S / P conversion circuit 30 when reading data from the flash memory. 6 is a timing chart showing input / output signals of the S / P conversion circuit 30 when reading data from the flash memory. 6 is a timing chart showing input / output signals of the S / P conversion circuit 30 when reading data from the flash memory.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Flash memory system 12 Flash memory controller 14 Flash memory module 16 Serial interface 20 Timing clock (CLK) signal line 22 Command (CMD) signal line 24 Serial input / output (S_I / O) signal line 30 Serial parallel (S / P) Conversion circuit 32 Flash memory 34 Parallel interface 40 Chip enable (CE) signal line 42 Command latch enable (CLE) signal line 44 Address latch enable (ALE) signal line 46 Write enable (WE) signal line 48 Read enable (RE) signal line 50 Parallel I / O (P_I / O) signal line

Claims (9)

In a flash memory system that provides a storage area for a host system,
A plurality of flash memory modules;
Connected to said plurality of flash memory modules, and a flash memory controller that relays and controlling communication between the host system and the plurality of flash memory modules,
Each of the flash memory modules
A plurality of flash memories each having a predetermined parallel interface;
A serial-parallel conversion circuit connected to the flash memory controller via a predetermined serial interface and connected to the plurality of flash memories via the parallel interface;
The serial-parallel conversion circuit is:
Instruction information and user data in the serial signal format for the flash memory are transferred to the flash memory controller via the serial interface,
Instruction information and user data in parallel signal format for the flash memory are transferred to and from the flash memory via the parallel interface, and instruction information and user data in serial signal format for the flash memory and the flash memory The signal format conversion between the parallel signal format instruction information and user data is performed.
Flash memory system. The flash memory system according to claim 1.
A flash memory system, wherein the number of flash memory modules connected to the flash memory controller is variable. The flash memory system according to claim 1 or 2,
A flash memory system, wherein each flash memory module is configured as one module or one package, and the number of flash memories connected to the serial-parallel conversion circuit is a constant value. The flash memory system according to claim 1.
The serial interface has one serial input / output signal line,
The flash memory system, wherein the serial / parallel conversion circuit and the flash memory controller sequentially transfer instruction information and user data in a serial signal format to the flash memory through the serial input / output signal line. The flash memory system according to claim 4.
The serial / parallel conversion circuit and the flash memory controller are configured to send not only serial signal format instruction information and user data to the flash memory but also serial signal format instructions to the serial / parallel conversion circuit through the serial input / output signal line. A flash memory system that also transfers information sequentially. The flash memory system according to claim 5, wherein
The serial interface further includes one command signal line,
The serial / parallel conversion circuit and the flash memory controller are configured to send a command signal indicating whether or not a serial signal transferred through the serial input / output signal line is instruction information for the serial / parallel conversion circuit through the command signal line. Transfer the flash memory system. The flash memory system according to claim 5 or 6,
The parallel interface includes a plurality of parallel input / output signal lines for sequentially transferring instruction information and user data in a parallel signal format for the flash memory, and a plurality for transferring a plurality of types of control signals for the flash memory. Control signal lines,
The serial-to-parallel converter circuit is configured to provide instruction information for the flash memory transferred through the parallel interface, a user, A flash memory system that manipulates data and control signals. The flash memory system according to claim 7, wherein
The instruction information for the serial / parallel conversion circuit includes the following four types of signals:
(1) An address identification signal for instructing to supply the subsequent serial signal as an address to the flash memory,
(2) A command identification signal for instructing to supply a serial signal subsequent thereto as a command to the flash memory,
(3) a data identification signal instructing to supply the subsequent serial signal as user data to the flash memory, and (4) operating a predetermined control signal for the flash memory to obtain user data from the flash memory. Read identification signal that instructs reading
Including flash memory system. The flash memory module for incorporation into a flash memory system according to claim 1.

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