JP2012018639A - Memory system and nonvolatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To restrict fluctuation of load capacity due to changes in the number of connected chips.SOLUTION: A parallel-operating element 10a comprises: chips 0-7 each of which has a first port 121 and a second port 122 for transmitting and receiving each IO signal, and a transfer system that transfers the IO signal received at the first port 121 to the second port 122 and transfers the IO signal received at the second port 122 to the first port 121; and one or more transfer paths that connect the first port 121 and the second port 122 in a 1:1 manner to transfer the IO signal between two chips. A transfer route of the IO signal having a daisy chain shape which begins with a chip 0, in which a first IO pin 202 provided to a controller and the first port 121 are connected to each other in a 1:1 manner, is formed.

Description

  The present invention relates to a memory system and a nonvolatile semiconductor memory.

  As an external storage device used in a computer system, an SSD (Solid State Drive) has attracted attention as a memory system equipped with a flash memory (flash EEPROM). The flash memory has advantages such as high speed and light weight compared with the magnetic disk device.

  The SSD includes a plurality of flash memory chips, a controller that performs read / write control of each flash memory chip in response to a request from the host device, and a buffer that performs data transfer between each flash memory chip and the host device. A memory, a power supply circuit, a connection interface for a host device, and the like are provided (for example, Patent Document 1).

Japanese Patent No. 3688835 Japanese Patent Laid-Open No. 11-120075 Japanese Patent Application No. 2008-162281

  An object of the present invention is to provide a memory system and a non-volatile semiconductor memory in which a change in load capacity according to a change in the number of connected chips is suppressed.

  According to an aspect of the present invention, a nonvolatile semiconductor memory array, one first port and one or more second ports for transmitting and receiving an IO signal for accessing the semiconductor memory array, and the first A plurality of memory chips each including a transfer system for transferring an IO signal received at one port to the second port and transferring an IO signal received at the second port to the first port; and the first port; One or more transfer paths that transfer the IO signal between two memory chips by connecting the second ports in a one-to-one relationship, wherein the plurality of memory chips and the transfer paths are the plurality of memory chips. A nonvolatile semiconductor memory forming a tree-like or daisy-chain-like IO signal transfer path with one of them as a head, and a first port provided in the head memory chip And a controller that transmits / receives an IO signal to / from each memory chip included in the nonvolatile semiconductor memory via the controller port. A system is provided.

  According to one aspect of the present invention, a non-volatile semiconductor memory array, one first port and one or more second ports for transmitting and receiving an IO signal for accessing the semiconductor memory array, and A plurality of memory chips each including a transfer system for transferring an IO signal received at the first port to the second port and transferring an IO signal received at the second port to the first port; And one or more transfer paths for transferring IO signals between the two memory chips by connecting the ports and the second ports in a one-to-one relationship, wherein the plurality of memory chips and the transfer paths are the plurality of the plurality of transfer paths. A tree-shaped or daisy-chained IO signal transfer path starting from one of the memory chips is formed, and the first port included in the leading memory chip includes the plurality of memories The Tsu controller for transmitting and receiving respectively and IO signals flop comprises IO signal controller port and is one-to-one connection for transmitting and receiving, the non-volatile semiconductor memory is provided, characterized in that.

  According to the present invention, there is an effect that it is possible to suppress a change in load capacity according to a change in the number of connected chips.

FIG. 1 is a diagram illustrating a configuration example of an SSD (Solid State Drive). FIG. 2 is a diagram for explaining the connection between the drive control circuit and the NAND memory. FIG. 3 is a diagram illustrating a connection method according to a comparative example. FIG. 4 is a timing chart for explaining the data capture timing. FIG. 5 is a diagram for explaining a connection method according to the first embodiment. FIG. 6 is a diagram illustrating the configuration of the chip according to the first embodiment. FIG. 7 is a diagram illustrating the function of the chip control unit. FIG. 8 is a flowchart for explaining the operation of the chip controller. FIG. 9 is a flowchart for explaining the operation of the chip controller during the read process. FIG. 10 is a flowchart for explaining the operation of the chip controller during the write process. FIG. 11 is a diagram illustrating a configuration of a NAND control unit for taking in read data. FIG. 12 is a timing chart illustrating the read process. FIG. 13 is a timing chart for explaining the write processing. FIG. 14 is a diagram for explaining the configuration of a chip according to the second embodiment. FIG. 15 is a diagram illustrating the configuration of the skew adjustment circuit. FIG. 16 is a timing chart illustrating the read processing according to the second embodiment. FIG. 17 is a diagram for explaining a connection method according to the third embodiment. FIG. 18 is a diagram for explaining the configuration of a Chip that is centrally connected. FIG. 19 is a diagram illustrating the function of the chip control unit. FIG. 20 is a flowchart for explaining the operation of the chip controller during the read process.

  When designing an SSD, it is necessary to use a Stack product in which a plurality of memory chips are stacked (stacked) in order to increase the data capacity in a limited number of Pins and mounting areas of a controller chip. In such a Stack product, the IO signal lines and the control signal lines are gathered inside the number of memory chips, and the load capacity of each signal line increases with the number of stacked memory chips.

  When the load capacity of each signal line becomes large, a delay due to the CR delay of the IO signal and the control signal occurs. When a synchronously designed controller is used, the read data from the memory is latched at a low load (number of stacks: small). Although it can be output, at high load (number of stacks: many), there is a possibility that the data read from the memory is delayed due to the CR delay and cannot be latched and output. Similarly, when the load capacity of each signal line increases, there is a possibility that a write error to the memory may occur due to signal delay.

  Exemplary embodiments of a memory system and a nonvolatile semiconductor memory will be explained below in detail with reference to the accompanying drawings. Note that the present invention is not limited to these embodiments.

(First embodiment)
As an example of the memory system, an SSD (Solid State Drive) that is used as a secondary storage device of a host device such as a personal computer equipped with a NAND flash memory chip as a semiconductor memory chip will be described. One embodiment is not limited to SSD. The SSD has a function of storing data requested to be written from the host device in the NAND flash memory chip, and reading data requested to be read from the host device from the NAND flash memory chip and outputting the data to the host device.

  FIG. 1 is a diagram illustrating a configuration example of an SSD according to the first embodiment of this invention. The SSD 100 includes an ASIC and a NAND memory 10 mounted on the system board 120. The ASIC includes a drive control circuit 4, a power supply circuit 5, and a DRAM 20. Note that the DRAM 20 may be mounted outside the ASIC.

  The SSD 100 is connected to a host device 1 such as a personal computer or a CPU core via a memory connection interface such as an ATA interface (ATA I / F) 2 and functions as an external memory of the host device 1. The SSD 100 can transmit and receive data to and from the debugging device 200 via a communication interface such as an RS232C interface (RS232C I / F) 3. The SSD 100 includes a NAND flash memory (hereinafter abbreviated as “NAND memory”) 10, a drive control circuit 4 as a controller, a DRAM 20, a power supply circuit 5, a status display LED 6, and the like.

  The power supply circuit 5 generates a plurality of different internal DC power supply voltages from an external DC power supply supplied from the power supply circuit on the host device 1 side, and supplies these internal DC power supply voltages to each circuit in the SSD 100. Further, the power supply circuit 5 detects the rise of the external power supply, generates a power-on reset signal, and supplies it to the drive control circuit 4.

  The NAND memory 10 has four parallel operation elements 10a to 10d. One parallel operation element includes a plurality of stacked NAND memory chips (hereinafter referred to as “Chip”). In the example illustrated in FIG. 1, for example, the parallel operation element 10 a includes an 8 Stack package 10 a 1 in which 8 Chips 0 to 7 (for example, 1 Chip = 2 GB) are stacked and an 8 Stack package 10 a 2 in which 8 Chips 8 to 15 are stacked. Similarly, the other parallel operation elements 10b to 10d include two sets of 8Stack packages, and the NAND memory 10 has a capacity of 128 GB. The two 8Stack packages included in the parallel operation elements 10a to 10d are connected in parallel to the drive control circuit 4 through 8 channels (Ch) of 8 bits. The 8ch packages of 8ch (ch0 to ch7) can operate in parallel with each other.

  The DRAM 20 functions as a data transfer cache and work area memory between the host device 1 and the NAND memory 10. The drive control circuit 4 controls data transfer between the host device 1 and the NAND memory 10 via the DRAM 20 and controls each component in the SSD 100. In addition, the drive control circuit 4 supplies a status display signal to the status display LED 6 and receives a power-on reset signal from the power supply circuit 5 to send a reset signal and a clock signal to each part in the own circuit and the SSD 100. It also has a function to supply.

  FIG. 2 is a diagram for explaining the connection between the drive control circuit 4 and the NAND memory 10. The drive control circuit 4 includes NAND control units 210a to 210d that are four interface circuits. The first control signal pin 201, the first IO signal pin (controller port) 202, and the second control of the NAND control units 210a to 210d. The signal pin 203 and the second IO signal pin (controller port) 204 are independently connected to the parallel operation elements 10a to 10d.

  Here, in order to reduce the gate scale, one NAND control unit controls two channels. However, one NAND control unit may control one channel. Further, one NAND control unit may control three or more channels. One parallel operation element is configured to include two 8Stack packages, but the number of 8Stack packages included in one parallel operation element is not limited to two. Further, the number of stacks in each stack package is not limited to eight.

  The first IO signal pin 202 and the second IO signal pin 204 of the NAND control unit 210a are connected to the 8Stack package 10a1 and the 8Stack package 10a2, respectively, and 8-bit data, commands, and addresses are input to the IO signal pins 202 and 204, respectively. Is output. Similarly, the first control signal pin 201 and the second control signal pin 203 of the NAND control unit 210a are also connected to the 8Stack package 10a1 and the 8Stack package 10a2, respectively, and a control signal is output respectively. Similarly, the two sets of IO signal pins and control signal pins included in the other NAND control units 210b to 210d are connected to the two sets of 8Stack packages included in the parallel operation elements 10b to 10d, respectively.

  The address output from the IO signal pins 202 and 204 includes a chip address that specifies one of a plurality of connected chips. Since a technique for designating one of a plurality of Chips using a part of an address is described in detail in Patent Document 2, detailed description thereof is omitted here.

  CE (chip enable) 0 is commonly connected to the four chips (Chip 0 to 3) included in the 8Stack package 10a1 to d1. Similarly, in Chips 4 to 7, Chips 8 to 11, and Chips 12 to 15, CE1, CE2, and CE3 are commonly connected between Ch0 to 3, respectively. CE 0 to 3 select a Chip group to be operated from Chip 0 to 3, Chip 4 to 7, Chip 8 to 11, and Chip 12 to 15.

  Next, a method for connecting signal lines in the 8Stack package will be described. First, a connection method compared with the SSD according to the first embodiment of the present invention will be described. This connection method is referred to as a connection method according to a comparative example. According to the connection method according to the comparative example, each signal is branched into a plurality of signals, and the branch ends of the respective signals are connected to the respective chips.

  FIG. 3 is a diagram illustrating the connection of a chip in the 8Stack package when the connection method according to the comparative example is employed. In order to distinguish from the first embodiment of the present invention, reference numeral 20a1 is given to the 8 Stack package when the connection method according to the comparative example is adopted. Also, illustration of CE0 and CE1 is omitted here. The IO signal (first IO signal) and the control signal (first control signal) are each branched into eight, and the branch ends of the IO signal and the control signal are connected to Chips 0 to 7, respectively. That is, each signal is connected on a one-to-eight basis between the drive control circuit 4 and the chip. The control signals include a WE (write enable) signal, an RE (read enable) signal, a CLE (command latch enable) signal, an ALE (address latch enable) signal, and the like.

  Here, the load of the signal pin on the Chip side is A [pF], the load of the signal pin on the NAND control unit 210a side is B [pF], and the wiring capacitance when the number of connected chips is 2 and 8 is C [pF], respectively. , C ′ [pF], the load capacity when the number of connected chips is 2 is 2A + B + C [pF], and the load capacity when the number of connected chips is 8 is 8A + B + C ′ [pF]. As the number of connected chips increases, the wiring length also increases, so C <C ′. That is, when the connection method according to the comparative example is employed, the load capacity varies depending on the number of connected chips. Variations in load capacity cause several problems.

  For example, the signal delay increases as the signal load capacity increases. In general, the signal delay between the chip and the drive control circuit 4 varies depending on the voltage and temperature. The timing of data capture from the NAND memory 10 by the drive control circuit 4 is set in consideration of the case where the signal delay is the shortest (best condition) and the case where the delay is the longest (worst condition). FIG. 4 is a timing chart for explaining the data capture timing. Consider a case where the NAND control unit 210a outputs the RE signal to the first control signal pin 201 at the timing shown in FIG. 4B based on the internal clock of the drive control circuit 4 shown in FIG. When the chip read data output timing under the worst condition and the best condition is the timing shown in FIGS. 4C and 4D, the read data fetching is set to start two cycles after the internal clock from the beginning of the RE. Then, the read data can be sequentially fetched from the head under the best condition or the worst condition. However, when the number of connected chips is added as a variation factor of the signal delay, the difference between the worst condition and the best condition is further increased. For example, when the number of connected chips is the maximum value among the assumed values (that is, when the load capacity is maximum), the worst condition shown in FIG. 4E is obtained, and the number of connected chips is the minimum value. In some cases (that is, when the load capacity is minimum), when the best condition as shown in FIG. 4F is obtained, there is no point at which read data can be taken in either condition. Therefore, the drive control circuit 4 side needs to adjust the timing according to the load capacity variation.

  In addition, an increase in the signal load capacity causes a rounding of the signal waveform. If the load capacity becomes too large and the waveform becomes extremely sharp, the signal level does not exceed the threshold value on the receiver side and does not propagate as a signal. Therefore, on the drive control circuit 4 side, it is necessary to make changes such as changing the driving capability of the driver circuit in addition to the timing adjustment described above in accordance with the load capacitance variation.

  The main feature of the first embodiment is that a plurality of chips are connected in a daisy chain in order to reduce fluctuations in load capacity in accordance with an increase or decrease in the number of connected chips. FIG. 5 is a diagram for explaining a connection method according to the first embodiment. Each of Chips 0 to 7 has two ports (first port 121 and second port 122) for transmitting and receiving the first control signal and the first IO signal, and the signal received from one port is the other port. It is possible to transfer to other chips via. In addition, the drive control circuit 4 receives and transmits read data (read data) from any chip connected in the form of a daisy chain as a control signal and is transmitted and received together with the data, and DQS (data strobe) that controls the timing of data capture A signal has been added. As shown in the figure, the control signal and the IO signal from the NAND control unit 210a are connected only to the first port 121 provided in the chip 0 that is the first chip of the chips 0 to 7 connected in a daisy chain, and the chips 0 to 7 are Between the two chips, the first port 121 and the second port 122 are connected in a one-to-one relationship with a signal line (transfer path) for transferring an IO signal and a signal line for transferring a control signal. And a daisy chain transfer path for IO signals. That is, according to the connection method of the first embodiment, since the chip and the NAND control unit are connected one-to-one without branching the signal line, the load capacity of the signal line is equal to the number of connected chips. Regardless of the value, the value is always constant. Incidentally, if the wiring capacitance when the number of connected chips is 1 is C ″ [pF], the load capacitance is A + B + C ″ [pF], which is smaller than the case where a plurality of chips are connected by the connection method according to the comparative example. It becomes.

  FIG. 6 is a diagram for explaining the configuration of the first embodiment of each chip included in the NAND memory 10. Since Chips 0 to 15 have the same configuration, the configuration of Chip 0 included in the parallel operation element 10a will be described here as a representative. As illustrated, Chip 0 includes a first port 121, a second port 122, a chip control unit 123, a memory array 124, selectors 160 and 161, AND circuits 162 and 163, and an inverter 164. The chip controller 123, the selectors 160 and 161, the AND circuits 162 and 163, the inverter 164, and the wiring connecting these components transfer the IO signal received at the first port 121 to the second port 122, and It functions as a transfer system for transferring the IO signal received at the 2-port 122 to the first port 121.

  The memory array 124 stores write data transmitted from the NAND control unit 210a. The chip control unit 123 executes access to the memory array 124 and control of the ports 121 and 122.

  The first port 121 includes signal pins 130 and 131 for receiving the RE signal and the WE signal input from the element connected to the own port 121 (in this case, the NAND control unit 210a), and the received RE signal. , And buffers 140 and 141 for driving the WE signal, respectively. In addition, the second port 122 has signal pins 134 and 135 for transmitting the RE signal and WE signal to the elements (in this case, Chip 1) connected to the own port 122, and the RE signal and WE for transmission. Buffers 146 and 147 for driving signals are provided. The output end of the buffer 140 is connected to the input ends of the chip control unit 123 and the buffer 146. Similarly, the output end of the buffer 141 is connected to the input ends of the chip control unit 123 and the buffer 147. With this connection, the RE signal and the WE signal received from the NAND control unit 210a through the first port 121 are transmitted to the chip control unit 123 and through the second port 122, respectively. Transferred to Chip1.

  The Chip 0 includes a circuit (not shown) that is the same as the circuit for the RE signal and the WE signal as a circuit for transferring the ALE signal and the CLE signal. The ALE signal and the CLE signal are transmitted from the first port 121. The inputted ALE signal and CLE signal are sent to the chip controller 123 and sent from the second port 122 to the next chip.

  The first port 121 further includes signal pins 132 and 133 for transmitting and receiving a DQS signal and an 8-bit IO signal (IO [7: 0]) to and from the NAND control unit 210a, and the NAND control unit 210a. Buffers 143 and 145 for driving the received DQS signal and IO signal, respectively, and three-state buffers 142 and 144 for driving the DQS signal and IO signal to transmit the DQS signal and IO signal to the NAND control unit 210a, respectively. ing.

  The second port 122 includes signal pins 136 and 137 for transmitting and receiving a DQS signal and an 8-bit IO signal (IO [7: 0]) to and from Chip1, respectively, and a DQS signal and IO received from Chip1. Buffers 149 and 151 for driving the signals, and three-state buffers 148 and 150 for driving the DQS signal and the IO signal, respectively, for transmitting the DQS signal and the IO signal to Chip 1 are provided.

  The three-state buffer 142 and the buffer 143, and the three-state buffer 148 and the buffer 149 form bidirectional buffers (bidirectional buffers 152 and 154), respectively, and the chip controller 123 to the three-state buffers 142 and 148, respectively. The transmission / reception of the DQS signal can be switched in accordance with the control signal input from. Similarly, the three-state buffer 144 and the buffer 145, and the three-state buffer 150 and the buffer 151 also form bidirectional buffers (bidirectional buffers 153 and 155), respectively, and are input to the three-state buffers 144 and 150, respectively. The transmission / reception of the IO signal can be switched according to the control signal.

  The chip controller 123 outputs a control signal (direction control signal) for switching input / output of the bidirectional buffers 152 to 155. A control signal logically inverted by the inverter 164 is connected to each of the bidirectional buffers 154 and 155. When the bidirectional buffers 152 and 153 are in a state (input state) that can be received from the NAND control unit 210a, both The bidirectional buffers 154 and 155 are ready to transmit to Chip 1 (output state). When the bidirectional buffers 152 and 153 are ready to transmit to the NAND control unit 210a (output state), the bidirectional buffers 154 and 155 are It will be in the state (input state) which can be received from.

  Specifically, the direction control signal from the chip control unit 123 branches into three, and two branch ends thereof are connected to control input ends of the three-state buffers 142 and 148, respectively. The other branch end of the direction control signal is input to the input end of the inverter 164, and the direction control signal logically inverted by the inverter 164 is further branched into two and supplied to the control input ends of the three-state buffers 144 and 150. Each is connected. Accordingly, the chip control unit 123 sets the first port 121 to the input state and the second port 122 to the output state when the direction control signal is set to Low, and sets the first port 121 to the output state when the direction control signal is set to High. The second port 122 can be in an input state.

  The output terminal of the buffer 143 is connected to the chip controller 123 and the input terminal of the AND circuit 162, and the output terminal of the AND circuit 162 is connected to the input terminal of the three-state buffer 148. The output terminal of the buffer 145 is connected to the chip controller 123 and the input terminal of the AND circuit 163, and the output terminal of the AND circuit 163 is connected to the input terminal of the three-state buffer 150. The AND circuits 162 and 163 that are connected to the three-stage buffers 148 and 150 in front of the three-state buffers 148 and 150 receive the DQS signal and the IO signal in the three-state buffers 148 and 150, respectively, at input terminals different from the input terminals. A signal (mask signal) specifying whether to transmit or mask is input from the chip control unit 123. The chip control unit 123 sets the mask signal to High, thereby transferring the DQS signal and the IO signal received from the NAND control unit 210a via the first port 121 to the Chip 1 via the second port 122 (third). Path) and the mask signal is set to Low, the path can be blocked.

  The output terminal of the DQS signal of the chip controller 123 and the output terminal of the buffer 149 are connected to the input terminal of the selector 160, respectively, and the output terminal of the selector 160 is connected to the input terminal of the three-state buffer 142. Similarly, the output end of the IO signal of the chip controller 123 and the output end of the buffer 151 are connected to the input end of the selector 161, and the output end of the selector 161 is connected to the input end of the three-state buffer 144. Yes. The selectors 160 and 161 switch input sources based on a selection signal from the chip control unit 123 (not shown). In other words, the chip control unit 123 operates a selection signal to the selectors 160 and 161, thereby transmitting a DQS signal and an IO signal from the first port 121 using the own chip as a transmission source (first route). One path can be selected from the path (second path) for transmitting the DQS signal and the IO signal received from the second port 122 from the first port 121.

  Since the output terminal of the buffer 151 is connected to the input terminal of the selector 161, the data input from the second port 122 is transferred to the first port 121 without being input to the chip controller 123. The output terminal of the buffer 149 is connected to the chip control unit 123, and the chip control unit 123 counts the DQS signal input from the second port 122. The chip controller 123 recognizes the data transfer completion timing (transmission completion timing) by counting the DQS signal to a predetermined value determined according to the size of the data input from the second port 122. .

  FIG. 7 is a diagram illustrating the function of the chip control unit 123. The chip control unit 123 includes an address decoder 125, a chip address decoder 126, and an IO controller (direction control unit) 127.

  The chip address decoder 126 determines whether or not its own Chip 0 is an access target based on the chip address included in the address received via the IO signal pin 133 of the first port 121, and selects the selector based on the determination result. Output control of selection signals 160 and 161 is executed. That is, the chip address decoder 126 functions as a selector system that selects one path from the first path and the second path in cooperation with the selector 161. The address decoder 125 decodes a portion of the received address excluding the chip address, and calculates an access position in the memory array 124 provided in the own chip. The IO controller 127 determines whether the received command is a read command or a write command, and when the received command is a read command, the reception completion timing of the read command and read address received by the first port 121 And the output control of the direction control signal based on the transmission completion timing of the read data transmitted from the first port 121. Further, the IO controller 127 functions as a mask system that cuts off / connects the third path based on the chip address in cooperation with the chip address decoder 126 and the AND circuit 163.

  Next, the operation of the chip controller 123 will be described with reference to FIGS. FIG. 8 is a flowchart for explaining the operation of the chip controller 123.

  As shown in FIG. 8, in the initial state, the IO controller 127 sets the direction control signal to Low, sets the first port 121 to the input state, sets the second port 122 to the output state, sets the mask signal to High, and AND circuits 162 and 163. The mask of the DQS signal and the IO signal is canceled (step S1). And the chip | tip control part 123 receives the address and command which were input via the 1st port 121 (step S2). Note that the command and address are input to the chip controller 123 and also transferred to the Chip 1 via the second port 122.

  When receiving the command, the IO controller 127 determines whether or not the received command is a read command (step S3). If the received command is a read command (step S3, Yes), the chip control unit 123 executes a read process (step S4). When the received command is a write command (No at Step S3), the chip control unit 123 executes a write process (Step S5). After step S4 or step S5, the process proceeds to step S2, and the IO controller 127 receives the next command.

  FIG. 9 is a flowchart for explaining in more detail the operation of the chip controller 123 during the read process. When the read process is started, the IO controller 127 determines whether or not reception of the read command and address (read address) has been completed (step S11), and waits for completion of reception (No in step S11).

  When the reception of the read command and the read address is completed (step S11, Yes), the IO controller 127 switches the direction control signal from low to high, and sets the first port 121 to the output state and the second port 122 to the input state (step). S12). Then, the chip address decoder 126 determines whether or not the read address (more specifically, the chip address included in the read address) indicates the own chip (step S13). When the read address points to the own chip (step S13, Yes), the chip address decoder 126 controls the selection signal to select the chip control unit 123 as the input source of the selectors 160 and 161 (step S14). The chip controller 123 reads the read data from the memory array 124, transmits the read data through the IO signal pin 133 of the first port 121, and simultaneously transmits a DQS signal for capturing the read data to the first port 121. Is transmitted via the DQS signal pin 132 (step S15). When the transmission of the read data is completed, the IO controller 127 switches the first port 121 to the input state and the second port 122 to the output state by setting the direction control signal to Low (step S16), and completes the read process.

  In step S13, when the read address does not point to the own chip (No in step S13), the chip address decoder 126 controls the selection signal to input from the second port 122 as the input source of the selectors 160 and 161. Select (step S17). When the DQS signal is input together with the read data from the second port 122, the IO controller 127 counts the input DQS signal to a predetermined value at which the read data transfer is completed (step S18). When completing the counting of the DQS signal, the IO controller 127 proceeds to step S16 and switches the direction control signal.

  In this way, each chip transmits read data to an element connected to the first port 121 when the read address points to its own chip, and the second address when the read address does not point to its own chip. Read data sent from the element connected to the port 122 can be transferred to the element connected to the first port 121.

  FIG. 10 is a flowchart for explaining in more detail the operation of the chip control unit 123 during the write process. When the write process is started, the IO controller 127 determines whether or not reception of the write command and address (write address) has been completed (step S21), and waits for completion of reception (No in step S21).

  When reception of the write command and the write address is completed (step S21, Yes), the chip address decoder 126 determines whether or not the write address points to the own chip (step S22). If the write address does not point to the own chip (step S22, No), the write process is completed.

  When the write address points to the own chip (step S22, Yes), the IO controller 127 switches the mask signal from High to Low so that later received write data and DQS signal are not propagated to Chip1 (Step S22). S23). Then, the chip controller 123 receives the write data together with the DQS signal, and writes the received write data to the memory array 124 (step S24). When the writing of the write data is completed, the IO controller 127 switches the mask signal from Low to High (Step S25) and completes the write process.

  In this way, each chip prevents the write data from being transferred to the subsequent chip when the write address points to its own chip, so that the power consumption due to the toggle of the IO cell can be reduced. Waste can be saved.

  Next, with reference to FIGS. 11 to 13, a description will be given of how the read data can be taken in without adjusting the timing on the drive control circuit 4 side even if the number of connected chips changes. FIG. 11 is a diagram illustrating a configuration of a NAND control unit for taking in read data.

  In FIG. 11, the NAND controller 210a will be described as a representative of the NAND controllers 210a to 210d. Data input to the first IO signal pin 202 is input to each of the latch circuit 206 and the latch circuit 207 via a buffer. The DQS signal input to the first control signal pin 201 is input to the latch circuit 206 and the latch circuit 207 via the buffer and delay circuit 205, respectively. The latch circuit 206 rises the input DQS signal, and the latch circuit Reference numeral 207 latches and outputs data using the falling edge of the input DQS signal as a trigger. Data output from the latch circuits 206 and 207 are input to different input terminals of the selector 208. The selector 208 selects an input source of data input using the DQS signal output from the delay circuit 205 as a selection signal. The selector 208 transmits data from the selected input source to the ASIC. With this configuration, the NAND control unit 210a can capture data using both edges of the DQS signal as triggers. Note that the NAND control unit 210a can capture data input from the second IO signal pin 204 using both edges of the DQS signal input from the second control signal pin 203 as a trigger.

  FIG. 12 is a timing chart illustrating the read process. (A) is the internal clock of the drive control circuit 4, (b) is the output of the WE signal, (c) is the output of the RE signal, (d) is the output of the DQS signal from the Chip indicated by the read address, (e) The input / output of the Chip IO signal indicated by the read address, (f) is the direction control signal inside the Chip, (g) is the DQS signal input to the latch circuits 206 and 207 of the NAND control unit, and (h) the latch circuit 207 The timing of output data and (i) output data of the latch circuit 206 are shown.

  As shown in the figure, when the chip indicated by the read address receives the read command (read command 1 and read command 2) output in synchronization with the WE signal and the read address, the direction control signal is switched from low to high. The first port 121 is set to the output state, and the second port 122 is set to the input state. When the chip completes outputting the read data (D0 to Dn), the chip switches the direction control signal from High to Low (timing 1), and sets the first port 121 to the input state and the second port 122 to the output state. In the chip located on the read data transfer path, switching from high to low is executed when the count of the DQS signal is completed (timing 2).

  Further, the Chip outputs a DQS signal delayed by tDQSD after the RE signal is output, and outputs read data delayed by a skew tDSQ from this DQS signal. In the NAND control unit, the transmitted DQS signal is delayed by the setup of the latch circuits 206 and 207 by the delay circuit 205 and input to the latch circuits 206 and 207, respectively. The data output by the chip is taken by using the delayed DQS signal as a trigger.

  FIG. 13 is a timing chart for explaining the write processing. (A) is the internal clock of the drive control circuit 4, (b) is the output of the WE signal, (c) is the output of the RE signal, (d) is the output of the DQS signal of the NAND controller, and (e) is the write address. The input / output of the Chip IO signal indicated, (f) indicates the timing of the mask signal inside the Chip indicated by the write address. As shown in the figure, when the chip indicated by the write address receives the write command and write address sent together with the WE signal, the mask signal is switched from High to Low and the DQS signal and write data ( D0 to Dn) are not transferred to subsequent Chips. The Chip indicated by the write address switches the mask signal from Low to High when the count of the DQS signal is completed. For a Chip whose write address is not shown, the mask signal is always High (not shown).

  As a technique similar to the first embodiment, Patent Document 3 is provided with a bus switch that switches connection of signal lines between a controller and a plurality of memory chips, and connects memory chips to be accessed. A technology for reducing the load capacity of a signal line at the time of accessing a memory is disclosed. However, according to the technique of Patent Document 3, when a plurality of Chips are branched and connected after the bus switch, the load capacity changes according to the number of Chips that are branched and connected. On the other hand, according to the first embodiment, the head chip is connected without branching the signal lines, and one or more chips are connected to the head chip in a daisy chain. The load capacity can always be constant regardless of the number of chips.

  As described above, according to the first embodiment of the present invention, the parallel operation elements 10a to 10d have one first port 121 for transmitting and receiving an IO signal for accessing the memory array 124, and A transfer system (chip control unit 123) that transfers an IO signal received at one second port 122 and the first port 121 to the second port 122, and transfers an IO signal received at the second port 122 to the first port 121. , Selectors 160 and 161, AND circuits 162 and 163, inverter 164, and wiring connecting these components), and Chip 1 to 7, and the first port 121 and the second port 122 are connected one-to-one. And one or more transfer paths for transferring IO signals between the two memory chips, and in a daisy chain shape with Chip 0 as the head Since the O signal transfer path is formed and the IO signal pin 202 provided in the drive control circuit 4 is connected to the first port 121 provided in the Chip 0 on a one-to-one basis, the IO signal pin 202 is connected to the number of connected chips. Regardless, since it is connected to one Chip on a one-to-one basis, it is possible to suppress fluctuations in load capacity according to changes in the number of connected Chips.

  The first port 121 and the second port 122 are provided with bidirectional buffers 153 and 155 for switching the transmission direction, respectively, and the chip control unit 123 completes reception of the read command and read address received by the first port 121. Since the IO controller 127 for switching the transmission direction of the bidirectional buffers 153 and 155 based on the timing and the transmission completion timing of the read data transmitted from the first port 121 is provided, the IO signal of the bidirectional IO signal line The transmission direction can be switched.

  Further, based on the chip address, the first path for transmitting read data read from the memory array 124 included in the own chip from the first port 121 and the read data received by the second port 122 are transmitted from the first port 121. Since the selector system (chip address decoder 126, selector 161) for selecting one of the two paths is provided, any chip connected in the form of a daisy chain can read data from the own chip and other chips. Transfer of the read data transferred from to the drive control circuit 4 can be executed.

  In addition, since each chip is configured to transmit the read data read from the memory array 124 included in its own chip from the first port 121 together with the data strobe signal, the drive control circuit 4 can change the number of connected chips. The read data can be taken in without adjusting the timing.

  Further, based on the chip address, a mask system (IO controller 127, chip address decoder 126, AND circuit 163 that blocks / connects the third path for transmitting the write data received from the first port 121 from the second port 122) ), The unnecessary transfer of the IO signal to the subsequent chip can be omitted, so that the power consumption can be reduced as compared with the case where the mask system is not provided.

(Second Embodiment)
In the first embodiment, since there is no circuit for synchronizing the read data and the DQS signal in the transfer path of the read data and the DQS signal from the tail end of the connection Chip to the NAND control unit, the read data and the DQS Each time a signal is transferred between chips, the skew between the read data and the DQS signal accumulates. Thus, in the second embodiment, the skew between the read data and the DQS signal is accumulated by latching and outputting the DQS signal and the read data input from the second port with the DQS signal. To prevent.

  The SSD of the second embodiment is different from the first embodiment in the internal configuration of the chip. FIG. 14 is a diagram for explaining the configuration of a chip according to the second embodiment. In addition, the same code | symbol as 1st Embodiment is attached | subjected to the component equivalent to 1st Embodiment, and detailed description is abbreviate | omitted.

  As shown in the figure, Chip (here, Chip 0 is representative) includes a first port 121, a second port 122, a chip control unit 123, a memory array 124, selectors 160 and 161, AND circuits 162 and 163, an inverter 164, and a skew. An adjustment circuit 301 is provided. The first port 121 includes signal pins 130 to 133, buffers 140, 141, 143, and 145, and three-state buffers 142 and 144. The second port 122 includes signal pins 134 to 137 and buffers 146, 147. 149, 151 and three-state buffers 148, 150. Thus, the chip of the second embodiment has a configuration in which the skew adjustment circuit 301 is added to the configuration of the first embodiment.

  The skew adjustment circuit 301 receives the DQS signal from the buffer 149 and the input of the IO signal (data) from the buffer 151, eliminates the skew between the received DQS signal and the IO signal, and performs IO after the skew is eliminated. The signal is output to the input terminal of the selector 161, and the DQS signal after skew is output to the input terminal of the selector 160.

  FIG. 15 is a diagram for explaining the configuration of the skew adjustment circuit 301. As shown in the figure, the data input to the skew adjustment circuit 301 is input to each of the latch circuit 303 and the latch circuit 304. The DQS signal from the buffer 149 is input to the latch circuit 303 and the latch circuit 303 via the delay circuit 302, the latch circuit 303 rises the input DQS signal, and the latch circuit 304 outputs the input DQS signal. Data is latched and output using the falling as a trigger. Data output from the latch circuits 303 and 304 is input to different input terminals of the selector 305. The selector 305 uses the DQS signal output from the delay circuit 302 as a selection signal to select one of the latch circuits 303 and 304 that are the input sources of the input data. The selector 305 transmits data from the selected input source to the selector 161. Further, the DQS signal used as the selector signal of the selector 305 is input to the input terminal of the selector 160. With this configuration, the skew adjustment circuit 301 can eliminate the skew between the read data and the DQS signal and output the skew.

  FIG. 16 is a timing chart illustrating the read processing according to the second embodiment. Here, assuming that a read command for reading a Chip other than Chip 0 is issued, the operation timing related to Chip 0 and Chip 1 will be described.

  (A) is the output of the Chip 1 DQS signal, (b) is the input / output of the Chip 1 IO signal, (c) is the DQS signal input to the latch circuits 206 and 207, and (d) is the output of the Chip 0 latch circuit 207. (E) shows the output data of the latch circuit 206, (f) shows the output of the DQS signal of Chip0, and (g) shows the input / output timing of the IO signal of Chip0.

  As shown in the figure, the DQS signal transmitted from the Chip 1 is input to the Chip 1 latch circuits 206 and 207 after being delayed by the setup of the latch circuits 206 and 207 by the delay circuit 205. Respectively output the input data by using the delayed DQS signal as a trigger. The delayed DQS signal is output together with the outputs of the latch circuits 206 and 207.

  As described above, according to the second embodiment of the present invention, each chip transmits read data from the memory array 124 included in its own chip from the first port 121 in synchronization with the DQS signal. Since the read data received at the second port 122 is acquired in synchronization with the DQS signal and the acquired read data is transmitted from the first port 121, the skew adjustment circuit 301 is provided as a latch circuit. The Chip can eliminate the skew between the transferred read data and the DQS signal, and can prevent the accumulation of the skew between the read data and the DQS signal.

  In the second embodiment, the configuration relating to the transfer of the DQS signal may be omitted, and the skew adjustment circuit 301 may be configured to latch and output the read data with the RE signal instead of the DQS signal. It is. In that case, since the RE signal and the read data can be synchronized in each chip, the data fetch timing in the drive control circuit 4 compared to the case where the chip without the skew adjustment circuit 301 is simply connected in the form of a daisy chain. Setting is easy. For example, the drive control circuit 4 may issue the RE signal a number of times corresponding to the connection position of the chip to be read, and use the RE signal as a timing signal for taking in read data.

(Third embodiment)
In the first and second embodiments, each Chip has two ports, and each Chip is connected in a daisy chain using two ports. In the third embodiment, a Chip having three or more ports is prepared and can be connected in a tree shape using the Chip.

  FIG. 17 is a diagram for explaining connection of signal lines in the 8Stack package in which the connection method of the third embodiment is adopted. Here, in order to distinguish from the first and second embodiments, the reference numeral 30a1 is assigned to the 8Stack package of the third embodiment. As shown in the figure, Chip0 has four ports (first port 121, second port 122, third port 400, and fourth port 401), and the second port 122, third port 400, and fourth port 401 have Chip1. , Chip4, and Chip6 first ports 121 are connected to each other. In the Chip0, the IO signal received by the first port 121 is transferred to the second port 122, the third port 400, and the fourth port 401, and the second port 122, the third port 400, and the fourth port 401 are transferred. The IO signal received at the port 401 is transferred to the first port 121. Chips 1 to 7 have the same configuration as that of the first or second embodiment, and Chip 2 and Chip 3 are connected in a daisy chain to Chip 1, and Chip 5 and Chip 7 are daisy chained to Chip 4 and Chip 6, respectively. It is connected. In this way, Chips 0 to 7 are connected in a tree shape with Chip 0 as the head.

  FIG. 18 is a diagram for explaining the configuration of Chip 0 that is centrally connected. The configuration related to the transfer of the RE signal, WE signal, DQS signal, and IO signal from the first port 121 to the second port 122, the third port 400, and the fourth port 401 is the same as that of the first or second embodiment. This is the same as the configuration related to the transfer of each signal from the first port 121 to the second port 122 in the embodiment, and illustration and detailed description thereof are omitted. The same components as those in the first embodiment are denoted by the same reference numerals as those in the first embodiment, and detailed description thereof is omitted.

  As illustrated in FIG. 18, the Chip 0 includes a first port 121, a second port 122, a third port 400, a fourth port 401, a chip control unit 402, a memory array 124, and selectors 403 and 404. The third port 400 includes signal pins 405 and 406 for transmitting and receiving DQS signals and IO signals, and buffers 409 and 410 for driving the received DQS signals and IO signals, respectively. Similarly, the fourth port 401 includes signal pins 407 and 408 for transmitting and receiving DQS signals and IO signals, and buffers 411 and 412 for driving received DQS signals and IO signals, respectively.

  The DQS signals from the second port 122, the third port 400, and the fourth port 401 are input to the chip control unit 402 and input to different input terminals of the selector 403, respectively. In addition, IO signals from the second port 122, the third port 400, and the fourth port 401 are input to different input terminals of the selector 404, respectively. The selectors 403 and 404 select the input source based on the selection signal from the chip control unit 402 and input each signal from the selected input source to the input terminals of the three-state buffers 142 and 144, respectively.

  FIG. 19 is a diagram illustrating the function of the chip control unit 402. As illustrated, the chip controller 402 includes an address decoder 125, a chip address decoder 420, and an IO controller 127. The chip address decoder 420 stores a chip address information storage unit 421 that stores chip address information 422 that is a correspondence between the chip addresses of Chips 1 to 7 and the port that receives the read data whose source is the Chip specified by the chip address. Based on the chip address received from the NAND control unit and the chip address information 422, output control of the selection signals of the selectors 403 and 404 is executed. According to the chip address information 422, for example, Chip 1 to 3 are associated with the second port 122, Chip 4 and Chip 5 are associated with the third port 400, and Chip 6 and Chip 7 are associated with the fourth port 401. The chip address information storage unit 421 may be a small-scale memory or a fuse, for example.

  Next, the operation of the chip controller 402 will be described. Here, only the operation at the time of read processing different from the chip control unit 123 of the first embodiment will be described. FIG. 20 is a flowchart for explaining the operation of the chip controller 402 during read processing.

  As shown in the figure, the chip control unit 402 executes operations equivalent to the chip control unit 123 in step S11 and step S12 in steps S31 and S32, respectively. After step S32, the chip address decoder 420 determines whether or not the read address points to the own chip. If the read address points to the own chip (step S23, Yes), the selection signal is controlled to select the selector. The chip controller 402 is selected as an input source of 403 and 404 (step S34). In step S35 and step S36, the chip control unit 402 executes the same operation as that of the chip control unit 123 in step S15 and step S16, and ends the read process.

  In step S33, when the read address does not point to the own chip (step S33, No), the chip address decoder 420 refers to the chip address information 422 and corresponds to the chip address included in the selector 403, 404 by the read address. The input from the attached port is selected (step S37). When the DQS signal is input together with the read data from the selected port, the IO controller 127 counts the input DQS signal to a predetermined value at which the transfer of the read data is completed (step S38). When the IO controller 127 counts the DQS signal until it reaches a value corresponding to the data size of the read data, the IO controller 127 proceeds to step S36 to switch the direction control signal and ends the read process.

  Thus, according to the third embodiment of the present invention, the Chip is designated by a plurality of second ports (second port 122, third port 400, fourth port 401), chip address and chip address. A chip address information storage unit 421 that stores chip address information 422 that associates a second port that receives read data that is a transmission source of the memory chip to be transmitted, and a selector system (chip address decoder 420, selector 404), Since the route is selected based on the chip address and the chip address information 422, a plurality of chips can be connected in a tree shape.

  1 host device, 4 drive control circuit, 10 NAND memory, 10a to d, 30a parallel operation element, 100 SSD, 121 first port, 122 second port, 123, 402 chip control unit, 124 memory array, 125 address decoder, 126, 420 Chip address decoder, 127 IO controller, 152-155 bidirectional buffer, 160, 161, 208, 403, 404, 305 selector, 162, 163 AND circuit, 164 inverter, 201 first control signal pin, 202 first IO Signal pin, 203 second control signal pin, 204 second IO signal pin, 205, 302 delay circuit, 206, 207, 303, 304 latch circuit, 210a-d NAND control unit, 301 skew adjustment circuit, 400 third port, 01 the fourth port, 421 chip address information storage unit, 422 chip address information.

Claims (8)

A non-volatile semiconductor memory array, one first port and one or more second ports for transmitting / receiving an IO signal related to access to the semiconductor memory array, and an IO signal received at the first port A plurality of memory chips each having a transfer system for transferring to the second port and transferring the IO signal received by the second port to the first port, and the first port and the second port on a one-to-one basis One or more transfer paths for connecting and transferring IO signals between the two memory chips, and the plurality of memory chips and the transfer path are headed by one of the plurality of memory chips. A non-volatile semiconductor memory forming a tree-like or daisy-chain-like IO signal transfer path;
A controller that has a controller port that is connected to the first port of the first memory chip in a one-to-one relationship, and that transmits and receives IO signals to and from the memory chips of the nonvolatile semiconductor memory via the controller port. When,
A memory system comprising: The IO signal includes a read request and a read request destination address from which the controller is a transmission source, read data from which a memory chip specified by the read request destination address is a transmission source and the controller is a transmission destination, Including
The first port and the second port each include a bidirectional buffer for switching the transmission direction,
The transfer system determines the transmission direction of the bidirectional buffer based on the reception completion timing of the read request and the read request destination address received at the first port and the transmission completion timing of the read data transmitted from the first port. A direction control unit for switching,
The memory system according to claim 1. The read request destination address includes a chip address that specifies a memory chip of a read request destination,
The transfer system is
Based on the chip address, a first path for transmitting read data read from the semiconductor memory array included in the self-memory chip from the first port and a first path for transmitting read data received by the second port from the first port. A selector system for selecting one of the two paths;
The memory system according to claim 2. One or more memory chips of the plurality of memory chips are:
A plurality of said second ports;
A chip address information storage unit that stores chip address information that associates each chip port with a second port that receives read data whose source is a memory chip specified by the chip address;
With
The selector system selects one path based on the chip address and the chip address information.
The memory system according to claim 3. Each of the plurality of memory chips is
Read data read from the semiconductor memory array provided in its own memory chip is transmitted from the first port in synchronization with a timing signal for the controller to capture the read data,
A skew adjustment circuit for acquiring the read data received at the second port in synchronization with the timing signal, and transmitting the acquired read data from the first port;
The memory system according to claim 2, wherein the memory system is a memory system.   5. The memory device according to claim 2, wherein each of the plurality of memory chips transmits read data read from a semiconductor memory array included in the memory chip from the first port together with a data strobe signal. The memory system according to one item. The IO signal includes a write request from which the controller is a transmission source, a write request destination address, and write data transmitted after the write request and the write request destination address,
The write request destination address includes a chip address that designates a memory chip of the write request destination,
The transfer system is
A mask system for blocking / connecting a third path for transmitting write data to be received from the second port from the second port based on the chip address;
The memory system according to claim 1. A non-volatile semiconductor memory array, one first port and one or more second ports for transmitting / receiving an IO signal related to access to the semiconductor memory array, and an IO signal received at the first port A plurality of memory chips each comprising a transfer system for transferring to the second port and transferring the IO signal received by the second port to the first port;
One or more transfer paths for connecting the first port and the second port in a one-to-one connection and transferring an IO signal between two memory chips;
With
The plurality of memory chips and the transfer path form a tree-shaped or daisy-chain-shaped IO signal transfer path starting from one of the plurality of memory chips,
The first port included in the top memory chip is connected to the controller port for transmitting and receiving the IO signal included in the controller that transmits and receives the IO signal to and from each of the plurality of memory chips.
A non-volatile semiconductor memory.

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