CN100397380C - Multi-channel flash memory transmission controller, chip and storage device - Google Patents
Multi-channel flash memory transmission controller, chip and storage device Download PDFInfo
- Publication number
- CN100397380C CN100397380C CNB2005101328809A CN200510132880A CN100397380C CN 100397380 C CN100397380 C CN 100397380C CN B2005101328809 A CNB2005101328809 A CN B2005101328809A CN 200510132880 A CN200510132880 A CN 200510132880A CN 100397380 C CN100397380 C CN 100397380C
- Authority
- CN
- China
- Prior art keywords
- flash memory
- bus
- control
- control module
- flash memories
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 230000015654 memory Effects 0.000 title claims abstract description 98
- 230000005540 biological transmission Effects 0.000 title claims abstract description 34
- 230000000694 effects Effects 0.000 claims description 5
- 230000006870 function Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 2
- 244000233952 Polygonum bistorta Species 0.000 description 1
- 230000006399 behavior Effects 0.000 description 1
- 230000008676 import Effects 0.000 description 1
- 230000005055 memory storage Effects 0.000 description 1
Images
Abstract
The present invention discloses a multichannel flash memory transmission controller, a chip which comprises the controller and a storage device. The controller comprises a main control state machine, a control bus control unit and a data bus control unit, wherein the main control state machine controls the control bus control unit to emit control signals to a plurality of flash memories by a group of multiplex control buses; state signals of a plurality of flash memories can input into the control bus control unit by the multiplex control buses in a wired mode; the control bus control unit can return the state signals after wired to the main control state machine; under the condition that the state signals after wired are effective, the flash memories can simultaneously transfer data with the data bus control unit by a plurality of groups of independent data buses under the function of the control signals. The read-write speed of the flash memories can be largely enhanced by the present invention.
Description
Technical field
The present invention relates to a kind of storage medium management devices, in particular to the flash memory management device; More specifically, relate to a kind of multi-channel flash memory transmission controller and comprise the chip and the memory device of this controller.
Background technology
As the main storage medium of USB flash disk, the transmission speed of Sheffer stroke gate flash memory (Nand Flash) itself is not high, moreover the operations such as reading and writing of flash memory are also needed the extra stand-by period.So in the high speed USB flash disk was used, in order to improve the transmission speed of USB flash disk, state-of-the-art technology was to adopt the binary channels transmission mechanism.
The transmission of binary channels transmission mechanism and single channel is similar, and it is equivalent to have two independent single channels, and each passage all has one group of independently data address instruction bus and one group control bus independently.The binary channels transmission mechanism is controlled two flash reading and writings simultaneously, thereby transmission speed is doubled.Under the situation of using flash memory, the binary channels transmission mechanism can reach the reading speed of 20MB/s and the writing speed of 12MB/s, and wherein, the difference of read or write speed comes from the difference of flash reading and writing additional wait time.
In the application of USB flash disk, raising speed and capacity are fundamental purposes.Because the definition of USBmass-storage Class bulk-only agreement, read-write can not take place simultaneously, and the read or write speed that the USB2.0 agreement is supported is all up to 480Mbps.The part of deduction usb protocol expense, actual read or write speed are also all up to nearly 48MB/s, and therefore, the read or write speed of existing binary channels transmission mechanism is the bottleneck that USB flash disk speed improves.
Summary of the invention
At the problems referred to above, the objective of the invention is to, a kind of hyperchannel such as four-way flash memory high-speed transfer scheme are provided, thereby improve the read or write speed of flash memory.
According to a first aspect of the invention, a kind of multi-channel flash memory transmission controller is provided, described controller comprises the major state machine, control bus control module and data bus control module, the major state machine is controlled described control bus control module and is transmitted control signal to a plurality of flash memories by one group of multiplexing control bus, the status signal of a plurality of flash memories is imported the control bus control module with line and mode by multiplexing control bus, described control bus control module to the major state machine line of return with after status signal, online with after the effective situation of status signal under, a plurality of flash memories transmit data with the data bus control module simultaneously by many groups independent data bus under the effect of control signal.
In first aspect, preferably, described line and mode realize like this: described a plurality of flash memory status signals link together, and link to each other with an end of a pull-up resistor, and the other end of described pull-up resistor links to each other with power supply.Further preferably, the resistance of described pull-up resistor is between 20 kilo-ohms to 30 kilo-ohms.
Preferably, described flash memory is the Sheffer stroke gate flash memory, and described data bus is a data address instruction multiplex bus; By described data address instruction multiplex bus, described major state machine is controlled described data bus control module and is sent address, command information to a plurality of Sheffer stroke gate flash memories.
Preferably, described hyperchannel is a four-way, and described a plurality of flash memories are four flash memories, and described many group independent data buses are four groups of independent data buses.
According to second aspect, a kind of chip is provided, it is characterized in that, comprise the multi-channel flash memory transmission controller described in the above-mentioned first aspect.
According to the third aspect, a kind of memory device is provided, comprise multi-channel flash memory transmission controller and a plurality of flash memory, described controller comprises the major state machine, control bus control module and data bus control module, the major state machine is controlled described control bus control module and is transmitted control signal to a plurality of flash memories by one group of multiplexing control bus, the status signal of a plurality of flash memories is imported the control bus control module with line and mode by multiplexing control bus, described control bus control module to the major state machine line of return with after status signal, online with after the effective situation of status signal under, a plurality of flash memories transmit data with the data bus control module simultaneously by many groups independent data bus under the effect of control signal.
In the third aspect, preferably, described line and mode realize like this: described memory device comprises a pull-up resistor, and an end of described pull-up resistor links to each other with power supply, and the other end links to each other with a plurality of flash memory status signals that are connected together.Further preferably, the resistance of described pull-up resistor is between 20 kilo-ohms to 30 kilo-ohms.
Preferably, described flash memory is the Sheffer stroke gate flash memory, and described data bus is a data address instruction multiplex bus; By described data address instruction multiplex bus, the major state machine is controlled described data bus control module and is sent address, command information to a plurality of Sheffer stroke gate flash memories.
According to the present invention, because multiplexing one group of control bus, multi-channel flash memory transmission controller can be controlled a plurality of flash memories simultaneously, and data bus and a plurality of flash memory transmit data simultaneously more by organizing independently, thereby have improved the read or write speed of flash memory greatly.
Description of drawings
For understanding the present invention better, only the invention will be further described in conjunction with the accompanying drawings with an embodiment below.In the accompanying drawing:
Fig. 1 is the structured flowchart of the four-way flash memory transmission controller of one embodiment of the invention;
Fig. 2 shows the demultiplex control signal of this embodiment of the invention;
Fig. 3 reads flash memory sequence figure for this embodiment of the invention;
Fig. 4 is the flash memory management synoptic diagram of this embodiment of the invention.
Embodiment
With reference to Fig. 1, Fig. 1 is the structured flowchart of the four-way flash memory transmission controller of one embodiment of the invention.Four-way flash memory transmission controller 10 is arranged in application chip, and application chip can be used in the memory device such as USB flash disk.Controller 10 comprises major state machine 11, data bus control module 12 and control bus control module 13.By other two unit 12,13 of major state machine 11 control, other two unit 12,13 return required information to major state machine 11.For realizing the four-way transmission, in this embodiment, control bus control module 13 links to each other with four Sheffer stroke gate flash memories (hereinafter to be referred as flash memory) by one group of multiplexing control bus 14, data bus control module 12 pass through four groups separately independently data bus IO1-IO4 link to each other with four flash memories respectively.
With reference to Fig. 2, Fig. 2 shows the demultiplex control signal of this embodiment of the invention.This group demultiplex control signal comprises that instruction sends that enable signal CLE, address send enable signal ALE, chip selection signal CE, write enable signal WEN, read enable signal REN, write protect signal WP and R/B (ready/busy) (being ready to/hurry) signal.Wherein, CLE, ALE, CE, WEN, REN, WP are the output signals of controller 10, and R/B is the input signal of controller 10, and it has reflected the state of flash memory.Control bus control module 13 is being controlled the behavior of each control signal.Here, the status signal R/B1-R/B4 of four flash memories imports control bus control module 13 with line and mode.
Especially, the line that can realize signal R/B1-R/B4 in the following ways with.The status signal R/B1-R/B4 of four flash memories is linked together, again by a pull-up resistor R and power supply V
CCLink to each other, pull-up resistor R is positioned on the circuit version at application chip place.Consider and will reduce quiescent current, the resistance of pull-up resistor R can not be too little, preferably between 20 kilo-ohms to 30 kilo-ohms.Like this, according to the standard of Sheffer stroke gate flash memory, under the state of being ready to, R/B is output as high resistant, and therefore, when four signals of R/B1-R/B4 all are in when being ready to state, total R/B is drawn high to 1 by pull-up resistor R; When flash memory was in busy condition, R/B was output as 0, therefore, when any one is output as 0 among four signal R/B1-R/B4, power supply V
CCTo the path that forms between the ground by pull-up resistor R and R/B output resistance, because the output resistance of this R/B is very little, the result of dividing potential drop is that total R/B output valve is 0.Therefore, the logic between four signal R/B1-R/B4 be with relation.Like this, realize a pin of R/B1-R/B4 multiplex controller 10 by adopting line and mode, controller 10 just can learn when four flash memories all are in the state of being ready to.
Especially, for the Sheffer stroke gate flash memory, data bus is actually data address instruction multiplex bus.Referring again to Fig. 1, major state machine 11 control data bus control units 12 are to four flash memory transport addresses, command information, and read and write data to four flash memories.Elementary instruction comprises reading and writing, wipes, return to copy and read (copybackread), return and copy instructions such as writing (copybackwrite).Receive at control bus control module 13 under the situation of effective R/B signal, promptly all be in when being ready to state when four flash memories, control bus control module 13 sends control signal under 11 controls of major state machine, and data bus control module 12 transmits data with four flash memories simultaneously by four groups of data address instruction multiplex bus IO1-IO4.
Data bus control module 12 returns to major state machine 11 and reads or whether write activity is finished, control bus control module 13 to major state machine 11 lines of return with after R/B.Major state machine 11 input, the output of control bus 14 and data address instruction multiplex bus IO1-IO4 respectively according to the different operating to flash memory by these two unit controls.For example, suppose that flash memory is the little page or leaf type of Samsung, read a page or leaf from flash memory, with reference to Fig. 3, Fig. 3 reads flash memory sequence figure for this embodiment of the invention.Major state machine 11 sends read instruction (00H) by data bus control module 12 control data address instruction multiplex buss to four flash memories, is 1 by control bus control module 13 control CLE simultaneously, and CE, WEN are 0; Next, major state machine 11 sends address (A1, A2, A3) by data bus control module 12 control data address instruction multiplex buss to four flash memories, is 1 by control bus control module 13 control ALE simultaneously, and CE is 0, WEN is 0; Waiting line with after R/B return to 1 from 0, then, major state machine 11 is 0 by control bus control module 13 control REN, and control data bus control unit 12 sense data from the address specific page of four flash memories is simultaneously delivered to other unit (not shown) of application chip.
With reference to Fig. 4, Fig. 4 is the flash memory management synoptic diagram of this embodiment of the invention.The unit of flash memory storage structure is a page or leaf (page), is example with big page or leaf flash memory, and every page comprises the data field of 2kB and redundancy (spare) district of 64 bytes.These pages or leaves are divided into group, and one group of 64 pages or leaves is called as piece.According to the present invention, realized being that 8kB, redundant area are the page or leaf of 256 bytes thereby form a data field with the address same page of four flash memories and management together.And four flash memories such as are read and write, wipe simultaneously at operation, the same with flash memory of control.Like this, the four-way transmission mechanism can be regarded as the page or leaf size is become original four times, data bus figure place also becomes four times original single channel transmission mechanism.Therefore, reading and writing, the time of a page or leaf of routine operation such as wiping, can operate 4 pages or leaves simultaneously, speed is single pass 4 times, twin-channel 2 times, thereby near the maximum transmitted ability of USB2.0 agreement.
Preamble is an example with four-way Sheffer stroke gate flash memory transmission controller, the description of property that the invention has been described.In addition, the present invention also can extend to the hyperchannel transmission control to flash memories such as two, eight, 16; The present invention is not limited to the Sheffer stroke gate flash memory, such as, for the rejection gate flash memory, its data bus separates with address bus, similarly, and can a shared group address bus, one group of control bus, and adopt the multi-group data bus to realize the multi-channel data transmission.This is obvious to those skilled in the art.
Obviously, the present invention described here can have many variations, and this variation can not be thought and departs from the spirit and scope of the present invention.Therefore, the change that all it will be apparent to those skilled in the art all is included within the covering scope of these claims.
Claims (10)
1. multi-channel flash memory transmission controller, comprise the major state machine, control bus control module and data bus control module, it is characterized in that, described major state machine is controlled described control bus control module and is sent identical control signal to a plurality of flash memories simultaneously by one group of multiplexing control bus, the status signal of a plurality of flash memories is imported the control bus control module with line and mode by multiplexing control bus, described control bus control module to the major state machine line of return with after status signal, online with after the effective situation of status signal under, a plurality of flash memories transmit data with the data bus control module by many group independent data buses respectively simultaneously under the effect of described control signal.
2. multi-channel flash memory transmission controller as claimed in claim 1, it is characterized in that, described line and mode realize like this: the status signal of described a plurality of flash memories links together, and links to each other with an end of a pull-up resistor, and the other end of described pull-up resistor links to each other with power supply.
3. multi-channel flash memory transmission controller as claimed in claim 2 is characterized in that, the resistance of described pull-up resistor is between 20 kilo-ohms to 30 kilo-ohms.
4. multi-channel flash memory transmission controller as claimed in claim 1 is characterized in that, described flash memory is the Sheffer stroke gate flash memory, and described data bus is a data address instruction multiplex bus; By described data address instruction multiplex bus, described major state machine is controlled described data bus control module and is sent address, command information to described a plurality of Sheffer stroke gate flash memories.
5. multi-channel flash memory transmission controller as claimed in claim 1 is characterized in that, described hyperchannel is a four-way, and described a plurality of flash memories are four flash memories, and described many group independent data buses are four groups of independent data buses.
6. a chip is characterized in that, comprises each described multi-channel flash memory transmission controller in the claim 1 to 5.
7. memory device, comprise multi-channel flash memory transmission controller and a plurality of flash memory, described multi-channel flash memory transmission controller comprises the major state machine, control bus control module and data bus control module, it is characterized in that, described major state machine is controlled described control bus control module and is sent identical control signal to a plurality of flash memories simultaneously by one group of multiplexing control bus, the status signal of a plurality of flash memories is imported the control bus control module with line and mode by multiplexing control bus, described control bus control module to the major state machine line of return with after status signal, online with after the effective situation of status signal under, a plurality of flash memories transmit data with the data bus control module by many group independent data buses respectively simultaneously under the effect of described control signal.
8. memory device as claimed in claim 7 is characterized in that, described line and mode realize like this: described memory device comprises a pull-up resistor, and an end of described pull-up resistor links to each other with power supply, and the other end links to each other with the status signal of a plurality of flash memories that are connected together.
9. memory device as claimed in claim 8 is characterized in that, the resistance of described pull-up resistor is between 20 kilo-ohms to 30 kilo-ohms.
10. as each described memory device in the claim 7 to 9, it is characterized in that described flash memory is the Sheffer stroke gate flash memory, described data bus is a data address instruction multiplex bus; By described data address instruction multiplex bus, described major state machine control data bus control unit sends address, command information to described a plurality of Sheffer stroke gate flash memories.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101328809A CN100397380C (en) | 2005-12-27 | 2005-12-27 | Multi-channel flash memory transmission controller, chip and storage device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101328809A CN100397380C (en) | 2005-12-27 | 2005-12-27 | Multi-channel flash memory transmission controller, chip and storage device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1790308A CN1790308A (en) | 2006-06-21 |
| CN100397380C true CN100397380C (en) | 2008-06-25 |
Family
ID=36788177
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005101328809A Expired - Fee Related CN100397380C (en) | 2005-12-27 | 2005-12-27 | Multi-channel flash memory transmission controller, chip and storage device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100397380C (en) |
Families Citing this family (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100458751C (en) * | 2007-05-10 | 2009-02-04 | 忆正存储技术(深圳)有限公司 | Paralleling flash memory controller |
| CN100547566C (en) | 2007-06-28 | 2009-10-07 | 忆正存储技术(深圳)有限公司 | Control method based on multi-passage flash memory apparatus logic strip |
| CN100530138C (en) | 2007-06-28 | 2009-08-19 | 忆正存储技术(深圳)有限公司 | Self-adaptive control method based on multi-passage flash memory apparatus logic strip |
| CN101271393A (en) * | 2008-01-22 | 2008-09-24 | 孙国仲 | Portable solid-state memory |
| CN101271394A (en) * | 2008-01-22 | 2008-09-24 | 孙国仲 | Computer without hard disk |
| CN101246450B (en) * | 2008-03-26 | 2010-04-21 | 普天信息技术研究院有限公司 | Flash memory and memory space managing method thereof |
| CN101587740B (en) * | 2008-05-23 | 2011-11-30 | 承奕科技股份有限公司 | Multi-channel solid-state memory system |
| CN101740102B (en) * | 2008-11-11 | 2014-03-26 | 西安奇维测控科技有限公司 | Multi-channel flash memory chip array structure and write-in and read-out methods thereof |
| US8447917B2 (en) | 2009-06-25 | 2013-05-21 | Mediatek Inc. | Flash memory devices and methods for controlling a flash memory device |
| CN101930798B (en) * | 2009-06-25 | 2014-04-16 | 联发科技股份有限公司 | Flash memory device, memory device and method for controlling flash memory device |
| CN102054531B (en) * | 2009-11-09 | 2014-04-23 | 技嘉科技股份有限公司 | Access device and method for flash memory |
| CN102023943B (en) * | 2010-11-25 | 2013-06-19 | 杭州晟元芯片技术有限公司 | Method for controlling as well as reading and writing NandFlash by four-path IO (input-output) interface |
| CN102222055A (en) * | 2011-06-02 | 2011-10-19 | 钟浩 | Device and method for improving running speed of high-capacity solid data memory system |
| WO2013038987A1 (en) * | 2011-09-14 | 2013-03-21 | 日本電気株式会社 | Network system |
| CN104679440B (en) * | 2013-11-29 | 2017-11-10 | 深圳市国微电子有限公司 | A kind of flash memory array management method and device |
| CN111916135A (en) * | 2019-05-10 | 2020-11-10 | 北京兆易创新科技股份有限公司 | Chip |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1156280A (en) * | 1996-01-30 | 1997-08-06 | Tdk株式会社 | Flash memory system |
| US6247084B1 (en) * | 1997-10-08 | 2001-06-12 | Lsi Logic Corporation | Integrated circuit with unified memory system and dual bus architecture |
| CN1487436A (en) * | 2003-08-08 | 2004-04-07 | 华中科技大学 | Massive memory system based on multi-channel memory equipment and its control method |
| WO2004082270A1 (en) * | 2003-03-12 | 2004-09-23 | Matsushita Electric Industrial Co., Ltd. | Camera recorder and data recording medium |
| CN2676291Y (en) * | 2004-01-02 | 2005-02-02 | 创惟科技股份有限公司 | Device for increasing access efficiency of flash memory |
| WO2005069150A1 (en) * | 2004-01-20 | 2005-07-28 | Trek 2000 International Ltd. | Portable data storage device using multiple memory devices |
-
2005
- 2005-12-27 CN CNB2005101328809A patent/CN100397380C/en not_active Expired - Fee Related
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1156280A (en) * | 1996-01-30 | 1997-08-06 | Tdk株式会社 | Flash memory system |
| US6247084B1 (en) * | 1997-10-08 | 2001-06-12 | Lsi Logic Corporation | Integrated circuit with unified memory system and dual bus architecture |
| WO2004082270A1 (en) * | 2003-03-12 | 2004-09-23 | Matsushita Electric Industrial Co., Ltd. | Camera recorder and data recording medium |
| CN1487436A (en) * | 2003-08-08 | 2004-04-07 | 华中科技大学 | Massive memory system based on multi-channel memory equipment and its control method |
| CN2676291Y (en) * | 2004-01-02 | 2005-02-02 | 创惟科技股份有限公司 | Device for increasing access efficiency of flash memory |
| WO2005069150A1 (en) * | 2004-01-20 | 2005-07-28 | Trek 2000 International Ltd. | Portable data storage device using multiple memory devices |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1790308A (en) | 2006-06-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100397380C (en) | Multi-channel flash memory transmission controller, chip and storage device | |
| CN105474319B (en) | For configuring the device and method of the I/O of the memory of mixing memory module | |
| CN101384984B (en) | Portable data storage device incorporating multiple flash memory units | |
| KR100661419B1 (en) | Non-volatile semiconductor memory device and semiconductor disk apparatus | |
| CA2740511A1 (en) | A composite memory having a bridging device for connecting discrete memory devices to a system | |
| KR100875978B1 (en) | Memory card and memory system including it | |
| US9355685B2 (en) | Multi-chip package and memory system | |
| CN112130754B (en) | Parallel operation in aggregating and virtualizing solid state drives | |
| CN2911791Y (en) | Multi-channel flashmemory transmission controller, chips and memory device | |
| CN101656096A (en) | Registered dimm memory system | |
| CN110718246B (en) | Memory device | |
| CN102622191A (en) | High-speed mass storage plate | |
| CN109213687A (en) | Data storage device, memory operation method and operation instruction execution method | |
| CN115904254B (en) | Hard disk control system, method and related components | |
| KR102596491B1 (en) | Semiconductor device | |
| WO2016072007A1 (en) | Semiconductor memory device, storage system, and calculator | |
| CN100349141C (en) | Method for dynamically adjusting redundant zone of nonvolatile memory and relevant apparatus thereof | |
| CN101069165B (en) | Computer system | |
| KR100885915B1 (en) | Inter-communicating multi memory chip and system including the same | |
| CN101571790A (en) | Flash memory controller | |
| US20150039813A1 (en) | NAND Interface Capacity Extender Device For Extending Solid State Drives Capacity, Performance, And Reliability | |
| JP4760778B2 (en) | Flash memory system and flash memory module incorporated in the system | |
| CN111414314A (en) | Data storage device, operating method thereof and controller thereof | |
| KR102242957B1 (en) | High speed NAND memory system and high speed NAND memory package device | |
| JP2014149669A (en) | Semiconductor memory device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20080625 Termination date: 20111227 |