CN108932204A - A kind of multi-channel flash memory storage system - Google Patents
A kind of multi-channel flash memory storage system Download PDFInfo
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- CN108932204A CN108932204A CN201810609063.5A CN201810609063A CN108932204A CN 108932204 A CN108932204 A CN 108932204A CN 201810609063 A CN201810609063 A CN 201810609063A CN 108932204 A CN108932204 A CN 108932204A
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- Prior art keywords
- chip
- flash memory
- flash
- fpga
- storage system
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
- G06F12/0638—Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1684—Details of memory controller using multiple buses
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0022—Multibus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/16—Memory access
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Read Only Memory (AREA)
Abstract
The present invention provides a kind of multi-channel flash memory storage system, including：Multiple fpga chips, the host interface for providing fpga chip and address carry out dsp chip, multiple memory chip groups, the data/address bus, control bus, chip selection signal line of signal processing；Flash memory chip set includes multiple flash chips, and the flash chip in same flash memory chip set is connect by common data/address bus and control bus with single fpga chip；Flash chip in all flash memory chip sets is connect by independent chip selection signal line with fpga chip；Multiple fpga chips are connect with dsp chip respectively；Improve the transmission rate and whole handling capacity of flash-memory storage system.
Description
Technical field
The present invention relates to field of flash memory more particularly to a kind of multi-channel flash memory storage systems.
Background technique
For storing industry, mechanical hard disk is afraid of vibration due to intrinsic disadvantage, and rate is low, and handling capacity is small, and volume is big etc.
Many disadvantages more and more use nand flash memory storage dish in certain specific fields.In addition, with flash memory storage single-deck
Cost reduces, and flash disk is substituted mechanical hard disk by more and more producers.Flash memory disk is presented increases becoming for dosage year by year
Gesture has pushed flash disk and flash-memory storage system so more and more storage producer carries out flash memory storage research and development
Progress.But the transmission rate of current flash-memory storage system is low, handling capacity is smaller.
Summary of the invention
In order to overcome the deficiencies in the prior art described above, the present invention provides a kind of multi-channel flash memory storage system, including：It is more
A fpga chip, the host interface for providing fpga chip and address carry out dsp chip, the multiple memory cores of signal processing
Piece group, data/address bus, control bus, chip selection signal line；
Flash memory chip set includes multiple flash chips, the flash chip in same flash memory chip set by common data/address bus and
Control bus is connect with single fpga chip；
Flash chip in all flash memory chip sets is connect by independent chip selection signal line with fpga chip；
Multiple fpga chips are connect with dsp chip respectively.
Preferably, the number of flash chip is within 16 in flash memory chip set.
Preferably, the number for the flash memory chip set connecting with same fpga chip is within 8.
Preferably, the control bus of different flash memory chip set connections is mutually indepedent；
The data/address bus of different flash memory chip set connections is mutually indepedent.
Preferably, the data/address bus of same flash chip, control bus, chip selection signal line connect same fpga chip.
Preferably, fpga chip uses XC6VLX760 type fpga chip.
Preferably, dsp chip uses TMS320 series DSP chip.
As can be seen from the above technical solutions, the present invention has the following advantages that：
In the present invention, fpga chip and dsp chip are the cores of storage system, the main reception for completing control signal and are turned
The real-time functions such as generate of hair, the mapping of physical address and logical address and allocation index information.Connect with same fpga chip
The number of the flash memory chip set connect is within 8；The number of flash chip is within 16 in flash memory chip set；In single channel,
Multiple flash chip multiple programmings improve whole handling capacity；Different flash chip shared data buses, improve in single channel
Access bandwidth and transmission rate.
Detailed description of the invention
In order to illustrate more clearly of technical solution of the present invention, attached drawing needed in description will be made below simple
Ground introduction, it should be apparent that, drawings in the following description are only some embodiments of the invention, for ordinary skill
For personnel, without creative efforts, it is also possible to obtain other drawings based on these drawings.
Fig. 1 is connection relationship diagram of the present invention.
Fig. 2 is single-chip single channel design schematic diagram.
Fig. 3 is single channel multi-chip design schematic diagram.
The position Fig. 4 multichannel multi-chip design schematic diagram.
Wherein, 1, dsp chip, 2, fpga chip, 3, flash chip, 4, data/address bus, 5, control bus.
Specific embodiment
It in order to make the invention's purpose, features and advantages of the invention more obvious and easy to understand, below will be with specific
Examples and drawings, the technical solution protected to the present invention are clearly and completely described, it is clear that implementation disclosed below
Example is only a part of the embodiment of the present invention, and not all embodiment.Based on the embodiment in this patent, the common skill in this field
Art personnel all other embodiment obtained without making creative work belongs to the model of this patent protection
It encloses.
The present invention provides a kind of multi-channel flash memory storage system, as shown in Figure 1, including：2 fpga chips 2, for pair
Dsp chip 1,6 flash memory chip set, a plurality of data that the host interface and address that fpga chip 2 provides carry out signal processing are total
Line 4, a plurality of control bus 5, a plurality of chip selection signal line；
Each flash memory chip set includes 6 flash chips 3, and 6 flash chips 3 in same flash memory chip set pass through common number
It is connect according to bus 4 and control bus 5 with single fpga chip 2；
Flash chip 3 in all flash memory chip sets is connect by independent chip selection signal line with fpga chip 2；2 FPGA cores
Piece 2 is connect with dsp chip 1 respectively.
Wherein, the control bus 5 of different flash memory chip set connections is mutually indepedent；The data of different flash memory chip set connections are total
Line 4 is mutually indepedent.Data/address bus 4, control bus 5, the chip selection signal line of same flash chip 3 connect same fpga chip 2.
Fpga chip 2 uses XC6VLX760 type fpga chip；Dsp chip 1 uses TMS320 series DSP chip；Flash memory core
Piece 3 uses JS29F08G08AANC1 type flash chip.
As shown in Fig. 2, being single channel single flash memory chip design schematic diagram；As shown in figure 3, being set for the more flash chips of single channel
Count schematic diagram；As shown in figure 4, being the more flash chip design schematic diagrams of multichannel.It wherein, include logic control mould in fpga chip
Block and data cache module, fpga chip are connect by NAND pci interface with nand flash memory chip.
In the present invention, master control logic module fpga chip 2 and address management module dsp chip 1 are the core of storage system
The heart, the main reception and forwarding for completing control signal, the mapping of physical address and logical address and the reality of allocation index information
When generate etc. functions.
The function of data classification module is receiving front-end data flow to be stored in fpga chip 2, forms data frame and adds
Each channel controller is sent to after entering allocation index information.Channel controller is then according to address information to corresponding address space
Take corresponding operation.Gating and shared data line are carried out by chip selection signal between the flash memory chip set of parallel connection.
Operation between channel and channel is independent mutually and can be with parallel work-flow.To read-write flash memory time in different channels and
Programming time can get up to operate parallel.In single channel, all chips share a data bus, and read-write chip operation must
It must serially execute.But can be with multiple programming, by single channel between chip and chip, the Cross program design of different chips, from
And make programming time parallel, improve the global storage bandwidth and performance of multichannel.
In single channel, multiple 3 multiple programmings of flash chip improve whole handling capacity；Different 3 shared datas of flash chip
Bus 4 improves access bandwidth and transmission rate in single channel.
Each embodiment in this specification is described in a progressive manner, the highlights of each of the examples are with other
The difference of embodiment, the same or similar parts in each embodiment refer to mutually.
Description and claims of this specification and term " first ", " second ", " third " " in above-mentioned attached drawing
Four " etc.（If there is）It is to be used to distinguish similar objects, without being used to describe a particular order or precedence order.It should manage
The data that solution uses in this way are interchangeable under appropriate circumstances, so as to the embodiment of the present invention described herein can in addition to
Here the sequence other than those of diagram or description is implemented.In addition, term " includes " and " having " and their any deformation,
It is intended to cover and non-exclusive includes.
The foregoing description of the disclosed embodiments enables those skilled in the art to implement or use the present invention.
Various modifications to these embodiments will be readily apparent to those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, of the invention
It is not intended to be limited to the embodiments shown herein, and is to fit to and the principles and novel features disclosed herein phase one
The widest scope of cause.
Claims (7)
1. a kind of multi-channel flash memory storage system, which is characterized in that including：Multiple fpga chips（2）, for fpga chip
（2）The host interface of offer and address carry out the dsp chip of signal processing（1）, multiple flash memory chip sets, data/address bus（4）, control
Bus processed（5）, chip selection signal line；
Flash memory chip set includes multiple flash chips（3）, flash chip in same flash memory chip set（3）Pass through common data
Bus（4）And control bus（5）With single fpga chip（2）Connection；
Flash chip in all flash memory chip sets（3）Pass through independent chip selection signal line and fpga chip（2）Connection；
Multiple fpga chips（2）Respectively with dsp chip（1）Connection.
2. multi-channel flash memory storage system according to claim 1, which is characterized in that
Flash chip in flash memory chip set（3）Number be 16 within.
3. multi-channel flash memory storage system according to claim 2, which is characterized in that
With same fpga chip（2）The number of the flash memory chip set of connection is within 8.
4. multi-channel flash memory storage system according to claim 1, which is characterized in that
The control bus of different flash memory chip set connections（5）Independently of each other；
The data/address bus of different flash memory chip set connections（4）Independently of each other.
5. multi-channel flash memory storage system according to claim 4, which is characterized in that
Same flash chip（3）Data/address bus（4）, control bus（5）, chip selection signal line connect same fpga chip（2）.
6. according to claim 1 or 3 or 5 any multi-channel flash memory storage systems, which is characterized in that
Fpga chip（2）Using XC6VLX760 type fpga chip.
7. multi-channel flash memory storage system according to claim 1, which is characterized in that
Dsp chip（1）Using TMS320 series DSP chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201810609063.5A CN108932204A (en) | 2018-06-13 | 2018-06-13 | A kind of multi-channel flash memory storage system |
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| CN201810609063.5A CN108932204A (en) | 2018-06-13 | 2018-06-13 | A kind of multi-channel flash memory storage system |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109710546A (en) * | 2018-12-13 | 2019-05-03 | 北京航星机器制造有限公司 | A kind of multi-bank flash-memory controller based on field programmable gate array |
| WO2021159494A1 (en) * | 2020-02-14 | 2021-08-19 | 华为技术有限公司 | Solid-state drive and control method for solid-state drive |
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Application publication date: 20181204 |