CN101740103A - Multi-channel flash memory controller - Google Patents
Multi-channel flash memory controller Download PDFInfo
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- CN101740103A CN101740103A CN200810232223A CN200810232223A CN101740103A CN 101740103 A CN101740103 A CN 101740103A CN 200810232223 A CN200810232223 A CN 200810232223A CN 200810232223 A CN200810232223 A CN 200810232223A CN 101740103 A CN101740103 A CN 101740103A
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Abstract
The invention relates to a multi-channel flash memory controller, which solves the defect of slow data read-write speed of a flash memory data in the prior art. The controller comprises an IDE interface module, a microprocessor and a flash memory management module which are connected with one another through two-port caches, wherein the flash memory management module comprises a flash memory interface command resolving unit, an inner management unit, a data interface management unit, a channel arbitration unit, a channel cache and a flash memory sequence unit; the data interface management unit, the channel arbitration unit and the flash memory sequence unit are sequentially connected; the data interface management unit and the channel arbitration unit are connected with the flash memory interface command resolving unit through the inner management unit; and a data transmission channel is independent of a command transmission channel. The multi-channel flash memory controller has the advantages of fast flash memory read-write speed, high data read-write reliability, high error correcting capacity, and long flash memory service life.
Description
Technical field
The present invention relates to a kind of multi-channel flash memory controller.
Background technology
Plurality of advantages such as flash memory is as a kind of new non-volatile memory medium, and is big, easy to carry, low in energy consumption with its storage density, that the power down data hold time long and shock resistance is good, very universal in field of consumer electronics.At industry and military industry field, also more and more come into one's own and welcome.In some mass data storage application scenarios, often have the multi-bank flash-memory cascade or form the permutation use, to enlarge the handling capacity of storage space and raising data.But,, correctly write to guarantee data because flash memory needs to carry out the wait of long period after writing data.Typically, write-once need be waited for 200us, and maximum latency needs 700us.If according to normal operation thinking, just wait for that the writing speed of data can be very slow after in flash memory, writing data, can't satisfy actual request for utilization.In some occasion, sacrifice the stand-by period that writes of each chip in order to obtain high writing speed, can bring the unreliability of data like this.
In addition,, wipe for a long time and cause some storage unit to be made mistakes easily, so-called bad piece promptly occurs because all there is certain serviceable life each sector of flash memory.Except the bad piece that occurs in the use, because production technology, each flash chip is at the certain bad piece of Shi Douyou that dispatches from the factory.Existing bad block management method basic ideas are that these bad pieces are abandoned, yet of flash memory comprises a lot of sectors, and out of order is a bit location of some sectors, and other sectors can normal running in the piece.The way waste storage space very that causes the monoblock storage unit to be abandoned because of makeing mistakes of or several like this.
Because the These characteristics that flash memory itself is had must take corresponding method to maximize favourable factors and minimize unfavourable ones in the use of flash memory, especially will solve two problems mentioned above.In the method for existing flash controller or similarly flash memory control, the raising read or write speed that the method that has can be to a certain degree, but certain bottleneck is still arranged, and do not have error correcting capability; The method that has be for the read or write speed of pursuit flash memory, on the stand-by period that chip writes, save, cause that data can not write reliably under the rugged surroundings; The method that also has is relatively weaker on error correcting capability, and the mistake of 2bit or 4bit can only be corrected in each sector, can not well improve the serviceable life of flash memory.
Summary of the invention
Purpose of the present invention provides a kind of multi-channel flash memory controller that can control the flash memory fast reading and writing for solving the slow defective of flash data read or write speed in the prior art.
Technical solution of the present invention is:
A kind of multi-channel flash memory controller, its special character is:
Comprise the ide interface module, microprocessor module and the flash memory management module that connect mutually by the twoport buffer memory;
Wherein the flash memory management module comprises flash interface command resolution unit, inner management unit, data interface management unit, channel arbitration unit, passage buffer memory, flash memory sequence unit;
Described data interface management unit, channel arbitration unit, flash memory sequence sequence of unit connect;
Described data interface management unit is connected with the flash interface command resolution unit by the inner management unit with channel arbitration unit.
Data transmission channel is independent of the command transfer passage.
Above-mentioned flash controller comprises that the Saloman that is arranged between data interface management unit and the channel arbitration unit is entangled and separates wrong administrative unit.
Above-mentioned flash memory sequence unit is low-speed clock flash memory sequence unit, and remaining element is the high-frequency clock unit.
The present invention has following advantage:
1, flash reading and writing speed is fast.Can break through the theoretical read or write speed of flash memory on the speed, make the read or write speed of flash memory can reach more than the 100MByte/s, to adapt to high-speed interface standard such as PATA, SATA, 1394 and USB etc.Improving on the flash reading and writing speed, as adopting the management by methods flash chip of two-dimensional array of the present invention.Each row has 4～8 row, is made up of 4～8 chips, and these chips are shared a data bus and control bus, and each row chip has oneself independently chip selection signal.Owing on a bus a plurality of chips are arranged, utilize the read-write waiting time of previous chip, carry out the read-write operation of next chip, thereby improved the writing speed of data.In addition, each row constitutes an independently passage, and multirow constitutes a plurality of independently passages.Each passage is independent of each other, independent parallel work, from and improved the transmission speed of data greatly.The institutional framework of two-dimensional array cooperates advanced channel management method, guarantees that the transmission speed of data is very high.
2, reading and writing data reliability height.Time response in strict accordance with flash disk operation on the reliability is waited for, guarantees the reliability of data under various conditions.Improving on the data storing reliability, the present invention guarantees that the time sequential routine of each chip is correct, and guarantee to write the stand-by period and operate in strict accordance with the maximal value that parameter is provided of chip, guaranteed that like this data still can be written to reliably in the Flash chip and go under abominable external condition.Concretely, exactly when a chip is in the state of writing wait, change write operation over to the next column position chip of delegation, and the like, behind chip polling operation one circle of delegation, the chip of operation just is in the time-delay completion status for the first time, can carry out writing next time again.So both guarantee reliably writing of chip, also guaranteed the transmission speed of data.
3, error correcting capability is strong, the flash memory long service life.Separate on the wrong ability entangling, this programme adopts unique decoding method, can check the mistake of 8 bytes to 512 byte datas, corrects the mistake of 4 bytes.This is higher than existing entangling far away and separates wrong method, thereby has improved greatly the serviceable life of flash memory.
Description of drawings
Fig. 1 is a flash memory chip array structure synoptic diagram of the present invention.
Fig. 2 is a flash controller theory diagram of the present invention.
Fig. 3 is flash interface buffer memory internal organizational structure figure of the present invention.
Fig. 4 is the read-write of the flash chip in each passage of the present invention streamline management method synoptic diagram.
Embodiment
Referring to Fig. 1, Fig. 2, be example with the ide interface, describe the flow process of total system work in detail.
Three big main modular are arranged, ide interface module, microprocessor module and flash memory management module among Fig. 2.Carry out the mutual of information and data by the twoport buffer memory between three modules.
The ide interface module mainly is responsible for the realization of ATA agreement, and is responsible for data are separated with order, and data are put into metadata cache, and the command area buffer memory is put in order.And providing the look-at-me of microprocessor, the notice microprocessor has new order etc. pending.
Microprocessor from command buffer sense command information, carries out command analysis after receiving look-at-me from the ide interface module, is converted into the operational order to flash chip; In addition, go back of the conversion of actuating logic address to physical address.After finishing these operations, order and address information after transforming are deposited in the flash interface buffer memory.Remaining work is given the flash memory management module and is finished.
The flash memory management module comprises a plurality of unit, is labeled as: flash interface command resolution unit, inner management unit, data interface management unit, Saloman error correction administrative unit, channel arbitration unit, passage buffer memory, flash memory sequence unit.Wherein,
The flash interface command resolution unit is responsible for reading order and address information from the flash interface buffer memory, and these orders and address information to next unit, promptly to inner administrative unit transmission.
The inner management unit be used for the coordination data interface management unit, entangle the work of separating wrong administrative unit and channel arbitration unit, and be responsible in these three cell operation processes and the flash interface command resolution unit is coordinated, repetition from the flash interface buffer memory, read or write data.
Reading of data from metadata cache is responsible in the data interface management unit, sends into to entangle and separates wrong administrative unit and encode, and perhaps receives self-picketing to separate the data through decoding of wrong administrative unit, and is deposited in the metadata cache.
Entangle and separate the decode operation of wrong administrative unit when being responsible for data and writing fashionable coding and data and read.Cross-cutting directly employing of the present invention was RS coding thinking at the Saloman coding that satellite communication field is used only in the past, because the coding advantage that Saloman coding thinking is brought, make the present invention can check the mistake of 8 bytes, corrected the mistake of 4 bytes 512 byte datas.This is higher than existing flash chip far away and entangles and separate wrong method, thereby has improved the serviceable life of flash memory widely, to such an extent as to further saved the cost of flash memory.
Channel arbitration unit is responsible for the management of follow-up a plurality of passage buffer memorys and the startup of passage task.
Timing generation unit is responsible for producing the sequential of control flash chip.
When carrying out data and write, leave in the flash interface buffer memory through the order and the address of microprocessor conversion, the flash interface command resolution unit command analysis after, pass to the inner management unit.Whether the current command transfer of inner management unit judges belongs to data transfer command.If log-on data interface management unit then from the metadata cache reading of data, and is sent into data that read to entangle and is separated wrong administrative unit and encode.Send into channel arbitration unit through coded data.Channel arbitration unit is according to the destination address selector channel of the address of current data, address information wherein leaves in the flash interface buffer memory, pass over via command resolution unit and inner management unit, and depositing the passage buffer memory in through coded data, and the flash memory sequence generation unit of startup respective channel, by timing generation unit data are write in the flash chip.
In the whole flash memory management module, the flash memory sequence generation unit is used for controlling flash chip, considers the low-speed characteristic of flash chip sequential, and the clock of this unit adopts low-speed clock.Other unit all adopt high-frequency clock.When channel arbitration unit is finished data after the startup command that writes and provide passage of passage buffer memory, the flash interface command resolution unit, inner management unit, data interface management unit, Saloman error correction administrative unit, channel arbitration unit have all been finished this data-moving operation.Can carry out operation next time again.Next time data-moving flow process and said process are just the same.
The channel allocation of data is finished by microprocessor.The address of the data that each passage will be operated and command information all leave in the flash interface buffer memory.Flash interface is cached with institutional framework shown in Figure 3.Institutional framework by Fig. 3 finds out that each passage all has oneself independently data message buffer zone.When the data volume of metadata cache is very big, might each channel allocation multi-pass operations.When this situation occurring, microprocessor once all is written to all operation informations in the information cache of each passage correspondence.Then by the flash interface command resolution unit, the inner management unit, the data interface management unit, Saloman error correction administrative unit, these several functional unit co-ordinations of channel arbitration unit, several times the data-moving that will operate in the passage buffer memory of respective channel.In this process, channel arbitration unit will constantly monitor the busy-idle condition of each passage, is in idle condition in case find certain passage, and front end also have to wait for the data of operation, then carries out reading, encode and moving of data immediately.
Like this, on macroscopic view, ide interface is responsible for the reception of external data, microprocessor is responsible for the conversion distribution of passage of order and data address, the flash interface command resolution unit of flash memory control module, inner management unit, the data interface management unit, Saloman error correction administrative unit, channel arbitration unit are responsible for reading, encoding of the interior data of data buffering and to moving that passage cushions, the flash memory sequence generation unit is responsible for data writing to flash chip.More than the co-ordination of each unit, constituted a flash controller efficiently jointly.
The operating process of read data and said process are just opposite.
Among the present invention, microprocessor only is responsible for the conversion of simple address mapping and order, and once can transmit the information of a plurality of passage multi-pass operationss.Concrete data-moving, encoding and decoding and data writing in flash memory all has hardware logic at a high speed to finish.Owing to reduced the interaction times of microprocessor and FPGA, saved the intermediate treatment time greatly so on the one hand; And, because overwhelming majority work finished by hardware logic, very fast of processing speed, a plurality of channel parallel work have improved the data throughout of system greatly.
Flash data of the present invention writes with reading method and has guaranteed that the time sequential routine of each chip is correct, and the stand-by period that writes and read flash chip of guaranteeing data operates in strict accordance with the parameter maximal value that flash chip provides, and especially this point is particularly important when writing data.So just guaranteed that in abominable external environment condition, data still can be read and write in the flash chip reliably.Concretely, exactly when previous chip is in the state of writing wait, be transferred to next position flash chip at once and carry out read-write operation, the rest may be inferred, order is read and write flash chip, after the chip in the single channel had all been finished data read-write operation, promptly read and write data for the first time flash chip of write operation of first chip in the single channel just in time was in the wait completion status, and the data that can carry out next time write so again.The streamline management method that Fig. 4 institute stream shows has promptly been described above-mentioned operating process.In the writing speed that has guaranteed data, guaranteed data write reliability.And, because the write latency of each chip has obtained sufficient assurance, also just realized the reliability of reading and writing data.
In the multi-channel flash memory that is made of single channel, single channel of the present invention of every increase just can make the read or write speed of the multi-channel flash memory that constitutes double than original single channel read or write speed, thereby significantly improves the read or write speed of flash memory.
Claims (3)
1. multi-channel flash memory controller is characterized in that:
Comprise the ide interface module, microprocessor module and the flash memory management module that connect mutually by the twoport buffer memory;
Wherein the flash memory management module comprises flash interface command resolution unit, inner management unit, data interface management unit, channel arbitration unit, passage buffer memory, flash memory sequence unit;
Described data interface management unit, channel arbitration unit, flash memory sequence sequence of unit connect;
Described data interface management unit is connected with the flash interface command resolution unit by the inner management unit with channel arbitration unit;
Data transmission channel is independent of the command transfer passage.
2. a kind of multi-channel flash memory controller according to claim 1 is characterized in that:
Described flash controller comprises that the Saloman that is arranged between data interface management unit and the channel arbitration unit is entangled and separates wrong administrative unit.
3. a kind of multi-channel flash memory controller according to claim 1 and 2 is characterized in that:
Described flash memory sequence unit is low-speed clock flash memory sequence unit, and remaining element is the high-frequency clock unit.
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| CN200810232223A CN101740103A (en) | 2008-11-11 | 2008-11-11 | Multi-channel flash memory controller |
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101964205A (en) * | 2010-09-17 | 2011-02-02 | 记忆科技(深圳)有限公司 | ECC (Error Correction Code) module dynamic multiplexing system and method based on solid state disk |
| CN102541778A (en) * | 2010-12-17 | 2012-07-04 | 西安奇维测控科技有限公司 | Ultra-high speed and ultra-large capacity storage device and implementation method thereof |
| CN104409099A (en) * | 2014-12-15 | 2015-03-11 | 成都傅立叶电子科技有限公司 | FPGA (field programmable gate array) based high-speed eMMC (embedded multimedia card) array controller |
| CN104021094B (en) * | 2013-03-01 | 2016-12-28 | 慧荣科技股份有限公司 | Data storage device and flash memory control method |
| CN108121503A (en) * | 2017-08-08 | 2018-06-05 | 鸿秦（北京）科技有限公司 | A kind of NandFlash address of cache and block management algorithm |
| CN108536623A (en) * | 2018-04-19 | 2018-09-14 | 深圳市得微电子有限责任公司 | Multichannel NAND Flash controllers and movable storage device |
| CN108932204A (en) * | 2018-06-13 | 2018-12-04 | 郑州云海信息技术有限公司 | A kind of multi-channel flash memory storage system |
| CN111078602A (en) * | 2019-12-27 | 2020-04-28 | 深圳大普微电子科技有限公司 | Flash memory master control chip, control method and test method thereof, and storage device |
| CN112463487A (en) * | 2020-11-25 | 2021-03-09 | 苏州浪潮智能科技有限公司 | Connection error detection method and system of full flash memory array and related components |
| CN112965669A (en) * | 2021-04-02 | 2021-06-15 | 杭州华澜微电子股份有限公司 | Data storage system and method |
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2008
- 2008-11-11 CN CN200810232223A patent/CN101740103A/en active Pending
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101964205A (en) * | 2010-09-17 | 2011-02-02 | 记忆科技(深圳)有限公司 | ECC (Error Correction Code) module dynamic multiplexing system and method based on solid state disk |
| CN101964205B (en) * | 2010-09-17 | 2013-08-07 | 记忆科技(深圳)有限公司 | ECC (Error Correction Code) module dynamic multiplexing system and method based on solid state disk |
| CN102541778A (en) * | 2010-12-17 | 2012-07-04 | 西安奇维测控科技有限公司 | Ultra-high speed and ultra-large capacity storage device and implementation method thereof |
| CN104021094B (en) * | 2013-03-01 | 2016-12-28 | 慧荣科技股份有限公司 | Data storage device and flash memory control method |
| CN104409099A (en) * | 2014-12-15 | 2015-03-11 | 成都傅立叶电子科技有限公司 | FPGA (field programmable gate array) based high-speed eMMC (embedded multimedia card) array controller |
| CN104409099B (en) * | 2014-12-15 | 2017-12-29 | 成都傅立叶电子科技有限公司 | High speed eMMC array control units based on FPGA |
| CN108121503A (en) * | 2017-08-08 | 2018-06-05 | 鸿秦（北京）科技有限公司 | A kind of NandFlash address of cache and block management algorithm |
| CN108121503B (en) * | 2017-08-08 | 2021-03-05 | 鸿秦（北京）科技有限公司 | NandFlash address mapping and block management method |
| CN108536623A (en) * | 2018-04-19 | 2018-09-14 | 深圳市得微电子有限责任公司 | Multichannel NAND Flash controllers and movable storage device |
| CN108932204A (en) * | 2018-06-13 | 2018-12-04 | 郑州云海信息技术有限公司 | A kind of multi-channel flash memory storage system |
| CN111078602A (en) * | 2019-12-27 | 2020-04-28 | 深圳大普微电子科技有限公司 | Flash memory master control chip, control method and test method thereof, and storage device |
| CN112463487A (en) * | 2020-11-25 | 2021-03-09 | 苏州浪潮智能科技有限公司 | Connection error detection method and system of full flash memory array and related components |
| CN112965669A (en) * | 2021-04-02 | 2021-06-15 | 杭州华澜微电子股份有限公司 | Data storage system and method |
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Application publication date: 20100616 |