CN112463487A - Connection error detection method and system of full flash memory array and related components - Google Patents
Connection error detection method and system of full flash memory array and related components Download PDFInfo
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Abstract
The application discloses a connection error detection method of a full flash memory array, which is applied to a target host, wherein N full flash memory arrays are connected with the target host in a cascading mode, and the connection error detection method comprises the following steps: acquiring port connection parameters of a controller corresponding to the full flash memory array; the port connection parameters comprise a local terminal equipment address, a local terminal port address and an opposite terminal port address; performing connection error detection on the full flash memory arrays adjacent to the cascade connection according to the local terminal port address and the opposite terminal port address; and detecting the connection error of the controller of the full flash memory array according to the local terminal equipment address. The method and the device can detect the connection error in the full flash memory array. The application also discloses a connection error detection system of the full flash memory array, an electronic device and a storage medium, and the system has the beneficial effects.
Description
Technical Field
The present disclosure relates to the field of data storage technologies, and in particular, to a method and a system for detecting a connection error of a full flash memory array, an electronic device, and a storage medium.
Background
The cost-effective handling and manipulation of large data sets requires storage system performance that exceeds that provided by conventional hard-disk based storage systems. The full Flash memory array (Just a Bunch Of Flash, JBOF) has the characteristics Of high concurrency, high performance, low delay and the like, so the full Flash memory array is widely popularized and applied. In order to solve the problem of the total capacity of the NVMe disk, a plurality of full flash memory arrays are usually connected to a host in the related art, but at present, no technical scheme exists for detecting connection errors of the full flash memory arrays.
Therefore, how to detect a connection error in a full flash memory array is a technical problem that needs to be solved by those skilled in the art.
Disclosure of Invention
The present application is directed to a method and a system for detecting a connection error in a full flash memory array, an electronic device, and a storage medium, which are capable of detecting a connection error in a full flash memory array.
In order to solve the above technical problem, the present application provides a connection error detection method for a full flash memory array, which is applied to a target host, where N full flash memory arrays are connected to the target host in a cascade manner, and the connection error detection method includes:
acquiring port connection parameters of a controller corresponding to the full flash memory array; the port connection parameters comprise a local terminal equipment address, a local terminal port address and an opposite terminal port address;
performing connection error detection on the full flash memory arrays adjacent to the cascade connection according to the local terminal port address and the opposite terminal port address;
and detecting the connection error of the controller of the full flash memory array according to the local terminal equipment address.
Optionally, performing connection error detection on full flash memory arrays adjacent to the cascade connection according to the home port address and the opposite port address, includes:
acquiring a topology structure chart for describing the connection relation of a full flash memory array in the target host;
and comparing the local port address and the opposite port address of the controller corresponding to the adjacent full flash memory array step by step according to the topology structure diagram so as to detect the connection error.
Optionally, comparing the local port address and the opposite port address of the controller corresponding to the adjacent full flash memory array step by step according to the topology structure diagram, so as to perform connection error detection, including:
selecting a first full flash memory array and a second full flash memory array step by step according to the topological structure chart; the first controller corresponding to the first full flash memory array is connected with the second controller corresponding to the second full flash memory array;
judging whether the address of the local port of the first controller is the same as the address of the opposite port of the second controller or not to obtain a first judgment result;
judging whether the opposite port address of the first controller is the same as the home port address of the second controller or not to obtain a second judgment result;
and if the first judgment result and/or the second judgment result are/is different in address, judging that the first controller and the second controller have a connection error.
Optionally, performing connection error detection on the controller of the full flash memory array according to the address of the home terminal device includes:
selecting a target full flash memory array from all the full flash memory arrays;
judging whether the local terminal equipment addresses of all controllers of the target full flash memory array are the same or not;
if not, judging that the target full flash memory array has a controller connection error.
Optionally, after performing connection error detection on the full flash memory arrays adjacent to the cascade connection according to the local port address and the opposite port address, the method further includes:
marking the lines with connection errors in the topological structure diagram; the topology structure diagram is used for describing the connection relation of the full flash memory array in the target host.
Optionally, after marking the line with the connection error in the topology structure diagram, the method further includes:
and generating alarm information, and displaying the port connection parameters with the wrong connection in a human-computer interaction interface.
Optionally, the full flash memory array is a PCIE full flash memory array based on MiniSAS.
The application also provides a connection error detection system of full flash memory array, is applied to the target host computer, a plurality of N full flash memory arrays through cascaded mode with the target host computer is connected, connect the error detection system and include:
the parameter acquisition module is used for acquiring port connection parameters of the controller corresponding to the full flash memory array; the port connection parameters comprise a local terminal equipment address, a local terminal port address and an opposite terminal port address;
the first error detection module is used for carrying out connection error detection on the full flash memory arrays adjacent to the cascade connection relation according to the local port address and the opposite port address;
and the second error detection module is used for carrying out connection error detection on the controller of the full flash memory array according to the local terminal equipment address.
The application also provides a storage medium, on which a computer program is stored, and the computer program realizes the steps executed by the connection error detection method of the full flash memory array when being executed.
The application also provides an electronic device, which comprises a memory and a processor, wherein a computer program is stored in the memory, and the processor realizes the step executed by the connection error detection method of the full flash memory array when calling the computer program in the memory.
The application provides a connection error detection method of a full flash memory array, which is applied to a target host, wherein N full flash memory arrays are connected with the target host in a cascading mode, and the connection error detection method comprises the following steps: acquiring port connection parameters of a controller corresponding to the full flash memory array; the port connection parameters comprise a local terminal equipment address, a local terminal port address and an opposite terminal port address; performing connection error detection on the full flash memory arrays adjacent to the cascade connection according to the local terminal port address and the opposite terminal port address; and detecting the connection error of the controller of the full flash memory array according to the local terminal equipment address.
According to the scheme provided by the application, the full flash memory array is connected with the target host in a cascading mode, the quantity of host expansion cards can be reduced in the cascading mode, and the storage capacity of the target host is effectively increased. The full flash memory arrays are connected through the ports of the controller, and after port connection parameters of the controllers corresponding to the full flash memory arrays are obtained, the method and the device can judge whether connection errors exist in the full flash memory arrays or not by utilizing the port connection parameters. Specifically, the connection error detection can be performed on the full flash memory array adjacent to the cascade connection according to the local terminal port address and the opposite terminal port address, and the connection error detection can be performed on the controller of the full flash memory array according to the local terminal device address. Therefore, the method and the device can detect the connection error in the full flash memory array. The application also provides a connection error detection system of the full flash memory array, an electronic device and a storage medium, and the connection error detection system, the electronic device and the storage medium have the beneficial effects and are not repeated.
Drawings
In order to more clearly illustrate the embodiments of the present application, the drawings needed for the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings can be obtained by those skilled in the art without inventive effort.
Fig. 1 is a flowchart illustrating a connection error detection method for a full flash memory array according to an embodiment of the present disclosure;
fig. 2 is a schematic diagram of a cascade of a full flash memory array according to an embodiment of the present disclosure;
FIG. 3 is a schematic diagram of a port connection of a full flash memory array according to an embodiment of the present application;
fig. 4 is a schematic structural diagram of a connection error detection system of a full flash memory array according to an embodiment of the present disclosure.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1, fig. 1 is a flowchart illustrating a connection error detection method for a full flash memory array according to an embodiment of the present disclosure.
The specific steps may include:
s101: acquiring port connection parameters of a controller corresponding to the full flash memory array;
the embodiment can be applied to target hosts such as personal computers and servers, and the N full flash memory arrays are connected with the target hosts in a cascading mode. In this embodiment, the full flash memory array can be better expanded, a MiniSAS cable is used as a PCIE (peripheral component interconnect express) transmission medium, and the MiniSAS is used as a marking line, so that the expansibility is good. MiniSAS is SFF-8088 cable, external mini SAS passive cable.
In the related art, in order to solve the problem of the total capacity of the NVMe disk in the target host, the full flash memory array is usually connected to the host in parallel, but when the full flash memory array is connected in parallel, the expansion card needs to be inserted into the main cabinet, so that the cost is increased. Referring to fig. 2, fig. 2 is a schematic diagram of a cascade of full flash memory arrays according to an embodiment of the present disclosure, in fig. 2, a PCIW SW is a PCIE Switch, a main cabinet of a target host is connected to a first-level full flash memory array, and the first-level full flash memory array is connected to a second-level full flash memory array, and in fig. 2, the full flash memory arrays are cascaded in two levels, so that the use of host expansion cards can be reduced, and the storage capacity can be effectively improved. A plurality of NVMe SSDs may be connected in the full flash memory array, and the full flash memory array in this embodiment is a PCIE full flash memory array based on MiniSAS. (NVMe) NVM Express is an open collection of standards and information to fully demonstrate the advantages of non-volatile memory in all types of computing environments from mobile devices to data centers. The full flash memory array can use PCIE as a physical bottom layer transmission protocol, and the Nvme as an in-band SSD protocol has the characteristics of realizing high bandwidth, high concurrency, low delay and the like.
In this embodiment, chassis devices composed of PCIE SW form a cascade, each port has a connector connection description, and a cascade topology in which a host is connected to JBOF1 and JBOF1 is connected to JBOF2 is formed by the connector connection descriptions. The connector connection description is a port connection parameter, and the port connection parameter includes a home device address, a home port address, and an opposite port address.
Referring to fig. 3, fig. 3 is a schematic diagram of port connections of a full flash memory array according to an embodiment of the present disclosure, in fig. 3, a CPU1 is connected to a first-level full flash memory array, a CPU2 is connected to a second-level full flash memory array, wwpn of a CPU1 is C4.0.0, and wwpn of a CPU2 is 1 C4.0.0. The home device address of the first port of the controller 1 of the first-level full flash memory array is 0x56c92bf80203043f, the home address is C5.0.0, and the opposite address is C4.0.0. The home device address of the second port of the controller 1 of the first-level full flash memory array is 0x56c92bf80203043f, the home address is C6.0.0, and the opposite address is C7.0.0. The home device address of the first port of the controller 2 of the first-level full flash memory array is 0x56c92bf80203047f, the home address is 1C5.0.0, and the opposite address is 1 C4.0.0. The home device address of the second port of the controller 2 of the first-level full flash memory array is 0x56c92bf80203047f, the home address is 1C6.0.0, and the opposite address is 1 C7.0.0. The local device address of the port of the controller 1 of the second-level full flash memory array is 0x56c92bf80000003f, the local address is C7.0.0, and the opposite address is C6.0.0. The local device address of the port of the controller 2 of the second-level full flash memory array is 0x56c92bf80000007f, the local address is 1C7.0.0, and the opposite address is 1 C6.0.0. In the above embodiment, the controller 1 is on the left, the controller 2 is on the right, the highest bit of the connection address on the controller 1 is 0, and the highest bit of the connection address on the controller 2 is 1, so as to distinguish the controller 1 from the controller 2. The device addresses of the controllers are generated by the base addresses of the chassis, and the base addresses are unique, such as 0x56c92bf802030400, 0x56c92bf80203043f for controller 1, and 0x56c92bf80203047f for controller 2.
S102: performing connection error detection on the full flash memory arrays adjacent to the cascade connection according to the local terminal port address and the opposite terminal port address;
in this embodiment, connection error detection is performed on all flash memory arrays adjacent to each other in the cascade relationship on the basis of obtaining the port address of the home terminal and the port address of the opposite terminal. Specifically, the host storage system obtains the local port addresses and the opposite port addresses of all the ports, performs one-level and one-level traversal, detects the address validity, namely, determines whether the opposite port addresses correspond to the next-level device port addresses, and if not, a connection error exists. The local port address refers to the address of the port, the opposite port address refers to the address of the opposite port connected with the local port, if the local port address and the opposite port address of two ports adjacent in the cascade relation correspond to each other, the connection of the full flash memory array is correct, otherwise, the connection is wrong.
S103: and detecting the connection error of the controller of the full flash memory array according to the local terminal equipment address.
In this embodiment, it may also be detected whether the addresses of the local devices of the controllers of the same full flash memory array are the same, so as to ensure that the controllers connected to the same full flash memory array are the controllers of the same chassis.
As a feasible implementation manner, after performing connection error detection on the full flash memory arrays adjacent to the cascade relationship according to the local port address and the opposite port address, this embodiment may also mark a line with a connection error in the topology structure diagram; the topology structure diagram is used for describing the connection relation of the full flash memory array in the target host. Furthermore, after the line with the connection error is marked in the topological structure diagram, alarm information can be generated, and the port connection parameters with the connection error are displayed in a human-computer interaction interface.
In the scheme provided by the embodiment, the full flash memory array is connected with the target host in a cascading mode, and the quantity of host expansion cards can be reduced in the cascading mode, so that the storage capacity of the target host is effectively increased. The full flash memory arrays are connected through the ports of the controller, and after the port connection parameters of the controller corresponding to the full flash memory arrays are obtained, the embodiment can judge whether the full flash memory arrays have connection errors or not by using the port connection parameters. Specifically, in this embodiment, connection error detection may be performed on a full flash memory array adjacent to the cascade connection according to the home port address and the opposite port address, and connection error detection may also be performed on a controller of the full flash memory array according to the home device address. It can be seen that the present embodiment is capable of detecting connection errors in a full flash array.
As a further description of the corresponding embodiment of fig. 1, the process of performing connection error detection according to the home port address and the peer port address in S102 may include: acquiring a topology structure chart for describing the connection relation of a full flash memory array in the target host; and comparing the local port address and the opposite port address of the controller corresponding to the adjacent full flash memory array step by step according to the topology structure diagram so as to detect the connection error.
Specifically, the step of comparing the local port address and the opposite port address of the controller corresponding to the adjacent full flash memory array step by step according to the topology structure diagram comprises the following steps:
step 1: selecting a first full flash memory array and a second full flash memory array step by step according to the topological structure chart; the first controller corresponding to the first full flash memory array is connected with the second controller corresponding to the second full flash memory array;
step 2: judging whether the address of the local port of the first controller is the same as the address of the opposite port of the second controller or not to obtain a first judgment result;
and step 3: judging whether the opposite port address of the first controller is the same as the home port address of the second controller or not to obtain a second judgment result;
and 4, step 4: and if the first judgment result and/or the second judgment result are/is different in address, judging that the first controller and the second controller have a connection error.
As a further description of the corresponding embodiment in fig. 1, the process of performing connection error detection on the controller of the full flash memory array according to the local device address in S103 may include: selecting a target full flash memory array from all the full flash memory arrays; judging whether the local terminal equipment addresses of all controllers of the target full flash memory array are the same or not; if not, judging that the target full flash memory array has a controller connection error.
The above-mentioned scheme for performing error detection by using the address of the home terminal device, the address of the home terminal port, and the address of the opposite terminal port is illustrated as follows:
for example, the controller 1 is connected in the following manner: host controller 1wwpn C5.0.0 is connected to JBOF1, port 2 of controller 1 of JBOF1 is connected to port 1 of JBOF2, and port 1 of controller 1 of JBOF2 is connected to port 2 of JBOF 1. The connection mode of the controller 2 is as follows: host controller 2wwpn C5.0.0 is connected to JBOF1, port 2 of controller 1 of JBOF1 is connected to port 1 of JBOF2, and port 1 of controller 1 of JBOF2 is connected to port 2 of JBOF 1.
If the local port address of the port 2 of the controller 1 of the JBOF1 is abc, the opposite port address is def, and the port 2 of the controller 1 of the JBOF1 is connected with the controller 1 of the JBOF2, only if the opposite port address of the port of the controller 1 of the JBOF2 is abc and the local port address is def, it is determined that the port 2 of the controller 1 of the JBOF1 is correctly connected with the port of the controller 1 of the JBOF2, otherwise, it is determined that the connection is wrong.
When the local device address of the controller 1 of the JBOF1 is ghijk, it is determined that the controller 1 of the JBOF1 and the controller 2 are controllers of the same chassis only when the local device address of the controller 2 of the JBOF1 is also ghijk, otherwise, it is determined that the connection is wrong.
The embodiment provides a cascade error detection method, the number of cascades is increased through cascading, the storage capacity is improved, the device connection errors are found in time through effective topology detection, the problem caused by unavailability of devices is avoided, and the usability and the safety are improved.
Referring to fig. 4, fig. 4 is a schematic structural diagram of a connection error detection system of a full flash memory array according to an embodiment of the present disclosure;
the system may include:
a parameter obtaining module 100, configured to obtain a port connection parameter of a controller corresponding to the full flash memory array; the port connection parameters comprise a local terminal equipment address, a local terminal port address and an opposite terminal port address;
a first error detection module 200, configured to perform connection error detection on full flash memory arrays adjacent to each other in a cascade relationship according to the local port address and the opposite port address;
and a second error detection module 300, configured to perform connection error detection on the controller of the full flash memory array according to the local device address.
In the scheme provided by the embodiment, the full flash memory array is connected with the target host in a cascading mode, and the quantity of host expansion cards can be reduced in the cascading mode, so that the storage capacity of the target host is effectively increased. The full flash memory arrays are connected through the ports of the controller, and after the port connection parameters of the controller corresponding to the full flash memory arrays are obtained, the embodiment can judge whether the full flash memory arrays have connection errors or not by using the port connection parameters. Specifically, in this embodiment, connection error detection may be performed on a full flash memory array adjacent to the cascade connection according to the home port address and the opposite port address, and connection error detection may also be performed on a controller of the full flash memory array according to the home device address. It can be seen that the present embodiment is capable of detecting connection errors in a full flash array.
Further, the first error detection module 200 includes:
the topological graph acquisition unit is used for acquiring a topological structure diagram for describing the connection relation of the full flash memory array in the target host;
and the address comparison unit is used for comparing the local port address and the opposite port address of the controller corresponding to the adjacent full flash memory array step by step according to the topology structure diagram so as to detect the connection error.
Further, the address comparison unit is used for selecting a first full flash memory array and a second full flash memory array step by step according to the topology structure chart; the first controller corresponding to the first full flash memory array is connected with the second controller corresponding to the second full flash memory array; the first controller is further configured to determine whether a local port address of the first controller is the same as an opposite port address of the second controller, so as to obtain a first determination result; the first controller is further configured to determine whether an opposite port address of the first controller is the same as a home port address of the second controller, and obtain a second determination result; and if the first judgment result and/or the second judgment result are/is different in address, judging that the first controller and the second controller have a connection error.
Further, the second error detection module 300 is configured to select a target full flash memory array from all the full flash memory arrays; the system is also used for judging whether the local terminal equipment addresses of all the controllers of the target full flash memory array are the same or not; if not, judging that the target full flash memory array has a controller connection error.
Further, the method also comprises the following steps:
the marking module is used for marking the line with connection errors in the topological structure diagram; the topology structure diagram is used for describing the connection relation of the full flash memory array in the target host.
Further, the method also comprises the following steps:
and the alarm module is used for generating alarm information after marking the line with the connection error in the topological structure diagram and displaying the port connection parameters with the connection error in the human-computer interaction interface.
Further, the full flash memory array is a PCIE full flash memory array based on MiniSAS.
Since the embodiment of the system part corresponds to the embodiment of the method part, the embodiment of the system part is described with reference to the embodiment of the method part, and is not repeated here.
The present application also provides a storage medium having a computer program stored thereon, which when executed, may implement the steps provided by the above-described embodiments. The storage medium may include: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.
The application further provides an electronic device, which may include a memory and a processor, where the memory stores a computer program, and the processor may implement the steps provided by the foregoing embodiments when calling the computer program in the memory. Of course, the electronic device may also include various network interfaces, power supplies, and the like.
The embodiments are described in a progressive manner in the specification, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. For the system disclosed by the embodiment, the description is relatively simple because the system corresponds to the method disclosed by the embodiment, and the relevant points can be referred to the method part for description. It should be noted that, for those skilled in the art, it is possible to make several improvements and modifications to the present application without departing from the principle of the present application, and such improvements and modifications also fall within the scope of the claims of the present application.
It is further noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Claims (10)
1. A connection error detection method of a full flash memory array is applied to a target host, N full flash memory arrays are connected with the target host in a cascading mode, and the connection error detection method comprises the following steps:
acquiring port connection parameters of a controller corresponding to the full flash memory array; the port connection parameters comprise a local terminal equipment address, a local terminal port address and an opposite terminal port address;
performing connection error detection on the full flash memory arrays adjacent to the cascade connection according to the local terminal port address and the opposite terminal port address;
and detecting the connection error of the controller of the full flash memory array according to the local terminal equipment address.
2. The method according to claim 1, wherein performing connection error detection on full flash memory arrays adjacent in a cascade relationship according to the local port address and the opposite port address comprises:
acquiring a topology structure chart for describing the connection relation of a full flash memory array in the target host;
and comparing the local port address and the opposite port address of the controller corresponding to the adjacent full flash memory array step by step according to the topology structure diagram so as to detect the connection error.
3. The method according to claim 2, wherein the step of comparing the local port address and the opposite port address of the controller corresponding to the adjacent full flash memory array step by step according to the topology structure diagram so as to perform connection error detection includes:
selecting a first full flash memory array and a second full flash memory array step by step according to the topological structure chart; the first controller corresponding to the first full flash memory array is connected with the second controller corresponding to the second full flash memory array;
judging whether the address of the local port of the first controller is the same as the address of the opposite port of the second controller or not to obtain a first judgment result;
judging whether the opposite port address of the first controller is the same as the home port address of the second controller or not to obtain a second judgment result;
and if the first judgment result and/or the second judgment result are/is different in address, judging that the first controller and the second controller have a connection error.
4. The method of claim 1, wherein performing connection error detection on the controller of the full flash memory array according to the address of the local device comprises:
selecting a target full flash memory array from all the full flash memory arrays;
judging whether the local terminal equipment addresses of all controllers of the target full flash memory array are the same or not;
if not, judging that the target full flash memory array has a controller connection error.
5. The method according to claim 1, wherein after performing connection error detection on full flash memory arrays adjacent to each other in the cascade relationship according to the home port address and the peer port address, the method further comprises:
marking the lines with connection errors in the topological structure diagram; the topology structure diagram is used for describing the connection relation of the full flash memory array in the target host.
6. The connection error detection method according to claim 5, further comprising, after marking the line with the connection error in the topology structure diagram:
and generating alarm information, and displaying the port connection parameters with the wrong connection in a human-computer interaction interface.
7. The connection error detection method of claim 1, wherein the full flash memory array is a PCIE full flash memory array based on MiniSAS.
8. A connection error detection system of a full flash memory array is applied to a target host, N full flash memory arrays are connected with the target host in a cascading mode, and the connection error detection system comprises:
the parameter acquisition module is used for acquiring port connection parameters of the controller corresponding to the full flash memory array; the port connection parameters comprise a local terminal equipment address, a local terminal port address and an opposite terminal port address;
the first error detection module is used for carrying out connection error detection on the full flash memory arrays adjacent to the cascade connection relation according to the local port address and the opposite port address;
and the second error detection module is used for carrying out connection error detection on the controller of the full flash memory array according to the local terminal equipment address.
9. An electronic device comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the method for detecting connection errors of a full flash memory array according to any one of claims 1 to 7 when calling the computer program in the memory.
10. A storage medium having stored thereon computer-executable instructions which, when loaded and executed by a processor, carry out the steps of the method for connection error detection of a full flash memory array according to any one of claims 1 to 7.
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| CN202011338260.1A CN112463487A (en) | 2020-11-25 | 2020-11-25 | Connection error detection method and system of full flash memory array and related components |
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| CN202011338260.1A CN112463487A (en) | 2020-11-25 | 2020-11-25 | Connection error detection method and system of full flash memory array and related components |
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| CN101727395A (en) * | 2008-10-17 | 2010-06-09 | 深圳市朗科科技股份有限公司 | Flash memory device and management system and method thereof |
| CN101740103A (en) * | 2008-11-11 | 2010-06-16 | 西安奇维测控科技有限公司 | Multi-channel flash memory controller |
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| CN103684918A (en) * | 2013-12-16 | 2014-03-26 | 华为技术有限公司 | Method and device for detecting link failure |
| WO2014110707A1 (en) * | 2013-01-15 | 2014-07-24 | 华为技术有限公司 | Method, device, and system for detecting interconnection error |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101727395A (en) * | 2008-10-17 | 2010-06-09 | 深圳市朗科科技股份有限公司 | Flash memory device and management system and method thereof |
| CN101740103A (en) * | 2008-11-11 | 2010-06-16 | 西安奇维测控科技有限公司 | Multi-channel flash memory controller |
| WO2014110707A1 (en) * | 2013-01-15 | 2014-07-24 | 华为技术有限公司 | Method, device, and system for detecting interconnection error |
| CN103543961A (en) * | 2013-10-12 | 2014-01-29 | 浙江宇视科技有限公司 | PCIe-based storage extension system and method |
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Application publication date: 20210309 |