CN108959020B - Method and device for calculating CPU utilization rate of computer - Google Patents

Method and device for calculating CPU utilization rate of computer Download PDF

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CN108959020B
CN108959020B CN201810430440.9A CN201810430440A CN108959020B CN 108959020 B CN108959020 B CN 108959020B CN 201810430440 A CN201810430440 A CN 201810430440A CN 108959020 B CN108959020 B CN 108959020B
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马伟民
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Huawei Technologies Co Ltd
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    • G06—COMPUTING; CALCULATING OR COUNTING
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    • G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
    • G06F11/3024—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a central processing unit [CPU]
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    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
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Abstract

The embodiment of the application discloses a method and a device for calculating the utilization rate of a computer CPU, relates to the technical field of computers, and solves the problems that kernel programming development needs to be carried out on an operating system after a hyper-threading technology is started, and customized development needs to be carried out on different OSs or virtualization platforms in the prior art. The specific scheme is as follows: acquiring the utilization rate of a thread running on each Core; calculating a physical Core utilization for running the Core based on the utilization of threads running on the Core; calculating a utilization of the CPU based on physical Core utilizations of the one or more cores. The scheme provided by the embodiment of the application is suitable for calculating the utilization rate of the CPU.

Description

Method and device for calculating CPU utilization rate of computer
Technical Field
The embodiment of the application relates to the technical field of computers, in particular to a method and a device for calculating the utilization rate of a computer CPU.
Background
A Central Processing Unit (CPU) has a large proportion of the cost of a computer, and how to effectively measure and manage the CPU utilization rate becomes a key problem for improving the IT system resource efficiency.
In the 80 s, the CPU has simpler structure and technology, and can measure the use condition of CPU resources through a top command or a windows task manager. However, with the wide application of Hyper-Threading (HT) and other technologies, the CPU utilization obtained by the Top and other commands for starting the Hyper-Threading feature cannot correctly present the actual use condition of the CPU resource, which leads to a lot of confusion or misguidance in the CPU resource management process. Such as: after the hyper-threading is started, when the CPU resource utilization rate is displayed by 50%, the actual CPU resource utilization rate already exerts most of the capacity of the CPU and reaches 70% -100%.
In the prior art, a method for accurately measuring the utilization rate of CPU resources is as follows: after the hyper-thread is started, the VMware acquires the number of non-suspended cycles (unhatched cycles) through software of the VMware, and divides the number of the cycles to obtain the physical Core utilization rate of the Core.
However, in the technical scheme, the utilization rate of the CPU is obtained by customized development, and kernel programming development is required for an operating system, which is only suitable for VMware commercial platforms. In other scenarios, such as platforms of a general Operating System (OS) and other xens, a Kernel-based Virtual Machine (KVM), etc., the above scheme has no universality and cannot obtain the CPU utilization.
Disclosure of Invention
The embodiment of the application provides a method and a device for calculating the CPU utilization rate of a computer, which can be universal for different OSs or virtualization platforms, and can accurately obtain the CPU utilization rate without development or a small amount of development after the hyper-threading technology is started.
In order to achieve the above purpose, the embodiment of the present application adopts the following technical solutions:
in a first aspect of embodiments of the present application, there is provided a method for calculating a CPU utilization of a central processing unit of a computer, where the computer includes a CPU, the CPU includes one or more physical cores, and each Core runs at least two threads, the method includes: firstly, acquiring the utilization rate of a thread running on each Core; then, calculating the utilization rate of a physical Core running the Core based on the utilization rate of the thread running on the Core; and calculating the utilization rate of the CPU based on the utilization rates of the physical cores of the one or more cores. Therefore, the utilization rate of the physical Core of the Core and the utilization rate of the CPU can be accurately obtained by obtaining the utilization rate of the thread, and the utilization rate of the thread can be obtained without development or little development generally, so that the method can be commonly used for different OSs or virtualization platforms, and is low in implementation cost and good in universality.
With reference to the first aspect, in a first possible implementation manner, the calculating a physical Core utilization rate of the Core based on a utilization rate of a thread running on the Core includes: and converting the utilization rate of the thread running on the Core into the physical Core utilization rate of the Core based on a preset model. The preset model comprises a first model and a second model, wherein the first model is a model representing the relationship between the utilization rate of threads running on the Core and the utilization rate of the Core; the second model is a model representing a relationship between the utilization rate of the Core and the physical Core utilization rate of the Core. Correspondingly, the converting the utilization rate of the thread running on the Core into the physical Core utilization rate of the Core based on the preset model may specifically include: substituting the utilization rate of the thread running on the Core into the first model to obtain the utilization rate of the Core; and substituting the utilization rate of the Core into the second model to obtain the physical Core utilization rate of the Core. In one implementation, when k threads run on Core, k is an integer and k is greater than or equal to 2, the first model is specifically:
Figure BDA0001653273700000011
wherein, thIs the utilization of the h-th thread running on the Core, and x is the utilization of the Core. Therefore, the utilization rate of each corresponding Core can be accurately obtained according to the utilization rate of the thread running on each Core. The second model specifically includes: y 2x-x2And y is the physical Core utilization rate of the Core. Therefore, the real utilization rate of the Core can be obtained according to the utilization rate of the Core, and the physical Core utilization rate of each Core can be obtained without developing a special module aiming at an OS or a virtualization platform to read the register information of a processor. Therefore, the physical Core utilization rate of the Core can be accurately and quickly obtained through the pre-established first model and the pre-established second model.
With reference to the first aspect and the foregoing possible implementation manners, in another possible implementation manner, the calculating a utilization rate of the CPU based on utilization rates of the physical cores of the one or more cores specifically includes: and obtaining the average physical Core utilization rate of the cores of the CPU as the utilization rate of the CPU based on the physical Core utilization rates of the one or more cores. In this way, when the CPU includes a plurality of cores, the CPU utilization rate can be obtained by averaging the physical Core utilization rates of the cores included in the CPU.
With reference to the first aspect and the foregoing possible implementation manners, in another possible implementation manner, when a computer includes multiple CPUs, the multiple CPU utilization rates of the computer are average utilization rates of the multiple CPUs. Therefore, when the computer comprises a plurality of CPUs, the CPU utilization rate of the computer can be obtained according to the utilization rate of each CPU in the computer, and the real CPU resource use condition of the computer is obtained.
In a second aspect of the embodiments of the present application, there is provided a computing apparatus for CPU utilization in a central processing unit of a computer, the computer including a CPU, the CPU including one or more physical cores, each Core running at least two threads thereon, the computing apparatus including: an acquisition unit and a calculation unit; the acquiring unit is used for acquiring the utilization rate of the thread running on each Core in at least one Core; a calculating unit, configured to calculate a physical Core utilization rate for operating the Core based on a utilization rate of a thread operating on the Core; the computing unit is further configured to compute a utilization of the CPU based on the physical Core utilization of the one or more cores.
With reference to the second aspect, in a first possible implementation manner, the computing unit is specifically configured to convert, based on a preset model, a utilization rate of a thread running on the Core into a physical Core utilization rate of the Core. The preset model includes a first model and a second model, and the description of the first model and the second model may refer to the first aspect, which is not described herein again. Correspondingly, the computing unit is specifically configured to: converting, based on the first model, a utilization of a thread running on the Core to a utilization of the Core; the calculation unit is specifically configured to convert the utilization rate of the Core into a physical Core utilization rate of the Core based on the second model.
With reference to the second aspect and the foregoing possible implementation manners, in another possible implementation manner, the calculating unit is specifically configured to: obtaining an average physical Core utilization of the cores of the CPU as the utilization of the CPU based on the physical Core utilization of the one or more cores.
With reference to the second aspect and the foregoing possible implementation manner, in another possible implementation manner, the computer includes a plurality of CPUs, and a plurality of CPU utilization rates of the computer are average utilization rates of the plurality of CPUs.
The above second aspect and descriptions of effects of various implementation manners of the second aspect may refer to descriptions of corresponding effects of the first aspect, and are not described herein again.
In a third aspect of the embodiments of the present application, a computer is provided, where the computer includes a processor and a memory, the processor includes at least one CPU, each CPU includes one or more physical cores, each Core runs on at least two threads, the memory is configured to be coupled to the processor and store necessary program instructions and data of the computer, and the processor is configured to execute the program instructions stored in the memory, so that the computer executes the method described above.
A fourth aspect of the embodiments of the present application provides a computer storage medium, where a computer program code is stored in the computer storage medium, and when the computer program code runs on a processor, the processor is caused to execute the method for calculating the CPU utilization of the central processing unit of the computer according to the first aspect or any of the possible implementation manners of the first aspect.
In a fifth aspect of the embodiments of the present application, a computer program product is provided, where the computer program product stores computer software instructions executed by the processor, and the computer software instructions include a program for executing the solution of the above aspect.
In a sixth aspect of the embodiments of the present application, there is provided an apparatus in the form of a chip, the apparatus includes a processor and a memory, the memory is configured to be coupled to the processor and stores necessary program instructions and data of the apparatus, and the processor is configured to execute the program instructions stored in the memory, so that the apparatus performs the functions of the computing apparatus for calculating the CPU utilization of the computer in the method.
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Fig. 1 is a schematic structural diagram of a computer according to an embodiment of the present disclosure;
FIG. 2 is a block diagram of a specific computer according to an embodiment of the present disclosure;
FIG. 3 is a flowchart of a method for calculating a CPU utilization of a computer according to an embodiment of the present disclosure;
FIG. 4 is a graph illustrating a comparison between actual and theoretical values of Core utilization and physical Core utilization of cores provided by an embodiment of the present application;
FIG. 5 is a schematic diagram of a computer according to an embodiment of the present disclosure;
fig. 6 is a schematic composition diagram of another computer provided in the embodiment of the present application.
Detailed Description
The embodiment of the present application provides a method for calculating a CPU utilization of a Computer, which may be, for example, a tablet Computer, a desktop Computer, a laptop Computer, a notebook Computer, an Ultra-mobile Personal Computer (UMPC), a handheld Computer, a netbook, a Personal Digital Assistant (PDA), and the like.
Fig. 1 is a schematic structural diagram of a computer 100 according to an embodiment of the present disclosure. As shown in fig. 1, the computer 100 includes: a hardware layer including a processor 101, a memory 102, a bus 103, etc., and a software layer including an operating system 104.
The processor 101: is a core component of the computer 100 and is used for running an operating system of the computer 100 and application programs (including system application programs and third party application programs) on the computer 100.
In this embodiment of the present application, the processor 101 may specifically be a Central Processing Unit (CPU), which may implement or execute various exemplary logic blocks, modules and circuits described in connection with the disclosure of the embodiment of the present application; a processor may also be a combination of computing functions, e.g., comprising one or more microprocessors, a DSP and a microprocessor, or the like. In the embodiment of the present application, only a processor is taken as an example for explanation, as shown in fig. 1, the computer 100 includes a CPU, the CPU includes a physical Core, and after the hyper-threading technology is started, at least two threads (only two threads are illustrated in fig. 1) run on each Core. The number of CPUs included in the computer and the number of physical cores included in each CPU are not limited in the embodiment of the present application. It is to be understood that fig. 1 is only an exemplary structure diagram, and the number of threads running on each Core may be the same or different, which is not limited in the embodiment of the present application.
The memory 102: may be used to store software programs and modules that are executed by the processor 101 to perform various functional applications and data processing of the computer 100 by operating the software programs and modules stored in the memory 102. Memory 102 may include one or more computer-readable storage media. The memory 102 includes a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function, and the like, for example, a program implementing the calculation method of the CPU utilization of the computer provided by the embodiment of the present application. The storage data area may store data created by the computer 100, and the like. For example, the utilization of the thread obtained during the execution of the calculation method of the CPU utilization of the computer, and the calculation results of each stage, such as the utilization of the Core, the utilization of the physical Core of the Core, the utilization of the CPU, the utilization of a plurality of CPUs of the computer, and the like, may be stored.
In this embodiment, the memory 102 may specifically include a volatile memory (volatile memory), such as a random-access memory (RAM); the memory may also include a non-volatile memory (non-volatile memory), a flash memory (flash memory), a hard disk (HDD) or a solid-state drive (SSD); the memory may also comprise a combination of memories of the kind described above.
Bus 103: the bus of the computer can be divided into a data bus, an address bus and a control bus according to the types of information transmitted by the computer, and the data bus, the address bus and the control bus are respectively used for transmitting data, data addresses and control signals.
The Operating System 104(Operating System, abbreviated as OS) is a computer program for managing and controlling hardware and software resources of a computer, and is the most basic System software directly running on a "bare computer" for supporting the running of other software, such as various application programs. The operating system in the embodiment of the present application may be various operating systems, for example, a Windows operating system, a Linux operating system, an iOS operating system, an Android open source operating system, and virtualization operating platforms such as kvm, xen, and the like running on the Windows operating system and the Linux operating system.
It is understood that fig. 1 is only an exemplary illustration, and in practical applications, the computer 100 may include more or less components than those shown in fig. 1, for example, a user interface for supporting interaction and information exchange between the system and a user, or a communication interface for supporting communication between the terminal and other terminals, servers, and networks; the structure shown in fig. 1 does not set any limit to the computer provided in the embodiments of the present application.
In order to solve the problems that kernel programming development needs to be performed on an operating system when the CPU utilization rate is obtained and customized development needs to be performed on different OSs or virtualization platforms in the background art, embodiments of the present application provide a method for calculating the CPU utilization rate of a computer, the method is universal to different OSs or virtualization platforms, and the CPU utilization rate can be accurately obtained without development or a small amount of development after a hyper-threading technology is started.
For convenience of description, as shown in fig. 2, a specific structural schematic diagram of a computer is provided, and here, the method for calculating the CPU utilization of the computer provided in the embodiment of the present application is illustrated only by using the structural schematic diagram shown in fig. 2. The computer 200 includes two CPUs, which are respectively designated as a CPU1 and a CPU2, a CPU1 and a CPU2 each include two physical cores Core, which are respectively designated as a Core11, a Core12, a Core21 and a Core22, two threads are run on a Core11 included in the CPU1, which are respectively designated as a thread 111 and a thread 112, two threads are run on a Core12 included in the CPU1, which are respectively designated as a thread 121 and a thread 122, two threads are run on a Core21 included in the CPU2, which are respectively designated as a thread 211 and a thread 212, and two threads are run on a Core22 included in the CPU2, which are respectively designated as a thread 221 and a thread 222.
The method for calculating the utilization rate of the CPU of the computer provided by the embodiment of the application is carried out in the scene after the hyper-threading technology is started by the computer. The hyper-threading technology enables a CPU to execute multiple threads simultaneously, and after the hyper-threading technology is started, at least two threads run on each physical Core. The threads in the following embodiments are all threads after the hyper-threading technique is turned on. The method provided by the embodiment of the application can be applied to various operating systems and various scenes of a virtualization platform.
With reference to fig. 1 and fig. 2, as shown in fig. 3, the method for calculating a CPU utilization of a computer according to the embodiment of the present application may include S301 to S303:
s301, obtaining the utilization rate of the thread running on each Core.
The utilization rate of the thread is the ratio of time slices occupied by the application programs running on the thread to time slices allocable on the thread, and can reflect the use condition of thread computing resources.
Specifically, the utilization rates of all threads running on one or more cores included in the CPU may be obtained separately, for example, referring to fig. 2, the utilization rates of the thread 111, the thread 112, the thread 121, and the thread 122 may be obtained separately for the CPU 1.
For example, the utilization of all threads running on each Core may be obtained based on the utilization of threads recorded within the operating system.
And S302, calculating the utilization rate of the physical Core running the Core based on the utilization rate of the thread running on the Core.
The physical Core utilization rate of the Core is the ratio of the currently used computing resources of the Core to all available computing resources of the Core, and can reflect the use condition of the real resources of the Core.
For example, calculating the physical Core utilization to run the Core based on the utilization of the threads running on the Core may include: and converting the utilization rate of the thread running on the Core into the physical Core utilization rate of the Core based on a preset model.
Specifically, the preset model is a model representing a relationship between the utilization rate of a thread running on the Core and the physical Core utilization rate of the Core, the specific form of the preset model is not specifically limited in the embodiment of the application, the utilization rate of the thread running on any Core is substituted into the preset model, and the obtained physical Core utilization rate of the Core is within the protection range of the application.
For example, the preset model may include a first model and a second model. The first model is a model representing a relationship between a utilization rate of a thread running on a Core and a utilization rate of the Core; the second model is a model representing a relationship between the utilization of the Core and the physical Core utilization of the Core.
Correspondingly, S302 may specifically include S302a-S302 b:
s302a, converting the utilization rate of the thread running on the Core into the utilization rate of the Core based on the first model.
The utilization rate of the Core refers to the ratio of time slices occupied by the application program running on all threads contained in the Core to time slices allocable on all threads contained in the Core.
The utilization rate of a thread running on any Core can be obtained by substituting the utilization rate of the thread running on the Core into the first model.
Specific form of the first model the embodiments of the present application are not particularly limited. As long as the relationship between the utilization of a thread running on a Core and the utilization of the Core can be clearly expressed. In one implementation, when k threads are running on the Core, k is an integer and k ≧ 2, the first model may be:
Figure BDA0001653273700000051
wherein, thIs the utilization of the h-th thread running on a Core, x is the utilization of the Core, and k is the number of threads running on the Core.
Illustratively, when there are three threads running on a Core, the utilization of the Core is
Figure BDA0001653273700000052
When two threads run on one Core, the utilization rate of the Core is
Figure BDA0001653273700000053
As shown in FIG. 2, if the utilization of threads 111 is 25% and the utilization of threads 112 is 35%, then the utilization of Core11 is 30%.
If the utilization of thread 121 is 30% and the utilization of thread 122 is 50%, then the utilization of Core12 is 40%.
If the utilization of the thread 211 is 40% and the utilization of the thread 212 is 50%, then the utilization of Core21 is 45%.
If the utilization of thread 221 is 35% and the utilization of thread 222 is 45%, then the utilization of Core22 is 40%.
S302b, converting the utilization rate of the Core into a physical Core utilization rate of the Core based on the second model.
And substituting the utilization rate of any Core into the second model to obtain the physical Core utilization rate of the Core.
Specific form of the second model the embodiments of the present application are not particularly limited. As long as the relationship between the utilization of one Core and the physical Core utilization of the Core can be clearly expressed. In one implementation, the second model may be:
y＝2x-x2wherein, y is the utilization rate of the physical Core of the Core, and x is the utilization rate of the Core.
Illustratively, in conjunction with FIG. 2, if the utilization of Core11 is 30%, then the physical Core utilization that represents the true resource usage of Core11 is 2x 0.3-0.3^ 2-0.51 ^ 51%.
If the utilization rate of the Core12 is 40%, the physical Core utilization rate of the real resource use condition of the Core12 is 2 × 0.4-0.4^2 ^ 0.64 ^ 64%.
If the utilization rate of the Core21 is 45%, the physical Core utilization rate of the real resource use condition of the Core21 is 2 × 0.45-0.45^2 ^ 0.6975 ^ 69.8%.
If the utilization rate of the Core22 is 40%, the physical Core utilization rate of the real resource use condition of the Core22 is 2 × 0.4-0.4^2 ^ 0.64 ^ 64%.
As shown in FIG. 4, which is a graph comparing an actual value with a theoretical value between the Core utilization rate and the physical nucleus utilization rate of the Core, the horizontal axis represents the Core utilization rate, the vertical axis represents the physical nucleus utilization rate of the Core, when the solid dots represent the Core utilization rate of 15% -75%, the curve shows that when the utilization rate of the Core is 15% -75%, the actually detected actual value range of the utilization rate of the physical Core of the Core is obtained by the calculation method provided by the embodiment of the application, because the number of sample points is too many, the actual values of the physical Core utilization rate of the actually detected Core are all in the curve range, therefore, the actual value range of the actually detected physical Core utilization rate of the Core is represented by the area of the curve, and the theoretical value of the physical Core utilization rate of the Core obtained by calculation in the embodiment of the application is very close to the actual value of the actually detected physical Core utilization rate of the Core after the data comparison of enough samples is carried out for verification.
S303, calculating the utilization rate of the CPU based on the utilization rate of the physical cores of the one or more cores.
The utilization rate of the CPU is a ratio of used resources of the CPU to allocable resources of the CPU, and can reflect the use condition of real resources of the CPU.
It should be noted that, in the embodiment of the present application, a specific calculation manner of how to calculate the utilization rate of the CPU from the utilization rates of the physical cores of one or more cores is not limited, and any method of obtaining the utilization rate of the CPU from the utilization rates of the physical cores of one or more cores is within the protection scope of the present invention.
For example, one implementation of calculating the utilization of a CPU based on the utilization of physical cores of one or more cores may be: and obtaining the average physical Core utilization rate of the cores of the CPU as the utilization rate of the CPU based on the physical Core utilization rates of the one or more cores.
The average physical Core utilization of the Core of the CPU may be:
substituting physical Core utilization of one or more cores contained in a CPU
Figure BDA0001653273700000061
And obtaining the average physical Core utilization rate of the Core of the CPU, namely the utilization rate of the CPU, wherein,
Figure BDA0001653273700000062
for CPU utilization, yiThe physical Core utilization rate of the ith Core contained in the CPU is shown, m is the number of cores contained in the CPU, and m is an integer.
It is to be understood that, in the embodiment of the present application, the number of cores included in each CPU is not limited, and the number of cores included in each CPU may be the same or different. For example, when the number of cores included in the CPU is two, the utilization rate of the CPU may be
Figure BDA0001653273700000063
Illustratively, in conjunction with FIG. 2, if the physical Core utilization of Core11 is 51% and the physical Core utilization of Core12 is 64%, then the utilization of CPU1 is 57.5%.
If the physical Core utilization of Core21 is 69.8% and the physical Core utilization of Core22 is 64%, then the utilization of CPU2 is 66.9%.
For example, the number of CPUs included in a computer is not limited in the embodiments of the present application, and if the computer includes multiple CPUs, the utilization rate of the multiple CPUs of the computer is an average utilization rate of the multiple CPUs.
The multiple CPU utilization rates of the computer refer to the ratio of used resources of all CPUs included in the computer to allocable resources of all CPUs included in the computer, and can reflect the use condition of real resources of the computer.
For example, the plurality of CPU utilization of the computer may be:
substituting utilization rate of each CPU in multiple CPUs included in computer
Figure BDA0001653273700000064
Obtaining a plurality of CPU utilization rates of the computer, wherein z is the plurality of CPU utilization rates of the computer,
Figure BDA0001653273700000065
the utilization rate of the jth CPU contained in the computer is shown, n is the number of CPUs contained in the computer, n is not less than 2, and n is an integer.
Specifically, when the computer only includes one CPU, the CPU utilization of the computer is the utilization of the single CPU; when a plurality of CPUs are included in a computer, the CPU utilization of the computer may be an average of the utilization of the plurality of CPUs included in the computer. The CPU utilization rate of the computer in the application refers to the CPU utilization rate displayed in a performance column after a task manager of the computer is started.
Illustratively, as shown in connection with FIG. 2, if the utilization of CPU1 is 57.5% and the utilization of CPU2 is 66.9%, then the CPU utilization of computer 200 is 62.2%.
According to the method for calculating the utilization rate of the CPU of the computer, the utilization rate of the thread running on each Core is obtained, the utilization rate of the physical Core running on the Core is calculated based on the utilization rate of the thread running on the Core, and the utilization rate of the CPU is calculated based on the utilization rates of the physical cores of one or more cores. Compared with the prior art in which different OSs or virtualization platforms need to be customized and developed, the method for calculating the CPU utilization rate can be universal for different OSs or virtualization platforms, and real CPU utilization rate data can be accurately obtained without development or a small amount of development.
The above description has introduced the scheme provided by the embodiments of the present invention mainly from the perspective of the method steps. It will be appreciated that the computer, in order to carry out the above-described functions, may comprise corresponding hardware structures and/or software modules for performing the respective functions. Those of skill in the art would readily appreciate that the present application is capable of being implemented as a combination of hardware and computer software for carrying out the various example elements and algorithm steps described in connection with the embodiments disclosed herein. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
In the embodiment of the present application, functional modules may be divided according to the above method example, for example, each functional module may be divided corresponding to each function, or two or more functions may be integrated into one processing module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode. It should be noted that, the division of the modules in the embodiment of the present invention is schematic, and is only a logic function division, and there may be another division manner in actual implementation.
In the case of dividing each functional module by corresponding functions, fig. 5 shows a possible structural diagram of the computer involved in the above embodiment, and the computer 500 includes: an acquisition unit 501 and a calculation unit 502. The acquiring unit 501 is used to support the computer to execute S301 in fig. 3; the computing unit 502 is used to support the computer to execute S302-S303 in fig. 3. All relevant contents of each step related to the above method embodiment may be referred to the functional description of the corresponding functional module, and are not described herein again.
Fig. 6 shows a possible schematic diagram of the computer involved in the above-described embodiment, in the case of an integrated unit. The computer 600 includes: a storage module 601 and a processing module 602. The processing module 602 is used to control and manage the actions of the computer, e.g., the processing module 602 is used to support the computer to perform S301-S303 of FIG. 3, and/or other processes for the techniques described herein. The storage module 601 is used for storing program codes and data of the computer. When the storage module 601 is a memory and the processing module 602 is a processor, the specific structure of the computer shown in fig. 6 may be the computer shown in fig. 1 or fig. 2, where the description of all relevant contents of the components related to fig. 1 or fig. 2 may be referred to the functional description of the corresponding components in fig. 6, and is not repeated herein. In another implementation, the computer structure according to the above embodiments may further include a processor and an interface, the processor and the interface communicating with each other, and the processor being configured to execute the embodiments of the present invention. The processor may be a CPU, or other hardware, such as a Field-Programmable Gate Array (FPGA), etc., or a combination of both.
The steps of a method or algorithm described in connection with the disclosure herein may be embodied in hardware or in software instructions executed by a processor. The software instructions may be comprised of corresponding software modules that may be stored in Random Access Memory (RAM), flash Memory, Erasable Programmable read-only Memory (EPROM), Electrically Erasable Programmable read-only Memory (EEPROM), registers, a hard disk, a removable disk, a compact disc read-only Memory (CD-ROM), or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. Of course, the storage medium may also be integral to the processor. The processor and the storage medium may reside in an ASIC. Additionally, the ASIC may reside in a core network interface device. Of course, the processor and the storage medium may reside as discrete components in a core network interface device.
Those skilled in the art will recognize that, in one or more of the examples described above, the functions described in this invention may be implemented in hardware, software, firmware, or any combination thereof. When implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer.
The above-mentioned embodiments, objects, technical solutions and advantages of the present invention are further described in detail, it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made on the basis of the technical solutions of the present invention should be included in the scope of the present invention.

Claims (18)

1. A method for calculating CPU utilization of a central processing unit of a computer, the computer including a CPU having one or more physical cores on each of which at least two threads run, the method comprising:
acquiring the utilization rate of the thread running on each Core;
calculating a physical Core utilization for running the Core based on the utilization of threads running on the Core;
calculating a utilization of the CPU based on physical Core utilizations of the one or more cores.
2. The computing method of claim 1, wherein computing the physical Core utilization of the Core based on the utilization of threads running on the Core comprises:
and converting the utilization rate of the thread running on the Core into the physical Core utilization rate of the Core based on a preset model.
3. The computing method of claim 2, wherein the predetermined model comprises a first model and a second model,
based on preset model, convert the utilization ratio of the thread running on the Core into the physical Core utilization ratio of the Core, specifically including:
converting, based on the first model, a utilization of a thread running on the Core to a utilization of the Core;
converting the utilization of the Core to a physical Core utilization of the Core based on the second model.
4. The computing method according to claim 3, wherein when k threads are run on the Core, k is an integer and k ≧ 2, the first model is in particular:
Figure FDA0002707882240000011
wherein, thIs the utilization rate of the h thread running on the Core, and x is the utilization rate of the Core.
5. The computing method according to claim 4, characterized in that the second model is in particular:
y＝2x-x2and y is the physical Core utilization rate of the Core.
6. The computing method according to any one of claims 1 to 5, wherein the computing the utilization of the CPU based on the utilization of the physical cores of the one or more cores specifically comprises:
obtaining an average physical Core utilization of the cores of the CPU as the utilization of the CPU based on the physical Core utilization of the one or more cores.
7. The computing method according to any one of claims 1 to 5, wherein the computer comprises a plurality of CPUs, and the plurality of CPU utilization rates of the computer is an average utilization rate of the plurality of CPUs.
8. The computing method of claim 6, wherein the computer comprises a plurality of CPUs, and wherein the plurality of CPU utilization rates of the computer is an average utilization rate of the plurality of CPUs.
9. A computing device for CPU utilization in a central processing unit of a computer, the computer including a CPU, the CPU including one or more physical cores, each Core having at least two threads running thereon, the device comprising: an acquisition unit and a calculation unit;
the obtaining unit is used for obtaining the utilization rate of the thread running on each Core in the at least one Core;
the computing unit is used for computing the utilization rate of a physical Core running the Core based on the utilization rate of the thread running on the Core;
the computing unit is further configured to compute a utilization of the CPU based on the physical Core utilization of the one or more cores.
10. The computing apparatus according to claim 9, wherein the computing unit is configured to convert a utilization of a thread running on the Core into a physical Core utilization of the Core based on a preset model.
11. The computing device of claim 10, wherein the pre-set model comprises a first model and a second model,
the computing unit is specifically configured to convert a utilization rate of a thread running on the Core into a utilization rate of the Core based on the first model;
the computing unit is specifically configured to convert the utilization rate of the Core into a physical Core utilization rate of the Core based on the second model.
12. The computing apparatus as recited in claim 11, wherein when k threads are run on the Core, k is an integer and k ≧ 2, the first model, in particular:
Figure FDA0002707882240000021
wherein, thIs the utilization rate of the h thread running on the Core, and x is the utilization rate of the Core.
13. The computing device according to claim 12, wherein the second model is in particular:
y＝2x-x2and y is the physical Core utilization rate of the Core.
14. The computing device according to any one of claims 9 to 13, wherein the computing unit is specifically configured to:
obtaining an average physical Core utilization of the cores of the CPU as the utilization of the CPU based on the physical Core utilization of the one or more cores.
15. The computing device of any one of claims 9-13, wherein the computer comprises a plurality of CPUs, and wherein the plurality of CPU utilization rates of the computer is an average utilization rate of the plurality of CPUs.
16. The computing device of claim 14, wherein the computer includes a plurality of CPUs, and wherein the plurality of CPU utilization rates of the computer is an average utilization rate of the plurality of CPUs.
17. A computer storage medium having computer program code stored therein, which when run on a processor causes the processor to perform a method of calculating a computer central processor CPU utilization according to any one of claims 1 to 7.
18. A computer, characterized in that the computer comprises a processor and an interface, the processor and the interface being in communication, the processor being configured to perform the method of any of claims 1-7.
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US11106481B2 (en) 2019-04-19 2021-08-31 Red Hat, Inc. Safe hyper-threading for virtual machines
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Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7197652B2 (en) * 2003-12-22 2007-03-27 International Business Machines Corporation Method and system for energy management in a simultaneous multi-threaded (SMT) processing system including per-thread device usage monitoring
US8589707B2 (en) * 2008-12-05 2013-11-19 Stmicroelectronics International N.V. System and method for optimizing electrical power consumption by changing CPU frequency including steps of changing the system to a slow mode, changing a phase locked loop frequency register and changing the system to a normal mode
CN101876933A (en) * 2009-04-28 2010-11-03 深圳富泰宏精密工业有限公司 Analysis system and method for CPU utilization rate
US8793515B2 (en) * 2011-06-27 2014-07-29 Intel Corporation Increasing power efficiency of turbo mode operation in a processor
US9075610B2 (en) * 2011-12-15 2015-07-07 Intel Corporation Method, apparatus, and system for energy efficiency and energy conservation including thread consolidation
JP6142709B2 (en) * 2013-07-23 2017-06-07 富士通株式会社 Measuring method, measuring program, portable information terminal, and control method thereof
US9594660B2 (en) * 2014-03-27 2017-03-14 International Business Machines Corporation Multithreading computer system and program product for executing a query instruction for idle time accumulation among cores
US9647909B2 (en) * 2014-09-23 2017-05-09 Uila Networks, Inc. Monitor a data center infrastructure
US9886324B2 (en) * 2016-01-13 2018-02-06 International Business Machines Corporation Managing asset placement using a set of wear leveling data
CN106293981A (en) * 2016-07-29 2017-01-04 浪潮电子信息产业股份有限公司 Detection method for server CPU hyper-threading technology
CN108255572A (en) * 2016-12-29 2018-07-06 华为技术有限公司 A kind of VCPU switching methods and physical host
JP6778130B2 (en) * 2017-02-24 2020-10-28 日本電信電話株式会社 Virtual computer system and its resource allocation method

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