CN111078602A - Flash memory master control chip, control method and test method thereof, and storage device - Google Patents
Flash memory master control chip, control method and test method thereof, and storage device Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2268—Logging of test results
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2273—Test methods
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1689—Synchronisation and timing concerns
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0658—Controller construction arrangements
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
Abstract
The invention relates to the field of storage, and discloses a flash memory master control chip, a control method, a test method and storage equipment thereof, wherein the flash memory master control chip comprises the following steps: determining the working state of a physical layer; according to the working state of the physical layer, the input channel is gated, the input channel comprises a first data channel which can be configured by the physical layer to the I/O interface by the first operation time sequence, or a second data channel which can be configured by a controller connected with the physical layer to the I/O interface by the second operation time sequence, the I/O interface is used for connecting a flash memory medium, and any operation time sequence is used for controlling the flash memory medium. The first data channel and the second data channel are configured in the flash memory main control chip to coordinate to operate the flash memory medium, wherein the second data channel bypasses the physical layer and directly generates a second operation time sequence to the I/O interface by the controller to operate the flash memory medium, so that the operation efficiency of the flash memory main control chip is improved.
Description
Technical Field
The invention relates to the field of storage, in particular to a flash memory master control chip, a control method, a test method and storage equipment thereof.
Background
A storage device (solid state Drive (SSD)) using NAND (Not-And, abbreviated as "NAND") flash memory particles as a medium has the advantages of short read/write delay time, low power consumption, And fast random access. It is a mainstream trend to build high-performance storage devices by using SSD devices.
The flash memory controller is an important component of the SSD controller, and is directly connected with the flash memory medium to operate the flash memory medium. However, some flash memory media have special timing requirements for special instructions, and if the flash memory controller needs to send a special instruction to operate the flash memory media, the flash memory controller needs to perform multiple adjustments and switching in the sending process, which further takes a lot of time and affects the performance of the flash memory media.
Disclosure of Invention
An object of the embodiments of the present invention is to provide a flash memory master control chip, a control method, a test method, and a storage device thereof, which can improve the operating efficiency of the flash memory master control chip.
In order to solve the technical problems, the invention provides the following technical scheme:
in a first aspect, an embodiment of the present invention provides a flash memory master control chip control method, including:
determining the working state of a physical layer;
according to the working state of the physical layer, an input channel is gated, wherein the input channel comprises a first data channel which can be configured by the physical layer to an I/O interface by a first operation time sequence, or a second data channel which can be configured by a controller connected with the physical layer to the I/O interface by a second operation time sequence, the I/O interface is used for connecting a flash memory medium, and any operation time sequence is used for controlling the flash memory medium.
Optionally, the operating state includes a busy state and an idle state, and the gating the input channel according to the operating state of the physical layer includes:
if the working state of the physical layer is a busy state, gating the first data channel;
and if the working state of the physical layer is an idle state, gating the first data channel or the second data channel.
Optionally, the method further comprises:
when the second data channel is gated, configuring the second operation time sequence for the I/O interface so that the flash memory medium executes working characteristic setting operation according to the second operation time sequence;
and when the flash memory medium is detected to finish the operation of setting the working characteristics, gating a first data channel so that the physical layer can configure the first operation time sequence to the I/O interface.
Optionally, the method further comprises:
controlling the physical layer to configure a first operation time sequence or a second operation time sequence for the I/O interface through the first data channel; the operating clock frequency required by the second operating sequence is less than the operating clock frequency required by the physical layer to generate the first operating sequence.
Optionally, controlling the physical layer to configure the first operation timing or the second operation timing for the I/O interface through the first data channel includes:
determining a current operating clock frequency of the physical layer;
if the current working clock frequency is greater than a preset frequency switching threshold, controlling the physical layer to switch the current working clock frequency to a target working clock frequency, wherein the target working clock frequency is less than or equal to the preset frequency switching threshold;
when the target working clock frequency of the physical layer is detected to be continuously stable, controlling the physical layer to finish initialization operation;
when the physical layer finishes initialization operation, sending a flash memory operation command to the physical layer so that the physical layer configures a second operation time sequence for the I/O interface through the first data channel according to the flash memory operation command;
when the physical layer is detected to finish the configuration of the second operation time sequence, controlling the physical layer to be switched to a normal working clock frequency;
when the normal working clock frequency of the physical layer is detected to be continuously stable, controlling the physical layer to finish initialization operation;
and controlling the physical layer to configure a first operation time sequence for the I/O interface through the first data channel.
In a second aspect, an embodiment of the present invention provides a flash memory master control chip, including:
an I/O interface;
a multiplexer configured with a first data channel and a second data channel;
a physical layer to send a first operation timing to the I/O interface when the multiplexer gates the first data channel; and
and the controller is used for sending a gating instruction to the multiplexer according to the working state of the physical layer so as to enable the multiplexer to gate the input channel to which the gating instruction points, when the first data channel is gated, the physical layer can configure the first operation time sequence to the I/O interface, and when the second data channel is gated, the controller can configure the second operation time sequence to the I/O interface.
Optionally, the physical layer is connected to the I/O interface through the first data channel of the multiplexer, and the controller is connected to the I/O interface through the second data channel of the multiplexer.
In a third aspect, an embodiment of the present invention provides a method for testing a flash memory master control chip, including:
driving a controller of the flash memory main control chip to generate a test timing sequence signal;
acquiring an interface test signal output by the I/O interface in response to the test timing signal;
generating a test result according to the test time sequence signal and the interface test signal;
if the test time sequence signal is not consistent with the interface test signal, generating a test result for indicating the I/O interface to make a fault;
and if the test time sequence signal is consistent with the interface test signal, generating a test result for indicating that the I/O interface is correct and the physical layer is wrong.
In a fourth aspect, an embodiment of the present invention provides a method for testing a flash memory main control chip, including:
inputting a test timing signal at the I/O interface;
acquiring an interface test signal output by a controller of the flash memory main control chip in response to the test timing sequence signal;
generating a test result according to the test time sequence signal and the interface test signal;
if the test time sequence signal is not consistent with the interface test signal, generating a test result for indicating the I/O interface to make a fault;
and if the test time sequence signal is consistent with the interface test signal, generating a test result for indicating that the I/O interface is correct and the physical layer is wrong.
In a fifth aspect, an embodiment of the present invention provides a storage device, including the above flash memory master control chip.
Compared with the prior art, the flash memory master control chip, the control method thereof, the test method thereof and the storage device provided by the embodiments of the invention firstly determine the working state of the physical layer; then, according to the working state of the physical layer, an input channel is gated, wherein the input channel comprises a first data channel which can be configured by the physical layer to an I/O interface by a first operation time sequence, or a second data channel which can be configured by a controller connected with the physical layer to the I/O interface by a second operation time sequence, the I/O interface is used for connecting a flash memory medium, and any operation time sequence is used for controlling the flash memory medium. The flash memory main control chip is provided with a first data channel and a second data channel to coordinate operation of the flash memory medium, wherein the second data channel bypasses the physical layer and is directly generated by a controller to the I/O interface to operate the flash memory medium, so that the operation efficiency of the flash memory main control chip is improved.
Drawings
One or more embodiments are illustrated by way of example in the accompanying drawings, which correspond to the figures in which like reference numerals refer to similar elements and which are not to scale unless otherwise specified.
Fig. 1 is a schematic structural diagram of a storage device according to an embodiment of the present invention;
fig. 2 is a schematic flowchart illustrating a switching operation instruction according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a storage device according to an embodiment of the present invention;
fig. 4 is a flowchart of a control method for a flash memory main control chip according to an embodiment of the present invention;
fig. 5 is a schematic flowchart of a control method of a flash memory main control chip in the direct mode according to an embodiment of the present invention;
fig. 6 is a flowchart of a control method for a flash memory main control chip according to an embodiment of the present invention;
fig. 7 is a flowchart of an output path fault location method of a flash memory main control chip according to an embodiment of the present invention;
fig. 8 is a flowchart of an input path fault location method of a flash memory master control chip according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Referring to fig. 1, an embodiment of the present invention further provides a storage device, where the storage device 100 includes a flash memory main control chip 10 and a flash memory medium 20, and the flash memory main control chip 10 is connected to the flash memory medium 20 and is configured to access the flash memory medium 20 and manage various parameters and data I/O interfaces of the flash memory medium 20; or, an interface and a protocol for providing access, a corresponding SAS/SATA Target protocol end or NVMe protocol end is realized, an I/O instruction sent by Host is obtained, and the I/O instruction is decoded and an internal private data result is generated to wait for execution; or, the core processing module is used for the core processing of FTL (Flash translation layer).
The Flash memory medium 20, which is a storage medium of the storage device 100 and is also called a Flash memory, a Flash memory or a Flash granule, belongs to a type of storage device, and is a nonvolatile memory, which can store data for a long time without current supply, and has storage characteristics equivalent to a hard disk, so that the Flash memory medium 20 can become a basis of a storage medium of various portable digital devices.
In this embodiment, the Flash memory medium 20 is Nand Flash, which uses a single transistor as a storage unit of binary signals, and has a structure very similar to that of a common semiconductor transistor, except that the single transistor of Nand Flash adds a floating gate and a control gate, the floating gate is used for storing electrons, the surface of the floating gate is covered by a layer of silicon oxide insulator and is coupled with the control gate through a capacitor, when negative electrons are injected into the floating gate under the action of the control gate, the storage state of the single crystal of Nand Flash is changed from "1" to "0", and when the negative electrons are removed from the floating gate, the storage state is changed from "0" to "1", and the insulator covered on the surface of the floating gate is used for trapping the negative electrons in the floating gate, so as to realize data storage. That is, the NandFlash memory cell is a floating gate transistor, and data is stored in the form of charge using the floating gate transistor. The amount of stored charge is related to the magnitude of the applied voltage to the floating gate transistor, and specifically, whether the memory cell stores data therein depends on whether the voltage of the stored charge is greater than a predetermined voltage threshold Vth. A Nand Flash comprises at least one Chip, each Chip is composed of a plurality of Block physical blocks, and each Block physical Block comprises a plurality of Page pages. The Block physical Block is the minimum unit of Nand FLASH for executing the erasing operation, the Page is the minimum unit of Nand FLASH for executing the reading and writing operation, and the capacity of one Nand FLASH is equal to the number of the Block physical Block and the number of the Page contained in one Block physical Block and the capacity of one Page.
The flash memory master control chip 10 includes an I/O interface 11, a physical layer 13, and a controller 15. Specifically, the I/O interface 11 is connected to the flash memory medium 20, and configured to send an operation timing sequence to the flash memory medium 20, or receive feedback data returned by the flash memory medium 20 according to the operation timing sequence. For example, if the operation timing sequence is a read operation timing sequence, the I/O interface 11 outputs the read operation timing sequence to the flash memory medium 20, and the flash memory medium 20 returns corresponding feedback data according to the read operation timing sequence.
A physical layer 13, connected to the I/O interface 11, for generating an operation timing sequence and sending the operation timing sequence to the flash memory medium 20 through the I/O interface to operate the flash memory medium 20; alternatively, the data stored in the flash memory medium 20 is received through the I/O interface 11. It is understood that the operation sequence is a standard operation sequence, and the physical layer 13 generates a standard operation sequence of a corresponding mode according to an interface operation mode of the flash medium 20, for example, the interface operation mode is an asynchronous mode, an ONFI mode or a Toggle mode, so that the operation sequence can be accurately identified by the flash medium 20. Specifically, the operating clock frequency of the flash memory medium 20 is different in different interface operating modes. Further, in the same interface operation mode, the operation clock frequencies required for operating the flash memory medium 20 in different types of operation timings are also different.
The controller 15 is connected to the physical layer 13 and configured to output an operation instruction to the physical layer 13, so that the physical layer 13 generates a corresponding operation timing sequence according to the operation instruction; alternatively, the controller 15 is further configured to receive the data stored in the flash memory medium 20 acquired by the physical layer.
Specifically, the operation instruction includes a normal operation instruction, such as a read operation instruction or a write operation instruction; the operation instructions also include special operation instructions such as a Set Feature setting operation instruction for setting an operation Feature of the flash medium 20 such as Timing Mode or wakeup cycle operation Feature. It will be appreciated that the physical layer may require different operating clock frequencies depending on the different types of operating instructions. Therefore, the operating clock frequency needs to be switched before switching different types of operation instructions.
Specifically, referring to fig. 2, fig. 2 is a schematic flowchart of a switching operation instruction according to an embodiment of the present invention, and as shown in fig. 2, when the flash memory main control chip 10 is in a normal mode, the controller 15 sends a normal operation instruction to the physical layer 13; if the flash memory master control chip 10 needs to set the operating characteristics of the flash memory medium 20, the controller 15 sends a special operating instruction to the physical layer 13, and because the operating clock frequency of the normal operating instruction is different from the operating clock frequency of the special operating instruction, the current operating clock frequency of the physical layer 13 needs to be acquired before switching the operating instruction. Please refer to the following embodiments related to controlling the physical layer to configure the first operation timing sequence or the second operation timing sequence for the I/O interface through the first data channel, which is not described in detail herein.
In order to improve the operation performance of the flash memory medium 20 and improve the operation efficiency of the flash memory medium 20, in some embodiments, referring to fig. 3, the flash memory master control chip 10 further includes a multiplexer 12, the multiplexer is configured with a first data channel and a second data channel, the physical layer 13 is connected to the I/O interface through the first data channel of the multiplexer 12, and the controller 15 is connected to the I/O interface through the second data channel of the multiplexer 12.
The controller 15 is further configured to send a gating instruction to the multiplexer 12 according to the operating state of the physical layer 13, so that the multiplexer 12 gates the data channel to which the gating instruction points, when the first data channel is gated, the physical layer 13 may configure the first operation timing to the I/O interface 11, and when the second data channel is gated, the controller 15 may configure the second operation timing to the I/O interface 11.
It should be noted that, the first data channel and the second data channel may both be configured with a first operation timing sequence or a second operation timing sequence, and when the first data channel is configured with the second operation timing sequence, it needs to be switched to a corresponding operating clock frequency, which may specifically refer to the switching flow diagram shown in fig. 2.
Specifically, the gating instruction is used to instruct the flash memory main control chip 10 to operate in a corresponding operating mode, where the operating mode includes a normal mode and a direct mode.
When the working mode of the flash memory main control chip 10 is the normal mode, on one hand, the controller 15 sends a gating instruction to control the multiplexer 12 to gate a first data channel to receive an operation timing sequence, wherein an input end of the first data channel is connected with the physical layer 13; on the other hand, the physical layer 13 generates a first operation timing according to an operation instruction of the controller 15, and the first operation timing is output to the I/O interface 11 through the first data channel, so as to control the flash memory medium 20 connected to the I/O interface 11.
When the working mode of the flash memory main control chip 10 is the direct mode, on one hand, the controller 15 sends a gating instruction to control the multiplexer 12 to gate a second data channel to receive an operation timing sequence, wherein an input end of the second data channel is connected with the controller 15; on the other hand, the controller 15 generates a second operation timing and outputs the second operation timing to the I/O interface 11 through the second data channel, thereby controlling the flash memory medium 20 connected to the I/O interface 11.
Specifically, before switching the operating mode of the flash memory main control chip 10, the operating state of the physical layer 13 needs to be obtained, where the operating state includes a busy state and an idle state. When the working mode of the flash memory master control chip 10 is the normal mode, the working state of the physical layer 13 is acquired: if the operating state is the idle state, the controller 15 may send a gating instruction to the multiplexer 12, so that the data channel is switched from the first data channel to the second data channel, that is, the gating instruction is sent to switch the operating mode of the flash memory main control chip 10 from the normal mode to the direct mode; if the working state is a busy state, the controller 15 will wait until the working state of the physical layer 13 is changed from the busy state to an idle state, and then may send a gating instruction to the multiplexer 12, so that the data channel is switched from the first data channel to the second data channel.
In the embodiment of the present invention, the first data channel is specifically configured to transmit a general operation sequence to operate the flash memory medium 20, such as a read/write operation sequence, an erase operation sequence, and the like; the second data channel is specifically configured to transmit an operation Timing for setting an operating characteristic (Set Feature) to Set the operating characteristic of the flash memory medium 20, for example, to Set a Timing Mode or a wakeup Cycle operating characteristic of the flash memory medium 20.
In some embodiments, the first data channel may configure the first operation timing and the second operation timing at the same time, and the second data channel may also configure the first operation timing and the second operation timing at the same time. It is understood that when the operation timing is switched in the first data channel, the physical layer 13 generating the operation timing needs to be initialized.
In an embodiment of the present invention, a storage device is provided, where the storage device includes a flash memory main control chip, and the flash memory main control chip includes an I/O interface, a multiplexer, a physical layer, and a controller, and sends a gating instruction through the controller to gate a first data channel or a second data channel of the multiplexer to operate a flash memory medium, and further gates a corresponding input channel according to different operation timings of the flash memory medium, so as to improve an operation efficiency of the flash memory main control chip.
An embodiment of the present invention further provides a method for controlling a flash memory master control chip, which is applied to the storage device, to improve the operation performance of the flash memory medium 20 and improve the operation efficiency of the flash memory medium 20, and please refer to fig. 4, where the method includes:
s41, determining the working state of the physical layer;
the working state comprises a busy state and an idle state, and when the physical layer is in the busy state, the working state represents that the last operation sequence of the physical layer is not finished.
And S42, gating the data channel according to the working state of the physical layer. The data channel includes a first data channel in which the physical layer can configure a first operation timing to the I/O interface, or a second data channel in which a controller connected to the physical layer can configure a second operation timing to the I/O interface, the I/O interface is used for connecting a flash memory medium, and any operation timing is used for controlling the flash memory medium.
In this embodiment, the first data channel and the second data channel are configured by a multiplexer, and are used for transmitting a first operation timing sequence and/or a second operation timing sequence, and the first data channel and the second data channel share the same output channel for output.
Specifically, when the working state of the physical layer is an idle state, the controller sends a gating instruction to gate an input channel to which the gating instruction points, the gating instruction is used for switching the working mode of the flash memory main control chip, and the working mode includes a normal mode and a direct mode.
When the working mode is a normal mode, the controller sends a gating instruction to control the multiplexer to establish a control connection relation with the physical layer through a first data channel; the controller also sends an operation instruction to the physical layer so that the physical layer generates a first operation time sequence according to the operation instruction, and the first operation time sequence is output to the I/O interface through the first data channel so as to control a flash memory medium connected with the I/O interface.
When the working mode is a direct mode, the controller sends a gating instruction to control the multiplexer to gate a second data channel to receive an operation time sequence, wherein the input end of the second data channel is connected with the controller; the controller also generates a second operation timing sequence and outputs the second operation timing sequence to the I/O interface through the second data channel, thereby controlling the flash memory medium connected with the I/O interface 11.
In some embodiments, the corresponding data channel is gated according to the working state of the physical layer, specifically, if the working state of the physical layer is a busy state, the first data channel is gated; and if the working state of the physical layer is an idle state, gating the first data channel or the second data channel.
Specifically, according to the requirement of the controller, it is determined whether the operating mode needs to be switched, for example, the Read Retry gear of the flash memory medium needs to be adjusted, and then the controller needs to switch the operating mode to operate the flash memory medium, so as to improve the operating time.
Specifically, if it is determined that the working mode needs to be switched, the working state of the physical layer is obtained before switching, where the working state includes a busy state and an idle state. When the working mode is a normal mode, acquiring the working state of the physical layer: if the operating state is the idle state, the controller may send a gating instruction to the multiplexer to switch the data channel from the first data channel to the second data channel, that is, send a gating instruction to switch the operating mode from the normal mode to the direct mode. If the working state is a busy state, the controller waits until the working state of the physical layer is converted from the busy state to an idle state, and then can send a gating instruction to the multiplexer, so that the data channel is switched from the first data channel to the second data channel.
In actual operation, if the current connection channel is a first data channel and the working state of the physical layer is an idle state, the controller sends a gating instruction to the multiplexer according to a requirement, so that the input channel is switched from the first data channel to a second data channel. And if the working state of the physical layer is busy, the controller waits until the working state of the physical layer is converted from the busy state to the idle state, and then sends a gating instruction to the multiplexer to switch the input channel.
It is understood that when the controller does not need to switch the operation mode, the currently gated data channel of the multiplexer is the first data channel even though the current operation state of the physical layer is the idle state.
In an embodiment of the present invention, a method for controlling a flash memory master control chip is provided, where an input channel is gated by determining a working state of a physical layer and according to the working state of the physical layer, the input channel includes a first data channel in which the physical layer can configure a first operation timing to an I/O interface, or a controller connected to the physical layer can configure a second data channel in which a second operation timing to the I/O interface, the I/O interface is used for connecting a flash memory medium, and any operation timing is used for controlling the flash memory medium. The flash memory main control chip is provided with a first data channel and a second data channel to coordinate operation of the flash memory medium, wherein the second data channel bypasses the physical layer and is directly generated by a controller to the I/O interface to operate the flash memory medium, so that the operation efficiency of the flash memory main control chip is improved.
Continuing to refer to fig. 4, in some embodiments, the method further comprises:
s43, when the second data channel is selected, configuring the second operation time sequence for the I/O interface, so that the flash memory medium executes the operation of setting the working characteristics according to the second operation time sequence;
s44, when the flash memory medium is detected to finish the operation of setting the working characteristic, gating the first data channel, so that the physical layer can configure the first operation time sequence to the I/O interface.
Specifically, referring to fig. 5, the switching process of the working mode is as follows:
in the normal mode, if the working state of the physical layer acquired at the node S1 is an idle state, the controller sends a gating instruction to gate the second data channel, so that the multi-channel check device establishes a control connection with the controller, the working mode is switched from the normal mode to the direct mode, and the controller generates a second operation timing sequence to the flash memory medium to execute the setting of the working characteristics. At a node S2, if it is detected that the flash memory medium completes the setting of the operating characteristics according to the second operation timing sequence, the controller sends a gating instruction to gate the first data channel, so that the physical layer establishes a control connection with the multi-channel check device, the operating mode is switched from the direct mode to the normal mode, and the physical layer generates a first operation timing sequence according to the operation instruction of the controller to the flash memory medium to execute a NAND instruction.
In the embodiment of the invention, the controller switches the working mode through the channel instruction, executes the second operation time sequence to set the working performance of the flash memory medium in the direct mode, and switches the working mode from the direct mode to the normal mode when detecting that the flash memory medium finishes the working characteristic setting operation so as to execute the NAND instruction in the normal mode. That is, when the working performance of the flash memory medium is set, the physical layer is bypassed to execute the second operation sequence, so that the operation efficiency of the flash memory main control chip is improved.
In the present invention, the first operation timing is a standard operation timing for executing the NAND instruction, and the second operation timing is a setting timing for setting the operation performance of the flash memory medium. Referring to fig. 6, in some embodiments, controlling the physical layer to configure the first operation timing or the second operation timing for the I/O interface through the first data channel includes:
s61, determining the current working clock frequency of the physical layer;
it can be understood that, before determining the current operating clock frequency of the physical layer, the operating state of the physical layer needs to be obtained first, and if the operating state of the physical layer is an idle state, the current operating clock frequency of the physical layer is further determined; and if the working state of the physical layer is busy, waiting until the working state of the physical layer is converted into an idle state, and further determining the current working clock frequency of the physical layer.
S62, if the current working clock frequency is larger than a preset frequency switching threshold, controlling the physical layer to switch the current working clock frequency to a target working clock frequency, wherein the target working clock frequency is smaller than or equal to the preset frequency switching threshold;
s63, when the target working clock frequency of the physical layer is detected to be continuously stable, controlling the physical layer to finish initialization operation;
s64, when the physical layer completes initialization operation, sending a flash memory operation command to the physical layer, so that the physical layer configures a second operation time sequence for the I/O interface through the first data channel according to the flash memory operation command;
wherein the second operation timing is used to set an operating characteristic of the flash memory medium.
S65, when detecting that the physical layer is configured with the second operation time sequence, controlling the physical layer to switch to a normal working clock frequency;
s66, when the normal working clock frequency of the physical layer is detected to be continuously stable, controlling the physical layer to finish initialization operation;
s67, controlling the physical layer to configure a first operation timing sequence for the I/O interface through the first data channel.
Wherein the first timing of operations is for executing a NAND instruction.
In some embodiments, an operating clock frequency required by the physical layer to generate the second operational timing is less than an operating clock frequency required by the physical layer to generate the first operational timing. Such as Toshiba flash memory particles, which operate at a clock frequency above 133MHz when executing NAND instructions, but which do not operate at a clock frequency above 133MHz when executing the operational performance setting (SetFeature) of Toshiba flash memory particles.
In an embodiment of the present invention, a control method of a flash memory master control chip is further provided, where a first operation timing sequence or a second operation timing sequence is configured for the I/O interface through controlling the physical layer through the first data channel, so as to operate a flash memory medium connected to the I/O interface.
Referring to fig. 7, an embodiment of the present invention further provides a method for testing a flash memory master control chip, where the method is used to locate a fault point of an output channel in the flash memory master control chip, where the fault point includes a physical layer fault or an I/O interface fault, and the method includes:
s71, driving a controller of the flash memory main control chip to generate a test timing signal;
s72, acquiring an interface test signal output by the I/O interface in response to the test timing signal;
specifically, the test timing signal is generated by driving the controller with an external test device, the external test device is further connected to the I/O interface, and receives the test timing signal output by the I/O interface in response to the test timing signal, and the external test device includes an oscilloscope, a logic analyzer, or a multimeter.
And S73, generating a test result according to the test timing sequence signal and the interface test signal.
S731, if the test timing sequence signal is inconsistent with the interface test signal, generating a test result for indicating that the I/O interface is faulty;
s732, if the test timing signal is consistent with the interface test signal, generating a test result for indicating that the I/O interface is correct and the physical layer is faulty.
Before executing the test method, the working mode of the flash memory main control chip is switched to a direct working mode, and the parameter of the I/O interface is set as an output attribute, so that the test time sequence signal is output to the I/O interface through the second data channel. Specifically, the process of locating the fault of the output path specifically includes: on one hand, the external test equipment drives a controller of the flash memory main control chip to generate a test time sequence signal, the controller generates the test time sequence signal and outputs the test time sequence signal to the I/O interface through the second data channel, and the I/O interface responds to the test time sequence signal to output an interface test signal. On the other hand, the external test equipment is further connected to the I/O interface, acquires an interface test signal output by the I/O interface, and compares the test timing signal with the interface test signal, if the test timing signal is consistent with the interface test signal, it indicates that the test timing signal can be accurately output through the I/O interface, and the test result is: the I/O interface is smooth, and the physical layer fails; if the test timing signals are inconsistent, the test timing signals cannot be accurately output through the I/O interface, and the test result is as follows: the I/O interface fails.
In the embodiment of the invention, when the working mode is a direct mode, a test time sequence signal is generated to the I/O interface through the controller, the I/O interface outputs an interface test signal according to the test time sequence signal, if the test time sequence signal is consistent with the interface test signal, the I/O interface is smooth, and the physical layer breaks down; otherwise, the I/O interface fails, and further the output channel fault of the flash memory main control chip is accurately positioned.
Referring to fig. 8, an embodiment of the present invention further provides a method for testing a flash memory master control chip, where the method is used to locate a failure point of an input channel in the flash memory master control chip, where the failure point includes a physical layer failure or an I/O interface failure, and the method includes:
s81, inputting a test time sequence signal at the I/O interface;
s82, acquiring an interface test signal output by the controller of the flash memory master control chip in response to the test timing signal;
and S83, generating a test result according to the test timing sequence signal and the interface test signal.
S831, if the test timing sequence signal is not consistent with the interface test signal, generating a test result for indicating the I/O interface to make a mistake;
s832, if the test timing signal is consistent with the interface test signal, generating a test result indicating that the I/O interface is correct and the physical layer is faulty.
Before executing the test method, the working mode of the flash memory main control chip is switched to a direct working mode, and the parameter of the I/O interface is set as an input attribute, so that the test time sequence signal input by the I/O interface is output through the second data channel. Specifically, the input path fault location process is as follows: in one aspect, an external test device outputs a test timing signal to the I/O interface, the test timing signal being output to the controller through a second data channel, the controller outputting an interface test signal in response to the test timing signal. On the other hand, the external test equipment is also connected with the controller, acquires the interface test signal output by the controller, and compares the test timing sequence signal with the interface test signal. If the test timing sequence signals are consistent with the test timing sequence signals, the test timing sequence signals can be accurately input through the I/O interface, and the test result is as follows: the I/O interface is smooth, and the physical layer fails; if the test timing signals are inconsistent, the test timing signals cannot be accurately input through the I/O interface, and the test result is as follows: the I/O interface fails.
In the embodiment of the invention, when the working mode is a direct mode, a test time sequence signal is configured to be input at an I/O interface, the I/O interface outputs an interface test signal according to the test time sequence signal, and if the test time sequence signal is consistent with the interface test signal, the I/O interface is smooth and a physical layer fails; otherwise, the I/O interface fails, and further the input channel fault of the flash memory main control chip is accurately positioned.
The above-described embodiments of the apparatus or device are merely illustrative, wherein the unit modules described as separate parts may or may not be physically separate, and the parts displayed as module units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network module units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment.
Through the above description of the embodiments, it is clear to those skilled in the art that each embodiment can be implemented by software plus a general hardware platform, and can also be implemented by hardware. Moreover, since the concept of the random encoding apparatus is the same as that of the random encoding method described in the above embodiments, the contents of the above embodiments may be referred to in the embodiments of the random encoding apparatus without conflicting with each other, and are not described herein again.
Embodiments of the present invention provide a non-transitory computer-readable storage medium having stored thereon computer-executable instructions for execution by one or more processors, e.g., to perform the method steps of fig. 4-6 described above.
Embodiments of the present invention provide a computer program product comprising a computer program stored on a non-transitory computer readable storage medium, the computer program comprising program instructions which, when executed by a computer, cause the computer to perform the random encoding method in any of the method embodiments described above, for example, to perform the method steps of fig. 4 to 6 described above.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; within the idea of the invention, also technical features in the above embodiments or in different embodiments may be combined, steps may be implemented in any order, and there are many other variations of the different aspects of the invention as described above, which are not provided in detail for the sake of brevity; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (10)
1. A flash memory master control chip control method is characterized by comprising the following steps:
determining the working state of a physical layer;
according to the working state of the physical layer, an input channel is gated, wherein the input channel comprises a first data channel which can be configured by the physical layer to an I/O interface by a first operation time sequence, or a second data channel which can be configured by a controller connected with the physical layer to the I/O interface by a second operation time sequence, the I/O interface is used for connecting a flash memory medium, and any operation time sequence is used for controlling the flash memory medium.
2. The method of claim 1, wherein the operating states comprise a busy state and an idle state, and wherein gating the input channel according to the operating state of the physical layer comprises:
if the working state of the physical layer is a busy state, gating the first data channel;
and if the working state of the physical layer is an idle state, gating the first data channel or the second data channel.
3. The method of claim 2, further comprising:
when the second data channel is gated, configuring the second operation time sequence for the I/O interface so that the flash memory medium executes working characteristic setting operation according to the second operation time sequence;
and when the flash memory medium is detected to finish the operation of setting the working characteristics, gating a first data channel so that the physical layer can configure the first operation time sequence to the I/O interface.
4. The method of any of claims 1 to 3, further comprising:
and controlling the physical layer to configure a first operation time sequence or a second operation time sequence for the I/O interface through the first data channel, wherein the working clock frequency required by the second operation time sequence is less than the working clock frequency required by the first operation time sequence.
5. The method of claim 4, wherein controlling the physical layer to configure the I/O interface with the first operational timing or the second operational timing via the first data channel comprises:
determining a current operating clock frequency of the physical layer;
if the current working clock frequency is greater than a preset frequency switching threshold, controlling the physical layer to switch the current working clock frequency to a target working clock frequency, wherein the target working clock frequency is less than or equal to the preset frequency switching threshold;
when the target working clock frequency of the physical layer is detected to be continuously stable, controlling the physical layer to finish initialization operation;
when the physical layer finishes initialization operation, sending a flash memory operation command to the physical layer so that the physical layer configures a second operation time sequence for the I/O interface through the first data channel according to the flash memory operation command;
when the physical layer is detected to finish the configuration of the second operation time sequence, controlling the physical layer to be switched to a normal working clock frequency;
when the normal working clock frequency of the physical layer is detected to be continuously stable, controlling the physical layer to finish initialization operation;
and controlling the physical layer to configure a first operation time sequence for the I/O interface through the first data channel.
6. A flash memory master control chip, comprising:
an I/O interface;
a multiplexer configured with a first data channel and a second data channel;
a physical layer to send a first operation timing to the I/O interface when the multiplexer gates the first data channel; and
and the controller is used for sending a gating instruction to the multiplexer according to the working state of the physical layer so as to enable the multiplexer to gate the input channel to which the gating instruction points, when the first data channel is gated, the physical layer can configure the first operation time sequence to the I/O interface, and when the second data channel is gated, the controller can configure the second operation time sequence to the I/O interface.
7. The chip of claim 6, wherein the physical layer is coupled to the I/O interface via the first data channel of the multiplexer, and wherein the controller is coupled to the I/O interface via the second data channel of the multiplexer.
8. A method for testing a flash memory master control chip is characterized by comprising the following steps:
driving a controller of the flash memory main control chip to generate a test timing sequence signal;
acquiring an interface test signal output by the I/O interface in response to the test timing signal;
generating a test result according to the test time sequence signal and the interface test signal;
if the test time sequence signal is not consistent with the interface test signal, generating a test result for indicating the I/O interface to make a fault;
and if the test time sequence signal is consistent with the interface test signal, generating a test result for indicating that the I/O interface is correct and the physical layer is wrong.
9. A method for testing a flash memory master control chip is characterized by comprising the following steps:
inputting a test timing signal at an I/O interface;
acquiring an interface test signal output by a controller of the flash memory main control chip in response to the test timing sequence signal;
generating a test result according to the test time sequence signal and the interface test signal;
if the test time sequence signal is not consistent with the interface test signal, generating a test result for indicating the I/O interface to make a fault;
and if the test time sequence signal is consistent with the interface test signal, generating a test result for indicating that the I/O interface is correct and the physical layer is wrong.
10. A memory device comprising the flash memory master chip of claim 6 or 7.
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