CN109213438A

CN109213438A - The storage device of the physical address to be allocated to write-in data is managed in advance

Info

Publication number: CN109213438A
Application number: CN201810620067.3A
Authority: CN
Inventors: 李永根; 金镇佑; 金暎植; 金焕忠; 赵廷勋
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2017-07-03
Filing date: 2018-06-15
Publication date: 2019-01-15
Also published as: DE102018110704A1; US10635349B2; KR20190004402A; US20190004736A1; KR102398181B1

Abstract

A kind of storage device includes nonvolatile memory and controller.Before controller receives the first write-in data, controller manages the corresponding relationship between the physical address and flow identifier of instruction storage region in advance.Controller controls nonvolatile memory, so that the first write-in data are stored in the first storage region, manages to the first flow identifier corresponding to the first write-in data in corresponding relationship the physical address of first storage region.No matter whether controller receives the second write-in data with the second flow identifier, and the first write-in data are transferred to nonvolatile memory based on corresponding relationship.

Description

The storage device of the physical address to be allocated to write-in data is managed in advance

Cross reference to related applications

This application claims submit to the South Korea patent application No.10-2017- of Korean Intellectual Property Office on July 3rd, 2017 0084233 priority, the disclosure of which are incorporated herein by quoting its whole.

Technical field

This disclosure relates to a kind of electronic device, and more particularly, to the behaviour of storage and the storage device of output data Make and configures.

Background technique

In recent years, various types of electronic devices are used.Electronic device is according to the electronic circuit being included therein It operates to execute the function of their own.Storage device is an example of electronic device.Storage device includes for storing data Memory device.Memory device storage or output data, therefore storage device provides a user storage service.

Meanwhile as storage device is widely used in many people, and data volume gradually increases, to high-performance and high reliability Storage device increase in demand.In addition, to the height of abundant service is provided while using a small amount of resource in storage device The demand of effect storage device also increases.

For example, storage device may include the various electronic circuits for managing data flow.The electronic circuit of storage device Data can be handled by using the resource of storage device, or information needed for can store data processing.When handling Data volume when increasing, stock number (for example, computing capability and/or buffer capacity etc.) needed for storage device also increases.So And vast resources can reduce the efficiency of storage device, and will increase the cost of manufacture storage device.

Summary of the invention

Each example embodiment of the disclosure can provide the storage dress that data flow can be managed using a small amount of resource The configuration and operation set.In the example embodiment of the disclosure, storage device can be before receiving write-in data from host, pipe Reason will be the physical address of write-in data distribution.In some example embodiments, storage device can be with centralized architecture come real It is existing, or can be realized with hardware automated framework.

In some example embodiments, storage device may include each nonvolatile memory and controller.It is non-volatile Property memory may include each storage region.Controller can be communicated by multiple channels with nonvolatile memory.It is controlling Before device receives the first write-in data, controller can manage in advance instruction storage region physical address and flow identifier it Between corresponding relationship.Controller can control nonvolatile memory, so that the first write-in data are stored in the first memory block In domain, the object of first storage region is correspondingly managed with the first flow identifier of the first write-in data in corresponding relationship Manage address.No matter whether controller receives the second write-in data with the second flow identifier, and can be based on corresponding relationship will First write-in data are transferred to nonvolatile memory.

In some example embodiments, storage device may include each nonvolatile memory, buffer storage and control Device processed.Nonvolatile memory may include storage region.Buffer storage can buffer nonvolatile memory to be stored in In first write-in data and second write-in data.Controller can be communicated with nonvolatile memory and buffer storage, be made It obtains the first write-in data and the second write-in data is stored in nonvolatile memory.The first write-in number with the first characteristic It can according to the second write-in data in the first storage region that can be stored in nonvolatile memory, and with the second characteristic To be stored in the second storage region of nonvolatile memory.No matter whether the second write-in data are buffered in buffer-stored In device, the be buffered in buffer storage first write-in data can be transferred to nonvolatile memory.

In some example embodiments, storage device may include nonvolatile memory and controller.It is non-volatile to deposit Reservoir may include storage region.Controller can control nonvolatile memory, so that the first write-in data are stored in and are connecing It is just determined in advance before receiving the first write-in data in the storage region of storage the first write-in data.In spite of connecing The second write-in data are received, the first write-in data can be transferred to nonvolatile memory.

In some example embodiments, storage device may include nonvolatile memory and controller.It is non-volatile to deposit Reservoir may include storage region.Controller may include job management circuit and processor.Job management circuit can manage Write operation, so that the with the first flow identifier first write-in data are stored in the first memory block of nonvolatile memory In domain, and the with the second flow identifier second write-in data are stored in the second storage region of nonvolatile memory In.Processor can be managed operation, to solve mistake associated with write operation or abnormal.Job management circuit can To manage write operation in the case where non-processor intervenes.No matter whether controller receives the second write-in data, can incite somebody to action Nonvolatile memory is transferred to by the first write-in data that controller receives.

According to an example embodiment of the present disclosure, write-in data can be stored in pre- before receiving write-in data from host It is first assigned in the storage region of physical address.Therefore, storage device can manage write-in data in the buffer of low capacity. May be implemented include low capacity buffer storage device, therefore the efficiency of managing storage can be improved, and can drop The cost of low manufacture storage device.

In the exemplary embodiment, storage device includes nonvolatile memory and Memory Controller.Memory Controller Perform the following operation: (1) mutual exclusion generated between the physical address and flow identifier of nonvolatile memory is associated with, and (2) are from master Machine device receives the first order with for data associated with the first flow identifier among each flow identifier to be written, and (3) the receive from host apparatus second order is transmitted to the first non-volatile memories among each nonvolatile memory Device, second order is including the first physical address associated with the first flow identifier among each physical address and wait store Data at first physical address.

Detailed description of the invention

Referring to the following drawings, above and other object and feature be will become obvious, wherein unless otherwise indicated, no Then identical appended drawing reference refers to identical part in various figures, in figure:

Fig. 1 is the block diagram for showing the electronic system including storage device according to some example embodiments；

Fig. 2 is the block diagram for showing the example arrangement of storage device of Fig. 1；

Fig. 3 is the block diagram for the example arrangement for describing the memory device of Fig. 2 according to some example embodiments；

Fig. 4 and Fig. 5 is the concept for the example arrangement for describing the memory device of Fig. 2 according to some example embodiments Figure；

Fig. 6 is the block diagram for describing the example write operation in the storage device of Fig. 2；

Fig. 7 is the example write operation for describing to execute in the storage device according to Fig. 2 of some example embodiments Block diagram；

Fig. 8 is the process of the example write operation executed in the storage device described according to Fig. 2 of some example embodiments Figure；

Fig. 9 is the interleaving access by multiple channels for describing the example write operation about Fig. 7 and Fig. 8 (interleving) flow chart；

Figure 10 is the concept map transmitted for describing the time-division multiplex of the example write operation about Fig. 7 and Fig. 8；

Figure 11 is the block diagram for showing the example arrangement of storage device of Fig. 1；

Figure 12 and Figure 13 is the frame for the exemplary operations for describing the storage device of Figure 11 according to some example embodiments Figure；

Figure 14 is the block diagram for showing the example arrangement and exemplary operations of the controller of Figure 11 according to some example embodiments；

Figure 15 is the concept map for showing the example arrangement of data packet of Figure 14 according to some example embodiments；

Figure 16 to Figure 18 is that the example for describing to execute in the storage device according to Figure 11 of some example embodiments is write Enter the block diagram of operation；

Figure 19 is the stream of the example write operation executed in the storage device described according to Figure 11 of some example embodiments Cheng Tu；And

Figure 20 is the block diagram for showing the example arrangement of storage device of Fig. 1.

Specific embodiment

Hereinafter, in detail and be explicitly described some example embodiments with reference to the accompanying drawings, so that those skilled in the art can be with Easily realize the disclosure.

I. example electronic system associated with the disclosure

Fig. 1 is the example arrangement for showing the electronic system 1000 including storage device 1300 according to some example embodiments Block diagram.

Electronic system 1000 may include primary processor 1101, working storage 1200, storage device 1300, communication module 1400, user interface 1500 and bus 1600.For example, electronic system 1000 can be such as desktop computer, calculating on knee Machine, tablet computer, smart phone, wearable device, video game console, work station, server, electric vehicle, household electric One of the electronic equipment of device and/or medical instrument etc..

Primary processor 1101 can control the integrated operation of electronic system 1000.Primary processor 1101 can handle various calculations Art operation and/or logical operation.For this purpose, primary processor 1101 may include special circuit (for example, field programmable gate array (FPGA) and/or special integrated chip (ASIC) etc.).For example, primary processor 1101 may include one or more processors core, And it can be realized with general processor, application specific processor or application processor.

Working storage 1200 can store will the data used in the operation of electronic system 1000.For example, work is deposited Reservoir 1200 can temporarily store the data handled by primary processor 1101 or to be handled by primary processor 1101.For example, work Memory 1200 may include the volatibility of dynamic random access memory (DRAM) and/or synchronous dram (SDRAM) etc. Memory and/or such as phase transformation RAM (PRAM), magnetic resistance RAM (MRAM), resistance RAM (ReRAM) and/or ferroelectric RAM (FRAM) Nonvolatile memory etc..

Storage device 1300 may include one or more memory devices and controller.The memory of storage device 1300 Device can store data, but regardless of supply electric power how.For example, storage device 1300 may include non-volatile memories Device, flash memory, PRAM, MRAM, ReRAM and/or FRAM etc..For example, storage device 1300 may include such as solid-state driving The storage medium of device (SSD), card memory and/or in-line memory etc..

Communication module 1400 can be communicated with the device/system outside electronic system 1000.For example, communication module 1400 can support various wireless communication protocols (such as long term evolution (LTE), World Interoperability for Microwave Access, WiMax (WIMAX), complete It ball mobile communication system (GSM), CDMA (CDMA), bluetooth, near-field communication (NFC), Wireless Fidelity (Wi-Fi) and/or penetrates Frequency identification (RFID)) etc.) at least one of, and/or various wired communication protocols (such as transmission control protocol/internet protocol At least one of view (TCP/IP), universal serial bus (USB) and/or Firewire etc.).

User interface 1500 can arbitrate the communication between user and electronic system 1000.For example, user interface 1500 can To include input interface, such as keyboard, keypad, button, touches plate, touches screen, touch tablet, touches ball, photograph mouse Machine, microphone, gyro sensor and/or vibrating sensor etc..For example, user interface 1500 may include output interface, it is all Such as liquid crystal display (LCD) device, light emitting diode (LED) display device, organic LED (OLED) display device, active matrix OLED (AMOLED) display device, loudspeaker, motor and/or LED light etc..

Bus 1600 can provide the communication path between each component of electronic system 1000.The each group of electronic system 1000 Part can the bus format based on bus 1600 it is exchanging data with one another.For example, bus format may include various interface protocols (such as USB, small computer system interface (SCSI), peripheral component interconnection high speed (PCIe), mobile PC Ie (M-PCIe), advanced techniques Attachment (ATA), Parallel ATA (PATA), serial ATA (SATA), Serial Attached SCSI (SAS) (SAS), integrated drive electronics (IDE), enhanced IDE (EIDE), flash non-volatile memory (NVMe) and/or Common Flash Memory (UFS) etc.) one of or It is a variety of.

Storage device 1300 can be realized based on the example embodiment of the disclosure.Before receiving write-in data, deposit Storage device 1300 can manage the physical address that distribute to write-in data in advance.According to example embodiment, storage device 1300 The write-in data in low capacity buffer can be managed.It is thus possible to improve the efficiency of managing storage 1300, and can be with Reduce the cost of manufacture storage device 1300.The example arrangement and example of storage device 1300 will be described referring to Fig. 2 to Figure 20 Operation.

Can storage device 1300 be provided as example in the following description.However, the present disclosure is not limited thereto.Example is implemented Example can be applied to include memory device any kind of device.For example, example embodiment even can be applied to include Volatile memory and/or nonvolatile memory in working storage 1200.Offer is described below more preferable to facilitate Understanding, and be not intended to be limited to the disclosure.

II-A. centralized architecture

Fig. 2 is the block diagram for showing the example arrangement of storage device 1300 of Fig. 1.The electronic system 1000 of Fig. 1 may include The electronic system 1000a of Fig. 2.The storage device 1300 of Fig. 1 may include the storage device 1300a of Fig. 2.

As described with reference to Fig. 1, primary processor 1101 can be communicated by bus 1600 with storage device 1300a.In this public affairs In opening, it is able to access that the object of storage device 1300 can be referred to as " host " 1100a.Primary processor 1101, which can be, to be made For the example of the object of host 1100a operation.However, the present disclosure is not limited thereto.

Host 1100a can exchange data DAT with storage device 1300a.Storage device 1300a can be in response to from host The order CMD that 1100a is received provides storage service to host 1100a.

For example, host 1100a can provide writing commands and write-in data to storage device 1300a.Storage device 1300a Requested write-in data can be stored in response to writing commands.For example, host 1100a can be mentioned to storage device 1300a For reading order.Storage device 1300a can export requested reading data to host 1100a in response to reading order.

Storage device 1300a may include one or more memory devices 1310 and controller 1330a.Although Fig. 2 shows Two memory devices 1311 and 1319 are gone out, but the quantity for the memory device being included in storage device 1300a can be with Differently it is altered or modified.

Each of memory device 1311 and 1319 can store or export the data requested by host 1100a.For This, each memory device 1311 and 1319 may include memory block for storing data.For example, working as memory device 1311 When with each of 1319 including NAND-type flash memory, each of memory device 1311 and 1319 may include along more The array for the storage unit that a wordline and multiple bit lines are formed, and can be for the operation of memory device 1311 and 1319 It is executed on the memory block of page unit or module unit.However, as described with reference to fig. 1, it is every in memory device 1311 and 1319 One type and configuration can be differently altered or modified.

Memory block can be identified and indicated based on the value for being referred to as " address ".Write-in data can be stored in by address In the memory block of instruction, and it can be exported from the memory block indicated by address and read data.

Host 1100a can provide address AD DR to storage device 1300a, to exchange about 1311 He of memory device The data of 1319 specific memory section.Storage device 1300a can be based on from the received address AD DR of host 1100a and request (for example, order CMD), to control memory device 1311 and 1319.

Meanwhile the address AD DR handled by host 1100a can be different from instruction memory device 1311 and 1319 The address of memory block.For example, the address AD DR handled by host 1100a can be referred to as " logical address ", and memory device 1311 and 1319 address can be referred to as " physical address ".Storage device 1300a can be executed to be patrolled by what host 1100a was handled The address conversion between address and memory device 1311 and 1319 physical address is collected, to suitably control memory device 1311 and 1319.

Controller 1330a can control the integrated operation of storage device 1300a.It is deposited for example, controller 1330a can be dispatched The operation of reservoir device 1311 and 1319, or coding reconciliation can be carried out to the signal/data handled in storage device 1300a Code.For example, controller 1330a can control memory device 1311 and 1319, so that memory device 1311 and 1319 stores Or output data.

Controller 1330a may include be configured as executing some operations that is described above and will be described below one A or multiple hardware components (for example, analog circuit and/or logic circuit etc.).In addition, controller 1330a may include one Or multiple processing cores.The described above and some operations of controller 1330a that will be described below can with software and/or The program code of firmware is realized, and (one or more) processing core of controller 1330a can execute the finger of program code Enable collection.(one or more) processing core of controller 1330a can handle various arithmetical operations and/or logical operation is referred to executing Enable collection.

Buffer storage 1350a can be buffered in data used in the operation of storage device 1300a.For example, buffering is deposited Reservoir 1350a can temporarily store the data quoted by controller 1330a.For example, buffer storage 1350a may include volatile Property memory (such as, static RAM (SRAM), DRAM and/or SDRAM etc.) and/or nonvolatile memory (such as flash memory, PRAM, MRAM, ReRAM and/or FRAM etc.).

In the example arrangement of Fig. 2, the processing core of controller 1330a can be intervened to be executed in storage device 1300a Various operations, including transmission write-in data and reading data.In addition, buffer storage 1350a can store for controller Various metadata cited in the operation of 1330a and the write-in data that be stored in memory device 1311 and 1319 and The reading data exported from memory device 1311 and 1319.It is understood, therefore, that utilization " centralized architecture " (for example, It is according to the control of controller 1330a by centralization) realize the example storage devices 1300a of Fig. 2.

II-B. the management of multithread and storage region

Fig. 3 be for describe be according to some example embodiments the example arrangement of the memory device 1310 of Fig. 2 block diagram. Fig. 4 and Fig. 5 is the concept map for describing the example arrangement of the memory device 1310 according to Fig. 2 of some example embodiments. For example, including four memory devices 1311,1312,1313 and 1319 by description storage device 1300a.However, providing this Example be in order to make it easy to understand, and the quantity of memory device can be differently altered or modified.

In some example embodiments, storage device 1300a can manage data flow according to multi-stream scheme.For example, stream It can be associated with data characteristic.Host 1100a can be flowed by one by several datas with same or similar characteristic It is transferred to storage device 1300a.On the other hand, host 1100a can be by different stream by several with different characteristics Data are transferred to storage device 1300a.

For example, system data can separate to transmit by a stream with user data.For example, raw within the same period At several datas with the data generated in different time period can separate to transmit by a stream.For example, by same Several datas that user generates can separate to transmit by a stream with the data generated by different user.These only with The relevant some examples of data characteristic, and can based on such as operation strategy of host 1100a and storage device 1300a and/ Or user the various factors such as is intended to and is altered or modified data characteristic.

It can be based on distributing to the flow identifier of data come processing stream.It can be failed to be sold at auction based on data characteristic differently to distribute Know symbol.For example, referring to Fig. 3, writing for the flow identifier with institute's reference numerals can be indicated by the shaded square of numeral mark Enter data.For example, several datas with flow identifier " 1 " can have the same or similar characteristic, and flow identifier It can be different from the characteristic for the data that flow identifier is " 2 " for the characteristic of the data of " 1 ".

For example, the description that four flow identifiers of processing will be provided.In this example, controller 1330a can be considered four A different data characteristic manages data flow.But it is to provide this example and is in order to make it easy to understand, and characteristic and traffic identifier The quantity of symbol can be differently altered or modified.

Each of memory device 1311,1312,1313 and 1319 may include memory block.For example, memory device Setting 1311 may include memory block MA11 to MA14.Similarly, memory device 1312,1313 and 1319 can respectively include storing Area MA21 to MA24, memory block MA31 to MA34 and memory block MA41 to MA44.

For example, memory block MA11 can be with to MA14, MA21 to MA24, MA31 each of to MA34 and MA41 to MA44 Corresponding to block size area, and the present disclosure is not limited to the examples.Memory block MA11 to MA14, MA21 to MA24, MA31 to MA34 It can be differently altered or modified with MA41 to MA44, to not overlap each other.Memory block MA11 to MA14, MA21 are arrived MA24, MA31 to MA34 and MA41 to MA44 can have identical size or different sizes.

Although it includes four memory blocks that Fig. 3, which shows each memory device all, the present disclosure is not limited to Fig. 3 institutes Show.The size and number for the memory block for including in each memory device can be differently altered or modified.Each memory The size and number for the memory block for including in device can be identical or different.

Each of memory device 1311,1312,1313 and 1319 may be coupled in multiple channel C H1 to CH4 A channel.Therefore, each of memory block MA11 to MA14, MA21 to MA24, MA31 to MA34 and MA41 to MA44 It may be coupled to one in channel C H1 to CH4.Controller 1330a can pass through channel C H1 to CH4 and memory device 1311,1312,1313 and 1319 communication.Channel C H1 to CH4 may include physical circuit, such as conducting wire and buffer circuit, thus Data are transmitted between controller 1330a and memory device 1311,1312,1313 and 1319.

Memory device 1311,1312,1313 and 1319 may include storage region MR1 to MR4.Storage region MR1 is extremely Each of MR4 may include at least one memory block.Storage region MR1 to MR4 can not overlap each other.Therefore, respectively Including can be different in memory block of the storage region MR1 into MR4.For example, each memory block for including in storage region MR1 can be with From include that each memory block in storage region MR2 is different.

Storage device 1300a can several defeated write-ins be spread in storage by difference respectively in different storage regions Data.On the other hand, storage device 1300a can by by one spread it is defeated come several write-in data be collectively stored in phase In same storage region.For example, several write-in data with flow identifier " 1 " can be collectively stored in storage region MR1 In.On the other hand, the write-in data with flow identifier " 2 " can be stored in the storage region separated with storage region MR1 In MR2, and it can be not stored in storage region MR1.

Therefore, a storage region can store several write-in data with same or similar characteristic.For example, having The write-in data (for example, write-in data with flow identifier " 1 ") of first characteristic can be merely stored in storage region MR1, And the write-in data (for example, being the write-in data of " 2 " with flow identifier) with the second characteristic can be merely stored in storage In the MR2 of region.

According to such multi-stream scheme, if can manage together in same storage region has same or similar characteristic Data are written in dry item.Therefore, it can improve and distribute the efficiency of new storage region for write-in data, and therefore can improve and write Enter the performance of operation.Furthermore it is possible to reduce time of the garbage collection operations of the page and protection free page for restoring invalid data Number, the garbage collection operations, and therefore can prevent the service life of storage device 1300a from shortening rapidly.

The configuration of storage region MR1 to MR4 can be differently altered or modified.Storage region MR1 is each into MR4 A may include from least one memory block in each memory block for be connected to same channel in choosing.Meanwhile storage region MR1 is extremely MR4 can respectively include the different memory blocks chosen from each memory block for being connected to same channel.

For example, storage region MR1 may include the memory block MA11 for being connected to channel C H1.When memory block MA11 is included When in storage region MR1, memory block MA11 can be not included in storage region MR2.On the contrary, storage region MR2 can be with Memory block MA12 including being connected to channel C H1.In this way, storage region MR1 to MR4 can not overlap each other.

It is every into MR4 it can be optionally comprised in storage region MR1 in association with all or part of channel C H1 to CH4 Memory block in one.Therefore, each of storage region MR1 to MR4 may include being respectively connected to all or part of lead to Each memory block of road CH1 to CH4.

For example, referring to Fig. 4, each of storage region MR1 to MR4 may include related to all channel C H1 to CH4 Each memory block of connection ground selection.For example, storage region MR1 may include being connected respectively to depositing for channel C H1, CH2, CH3 and CH4 Storage area MA11, MA21, MA31 and MA41.

For example, referring to Fig. 5, each storage region MR1a, MR3a and MR4a may include with channel C H1 into CH4 one Each memory block selected in association a bit.For example, storage region MR1a may include being connected respectively to depositing for channel C H1 and CH2 Storage area MA11 and MA21, and can not include any memory block selected in association with channel C H3 and CH4.Meanwhile it storing Region MR2a may include each memory block selected in association with all channel C H1 to CH4.

Each of storage region MR1a to MR4a may include at least one memory block for being connected to same channel.Example Such as, storage region MR1a may include a memory block for being connected to channel.On the other hand, storage region MR2a, MR3a and Each of MR4a may include the multiple memory blocks for being connected to same channel.For example, storage region MR1a may include connecting It is connected to a memory block MA11 of channel C H1, and storage region MR3a may include two memory blocks for being connected to channel C H1 MA13 and MA14.

Fig. 4 and Fig. 5 shows some possible configurations of storage region MR1 to MR4, and storage region MR1 is to MR4's Configuration can be changed or modified for Fig. 4 and difference shown in fig. 5.Including the storage in each storage region MR1 into MR4 Area can be adjacent to each other, or can be discontinuous.

The configuration of storage region MR1 to MR4 statically can be fixed or can be dynamically changed.Return to Fig. 3, controller 1330a can choose or change the configuration of storage region MR1 to MR4, and can be set or referring to storage region MR1 to MR4 The configuration chosen or the configuration having changed.

For example, controller 1330a can monitor the amount of the write-in data with specific flow identifier.For example, controller 1330a can monitor the use of the inactive area, available free area or the spare area that such as store invalid data, storage write-in data The distribution of each memory block in area etc..Controller 1330a can change storage region MR1 based on the amount and/or distribution that are monitored To the attribute of MR4, such as size and location.For example, also can change when changing the distribution of each memory block by garbage collection The attribute of storage region MR1 to MR4.However, providing these examples is for the ease of better understanding, it is not intended to limit this public affairs It opens.

Controller 1330a can receive write-in data flow WD_S (for example, from host 1100a).Data flow WD_S is written It is construed as including the data flow with a series of write-in data of one or more flow identifiers.Based on flow identifier, Storage region MR1 can be stored in one into MR4 including the write-in data in write-in data flow WD_S.

Buffer storage 1350a can buffer the write-in number in memory device 1311,1312,1313 and 1319 to be stored in According to.Controller 1330a can be communicated with buffer storage 1350a and memory device 1311,1312,1313 and 1319, be made Data must be written to be stored in memory device 1311,1312,1313 and 1319.Controller 1330a can control memory Device 1311,1312,1313 and 1319, so that write-in data are stored in memory device 1311,1312,1313 and 1313 and In 1319.It will describe to be used to be written data referring to Fig. 7 and Fig. 8 and be stored in memory device 1311,1312,1313 and 1319 In example write operation.

In some example embodiments, buffer storage 1350a will be described and illustrated for buffering write-in data.However, There is provided these example embodiments is for the ease of better understanding, rather than in order to limit the disclosure.In some example embodiments In, write-in data can be buffered in the internal storage of controller 1330a or in another additional storage.

II-C. example write operation

Fig. 6 is the block diagram for the example write operation for describing the storage device 1300a of Fig. 2.

It may include a series of write-in data by the received write-in data flow WD_S of controller 1330a.It is included in write-in number It can be buffered in buffer storage 1350a according to the write-in data in stream WD_S.For example, write-in data can be with logically Location.

In addition, logical address can be converted into physical address by controller 1330a.Physical address can indicate memory device Set the specific memory section on 1311,1312,1313 and 1319 or the position of particular memory region.Controller 1330a can be to write Physical address after entering data distribution translation.

In some cases, buffer storage 1350a can buffer write-in data, until the write-in number of all flow identifiers According to until being a fully buffered or sufficiently buffering.For example, when handling four flow identifiers, as shown in fig. 6, buffer storage 1350a can buffer write-in data, until the write-in data of whole four flow identifiers are a fully buffered.

After the write-in data of all flow identifiers are sufficiently buffered, controller 1330a can be write-in data distribution Physical address.Later, under the control of controller 1330a, write-in data can be stored in the physical address instruction by distributing Each memory block in.The write-in data of all flow identifiers can be by concurrently (such as synchronously or simultaneously) or sequentially It is stored in each memory block by the physical address instruction distributed.

Can the flow identifier based on the write-in data being stored in each memory block come managing storage area MR1 to MR4. For example, when the write-in data that flow identifier is " 1 " are stored in the specific memory section of memory device 1311, controller 1330a can be managed using the specific memory section as storage region MR1.For example, can receive and store with traffic identifier The write-in data for according with " 1 " determine storage region MR1 later.In this way it is possible in storage region corresponding with flow identifier In include memory block in management write-in data.

Several write-in data with same or similar characteristic can be effectively managed using multi-stream scheme.But When being the write-in data allocated physical address of certain flow identifiers before the write-in data to whole flow identifiers buffer, It may become chaotic using the distribution in area, and be likely difficult to effectively manage the write-in data of other ignored flow identifiers. Therefore, after the write-in data for buffering all flow identifiers, the physical address of each memory block is distributed to store write-in data It can be advantageous.

However, a large amount of money may be needed in buffer storage 1350a when buffering the write-in data of all flow identifiers Source.For example, it may be desirable to increase the capacity or buffer of buffer storage 1350a with corresponding to the quantity of flow identifier Quantity may be needed with the quantity of flow identifier as many.This can reduce the efficiency of managing storage 1300a, and will increase Manufacture the cost of storage device 1300a.

Fig. 7 is the example write-in behaviour for describing to execute in the storage device 1300a according to Fig. 2 of some example embodiments The block diagram of work.Fig. 8 is the example write operation for describing to execute in the storage device 1300a according to Fig. 2 of some example embodiments Flow chart.For the ease of more fully understanding, Fig. 7 and Fig. 8 will be described together.

In some example embodiments, controller 1330a can manage the corresponding pass between physical address and flow identifier It is CR (the operation S110 of Fig. 8).Write-in data can be received in controller 1330a (or writing including a series of write-in data Enter data flow WD_S) before, corresponding relationship CR is managed in advance.Therefore, buffer storage can be buffered in write-in data Before 1350a, corresponding relationship CR is managed in advance.

For example, as shown in fig. 7, the information of corresponding relationship CR can be stored in buffer storage 1350a.However, this Disclose without being limited thereto and different from shown in Fig. 7, the information of corresponding relationship CR can be stored in the inside of controller 1330a In memory or memory device 1311,1312,1313 and 1319.The letter of the accessible corresponding relationship CR of controller 1330a Breath is to carry out subsequent operation.

In corresponding relationship CR, a flow identifier can correspond to one or more physics of one storage region of instruction Address.For example, can manage a flow identifier to correspond to instruction includes each of each memory block in a storage region Physical address.For example, flow identifier " 1 " associated with the first characteristic can be managed in corresponding relationship CR, so that it is corresponded to In physical address associated with storage region MR1, and can be managed in corresponding relationship CR associated with the second characteristic Flow identifier " 2 ", to make it correspond to physical address associated with storage region MR2.

However, in some example embodiments, a flow identifier can correspond to indicate each object of multiple storage regions Reason address or multiple flow identifiers can correspond to each physical address of one storage region of instruction.Corresponding relationship CR can be with It is differently altered or modified, there is same or similar characteristic in one or more selected storage regions effectively to manage A plurality of data.

It can properly select or set in view of available area, dead space and using the distribution in area and position, controller 1330a Set corresponding relationship CR.However, controller 1330a can manage corresponding relationship CR before receiving write-in data in advance.Some In example embodiment, as described above, controller 1330a can be with the state of supervisory memory device 1311,1312,1313 and 1319 To dynamically change the attribute (for example, size and/or position etc.) of storage region MR1 to MR4.Therefore, corresponding relationship CR can be with Changed according to the operation of memory device 1311,1312,1313 and 1319.

After preparing corresponding relationship CR, controller 1330a can receive the write-in data (figure with specific flow identifier 8 operation S120).In some example embodiments, controller 1330a can be the write-in number received based on corresponding relationship CR Correspond to the physical address of specific flow identifier according to distribution.Controller 1330a can control memory device 1311,1312, 1313 and 1319, so that the write-in data received are stored in the storage region of distributed physical address.It therefore, can be with The management write-in data in storage region corresponding with flow identifier.

For example, controller 1330a can refer to when controller 1330a receives the write-in data with flow identifier " 1 " Corresponding relationship CR obtains physical address corresponding with flow identifier " 1 ".Physical address obtained can indicate storage region MR1.Controller 1330a can give the physical address assignments of acquisition to write-in data.Under the control of controller 1330a, receive To write-in data can be stored in distributed physical address each memory block in, that is, in storage region MR1.

In some cases, it can be different to be written by single by the size of the received write-in data of controller 1330a and grasp Make the program unit size of stored program unit data.For example, write-once operation can be executed, by 32 kilobytes (KB) program unit data is stored in memory device 1311,1312,1313 and 1319, and host 1100a can be to depositing Storage device 1300a provides the write-in data of slight 4KB bigger than program unit.

In this case, under the control of controller 1330a, buffer storage 1350a can be buffered to fail to be sold at auction with specific Know and accord with associated a plurality of write-in data, until program unit data is accumulated as stopping about the specific flow identifier.For example, working as When receiving the write-in data with flow identifier " 1 ", buffer storage 1350a can by the write-in data received with have Other write-in data of the one or more of flow identifier " 1 " buffer together.A plurality of write-in data with flow identifier " 1 " can be with It is buffered, until program unit data (that is, data of program unit) is accumulated as stopping about flow identifier " 1 ".

Controller 1330a can decide whether to have accumulated the program unit data (operation of Fig. 8 about specific flow identifier S130).When not accumulating program unit data (Fig. 8 operation S130 "No"), can receive next write-in data (Fig. 8's Operate S120).

When having accumulated program unit data ("Yes" of the operation S130 of Fig. 8), controller 1330a can be program unit Data allocated physical address (the operation S140 of Fig. 8).Controller 1330a can be based on corresponding relationship CR, to distribute and program list The corresponding physical address of the flow identifier of metadata.For example, when having accumulated program unit data about flow identifier " 1 ", Controller 1330a can be based on corresponding relationship CR, for the physical address of program unit data distribution instruction storage region MR1.

Later, program unit data can be transferred to by being distributed physically based on corresponding relationship CR by controller 1330a Storage region indicated by location (the operation S150 of Fig. 8).Program unit data can be transferred to including by distributing physically The storage region of memory block indicated by location.For example, the program unit data accumulated about flow identifier " 1 " can be transferred to By the memory block for the physical address instruction of storage region MR1 distributed.

Therefore, program unit data can be stored in the storage region corresponding to flow identifier.Here, a program Cell data may include have the write-in data of specific flow identifier and with identical flow identifier one or more other Data are written.

Under the control of controller 1330a, a plurality of write-in data with identical flow identifier can be stored in together together In one storage region.Controller 1330a can be with memory device 1311,1312,1313 and 1319 and buffer storage 1350a communication, so that including that a plurality of program unit data that data are written is stored in desired storage region.

It, can be before receiving write-in data when using corresponding relationship CR, predefining will store with specific stream The storage region of the write-in data of identifier.For example, receiving the write-in data with flow identifier " 1 " in controller 1330a With with flow identifier " 2 " write-in data, then be buffered in buffer storage 1350a before, it may be predetermined that deposit Storage area domain MR1 is used to store the write-in data with flow identifier " 1 ", and can predefine storage region MR2 and be used to deposit Store up the write-in data with flow identifier " 2 ".

Storage region MR1 to MR4 and corresponding relationship CR can be differently altered or modified as suitable for managing together Several write-in data with same or similar characteristic.As set forth above, it is possible to statically fix or can dynamically change Storage region MR1 to MR4 and corresponding relationship CR.

Different from the example of Fig. 6, the example write operation of Fig. 7 does not need to cache the write-in data of all flow identifiers.Cause This, once receive the write-in number of (or buffering) with specific flow identifier (or program unit data including data are written) According to, so that it may the write-in data (or program unit data) are transferred to based on corresponding relationship CR corresponding with specific flow identifier Storage region.In addition, sequence regardless of flow identifier or configuration, once receive (or buffering) write-in data (or journey Sequence cell data), so that it may it is transmitted to storage region MR1 to MR4.

Write-in data with specific flow identifier can be transferred to memory device 1311,1312,1313 and 1319, Without the write-in data for considering that there are other flow identifiers.For example, no matter the write-in data with flow identifier " 2 " are by controller 1330a is received or is buffered in buffer storage 1350a, can will have flow identifier " 1 " based on corresponding relationship CR Write-in data be transferred to storage region MR1.

For example, controller 1330a can control 1311,1312,1313 and of buffer storage 1350a and memory device 1319, so that the write-in data with flow identifier " 2 " are based on corresponding relationship CR and are stored in storage region MR2.It is similar Ground can will have the write-in data of flow identifier " 2 " to be transferred to the storage of memory device 1311,1312,1313 and 1319 Region MR2, without the write-in data for considering that there are flow identifier " 1 ", " 3 " or " 4 ".

According to the example write operation of Fig. 7, the write-in data of all flow identifiers may not be a fully buffered simultaneously, because This storage device 1300 can manage write-in data in low capacity buffer.For example, buffer storage 1350a can be implemented For with low capacity, or a small amount of buffer storage can be provided.Alternatively, it is possible to by the way that controller 1330a is used only In the internal storage of low capacity manage write-in data.It is thus possible to improve the efficiency of managing storage 1300, and The cost of manufacture storage device 1300 can be reduced.

II-D. it supplements

Fig. 9 is the interleaving access by multiple channel C H1 to CH4 for describing the example write operation about Fig. 7 and Fig. 8 Flow chart.For example, prepare write-in data (the operation S120 of Fig. 8) or preparation routine cell data (the operation S130 of Fig. 8) it Afterwards, the interleaving access of Fig. 9 can be executed.

It can be write-in data or program unit data allocated physical address (operation S140).For this purpose, real in some examples It applies in example, controller 1330a can choose idle channel (operation S141) of each channel C H1 into CH4.If special modality is not Be it is idle, then controller 1330a can choose another idle channel.Controller 1330a can be write-in data or program The physical address (operation S143) of channel attached memory block is distributed and chosen to cell data.

Later, write-in data or program unit data can be transferred to distributed physical address by controller 1330a Memory block (operation S150).Here it is possible to pass through the idle channel transmission write-in data or program unit data (operation chosen S151).Therefore, data or program unit data being written can be stored in memory device 1311,1312,1313 and 1319.

For example, referring to Fig. 7 and Fig. 9, the write-in data with flow identifier " 1 " can be stored in storage region MR1 Including each memory block among the memory block being connect with channel C H1 in.When channel C H1 is occupied, channel C H1 will not be empty Not busy.For example, channel C H2 can be idle and channel C H1 is not idle.In this case, controller 1330a can choose channel CH2 transmits the write-in data with flow identifier " 2 ".

Controller 1330a can distribute for the write-in data with flow identifier " 2 " from including in storage region MR2 The physical address of the memory block for being connected to channel C H2 among each memory block.Therefore, with the write-in data of flow identifier " 2 " It can be transmitted, and can be stored in the memory block of distributed physical address by idle channel CH2.

In this way, by a plurality of write-in data from controller 1330a be transferred to memory device 1311,1312, 1313 and 1319 can carry out interleaving access by channel C H1 to CH4.Since write-in data are transmitted by idle channel, so The performance of entire write operation can be improved.

Figure 10 is the concept map transmitted for describing the time-division multiplex of the example write operation about Fig. 7 and Fig. 8.

For example, using the clock synchronizer controller 1330a with frequency f1 to write-in data (for example, write-in data flow WD_S reception).Communication between controller 1330a and memory device 1311,1312,1313 and 1319, which can use, to be had The clock of frequency f2 is synchronous.

Meanwhile the communication between controller 1330a and memory device 1311,1312,1313 and 1319 can be by logical Road CH1 to CH4 is executed in a manner of interleaving access.Therefore, in order to improve the performance of interleaving access, it can choose frequency f1 and be higher than Frequency f2.

For example, frequency f1 can correspond to the product of the quantity of frequency f2 and channel C H1 to CH4.For example, when frequency f2 is When 0.8 Gigahertz (GHz), it is about 3.2 (=0.8 × 4) GHz that frequency f1, which can choose,.In this case, it is included in write-in A series of write-in data in data flow WD_S can with parallel distributed to channel C H1 to CH4 (in corresponding time-division domain A series of write-in data of transmission in (dividedtime domains)), to improve the performance of interleaving access.

The clock for having frequency f1 and f2 can be provided by isolated clock generator circuit.In some example embodiments In, clock generator circuit can the operation based on controller 1330a and memory device 1311,1312,1313 and 1319 come Change frequency f1 and f2.For example, clock generator circuit can be reduced suitably when some idle into CH4 of channel C H1 Frequency f1.For example, clock generator circuit can increase frequency when the data volume increase transmitted by channel C H1 to CH4 f1。

Meanwhile in some example embodiments, frequency f1 can be selected as identical as frequency f2.It is real in such example It applies in example, the data width (for example, data bits) that data flow WD_S is written can be every into CH4 greater than by channel C H1 The data width of the data of one transmission.For example, the data width of write-in data flow WD_S can correspond to channel C H1 to CH4 Quantity and the data width of the data by each of channel C H1 to CH4 transmission product.

For example, when the data by each of channel C H1 to CH4 transmission include 8, write-in data flow WD_S's Data width can be 32 (=8 × 4) positions.It, can be with when transmitting data by respective channel in such example embodiment The clock for being directed to channel C H1 to each of CH4 is enabled within the period being inversely proportional with number of channels.

The multi-stream scheme based on flow identifier associated with different data characteristic is described referring to Fig. 3 to Figure 10. However, the present disclosure is not limited to above description, and similar embodiment can be used for individually flowing.

For example, controller 1330a can manage the first write-in data and predetermined instruction is used to store described first The corresponding relationship between the physical address of the storage region of data is written.It can be before receiving the first write-in data, in advance Manage the corresponding relationship.

In spite of the second write-in data are received, the first write-in data can be transferred in advance really based on corresponding relationship Fixed storage region.Controller 1330a can control memory device so that first write-in data be stored in it is predetermined In storage region.Operation strategy based on host 1100a and storage device 1300a and/or user be intended to etc. it is various because Element, it may be predetermined that store the storage region of the first write-in data.

III-A. hardware automated framework

Figure 11 is the block diagram for showing the example arrangement of storage device 1300 of Fig. 1.The electronic system 1000 of Fig. 1 may include The electronic system 1000b of Figure 11.The storage device 1300 of Fig. 1 may include the storage device 1300b of Figure 11.

Figure 11 is compared with Fig. 2, in some example embodiments, storage device 1300b may include controller 1330b and buffer storage 1350b.Controller 1330b can pass through multiple channel C Hs and one or more memory devices 1310 communications.Controller 1330b may include by the host interface layer 1331a of referring to Fig.1 2 and Figure 19 description, memory interface Layer 1332, reads management circuit 1335, data field management circuit 1337 and processor 1339 at write-in management circuit 1333.

Storage device 1300b can be realized with " hardware automated framework ".Storage device 1300b can be by dedicated hard Part circuit manages simple operation, rather than the control of the processor 1339 that places one's entire reliance upon.The opposite frequency of special hardware circuit management The simple operation executed numerously, without the intervention of processor 1339, therefore can be improved storage device 1300b efficiency and Performance.

Buffer storage 1350b can be buffered in data used in the operation of storage device 1300b.For example, buffering is deposited Reservoir 1350b can temporarily store the data quoted by controller 1330b.However, buffer storage 1350b can not store to The write-in data that are stored in memory device 1311 and 1319 do not read the number exported from memory device 1311 and 1319 According to this will be described below.On the contrary, buffer storage 1350b can be provided as additional storage, it will be by controlling for storing The metadata of device 1330b reference.For example, buffer storage 1350b may include the easy of SRAM, DRAM and/or SDRAM etc. The nonvolatile memory of the property lost memory and/or flash memory, PRAM, MRAM, ReRAM and/or FRAM etc..

About Figure 11 other component not described be configurable to it is essentially identical those of referring to described in Fig. 2 to Figure 10 And it is substantially alike operated with those of referring to described in Fig. 2 to Figure 10.For simplicity, extra retouch will be omitted below It states.

Figure 12 and Figure 13 is the exemplary operations for describing the storage device 1300b according to Figure 11 of some example embodiments Block diagram.2 and Figure 13 referring to Fig.1, controller 1330b may include first kind job management circuit HW and processor 1339.

For example, first kind job management circuit HW may include the write-in management circuit 1333 of Figure 11, read management electricity Road 1335 and data field manage circuit 1337.First kind job management circuit HW can manage with memory device 1311 and 1319 associated first kind operations.Processor 1339 can handle associated with memory device 1311 and 1,319 second Type of operation.For example, first kind operation may include the simple operation more frequently executed than Second Type operation.

For example, first kind operation may include the storage to the first unit size in memory device 1311 and 1319 The operation that area executes.For example, first unit size may include a page cell size.For example, first kind operation may include one As operate, such as the write operation of storage write-in data in memory device 1311 and 1319 and/or for from storage The read operation etc. of data is read in the output of device device 1311 and 1319.

For example, Second Type operation may include the storage to the second unit size in memory device 1311 and 1319 The operation that area executes.Second unit size can be of different sizes with first unit, for example, second unit size may include block/ Sub-block/superblock cell size.For example, Second Type operation may include management operation, such as garbage collection, wear leveling, Power-off protection etc..

Example embodiment based on above-mentioned example will be described in the following description.However, providing such example embodiment It is for the ease of better understanding, rather than in order to limit the disclosure.First kind operation can be differently altered or modified Intervention to manage the simple operation frequently executed, without processor 1339.In addition, Second Type operation can be by differently It is altered or modified to manage complex job under the control of processor 1339.First unit size and second unit size can also be with It is differently altered or modified, and can be mutually the same.

Figure 12 shows operation associated with first kind operation.For example, first kind operation may include by host The operation of 1100a request.It can be managed according to including the operation of hardware circuit in first kind job management circuit HW First kind operation, without the intervention of processor 1339.

It (including can be data allocation buffer, buffer number from all operations for example, when managing first kind operation According to, trigger data input/output, and/or control the path etc. of data input/output) in exclude the intervention of processor 1339.Though First kind operation is usually so managed by first kind job management circuit HW, but processor 1339 can be not involved in the first kind It type operation and can not be communicated with buffer storage 1350b.

When first kind operation includes write operation, first kind job management circuit HW can will be from host 1100a Received write-in data are transferred to one or more memory devices 1310.When first kind operation includes read operation, the The reading data exported from one or more memory devices 1310 can be transferred to host by one type job management circuit HW 1100a.Write-in data and reading data can be transmitted to flow the packet unit of PC_S.

Meanwhile buffer storage 1350b can not store to be stored in writing in one or more memory devices 1310 Enter data or does not read the data exported from one or more memory devices 1310.On the contrary, can be in first kind working pipe It manages management write-in data in the internal buffer of circuit HW and reads data.

Figure 13 shows operation associated with Second Type operation.For example, Second Type operation may include and host The operation that the request of 1100a independently executes.It can be under the control of processor 1339 (for example, based on processor 1339 The software of execution and/or the program code of firmware) processing Second Type operation.

For example, first kind job management circuit HW can be monitored and one or more memory devices 1310 and controller The associated state of the operation of 1330b.First kind job management circuit HW can be managed based on the state of monitoring for triggering The intervention condition of the intervention of processor 1339.For example, monitored state can with whether about first kind operation (for example, write-in Operation and/or read operation etc.) generation is wrong or exception is associated.For example, when mistake relevant to first kind operation occurs Or when abnormal, it can satisfy intervention condition.

When meeting intervention condition simultaneous processor 1339 and not intervening first kind operation, first kind job management circuit HW can provide the notice of the information including monitored state to processor 1339.Therefore, first kind job management circuit HW can To notify that intervention condition is met to processor 1339.

In response to the notice received from first kind job management circuit HW, processor 1339 is exportable for handling the The administration order of two type of operation.First kind job management circuit HW can receive administration order from processor 1339.First Type of operation management circuit HW can execute the Second Type operation guided by administration order.Second Type operation may include using In the management operation for solving monitored state (for example, mistake associated with first kind operation or exception).

For example, Second Type operation may include the management operation for one or more memory devices 1310.First Type of operation management circuit HW can be communicated with one or more memory devices 1310, to hold under the control of processor 1339 Row Second Type operation.

III-B. the example arrangement of controller and data packet

Figure 14 is the example arrangement and exemplary operations for showing the controller 1330b according to Figure 11 of some example embodiments Block diagram.

Controller 1330b may include host interface layer 1331a, memory interface layer 1332, write-in management circuit 1333, Read management circuit 1335, data field management circuit 1337 and processor 1339.For example, write-in management circuit 1333, reading pipe Managing circuit 1335 and data field management circuit 1337 may include in the first kind job management circuit HW of Figure 12 and Figure 13.

Host interface layer 1331a can be interacted with host 1100a.For example, host interface layer 1331a can will be from host The received order and data of 1100a are converted to the format handled in controller 1330b.For example, host interface layer 1331a can be with By the data conversion handled in controller 1330b at the format handled in host 1100a, and can be by converted format Data be output to host 1100a.

Memory interface layer 1332 can be interacted with one or more memory devices 1310.For example, memory interface layer Write-in data and related command can be converted to the format handled in one or more memory devices 1310 by 1332.Example Such as, the reading data received from one or more memory devices 1310 can be converted to and controlled by memory interface layer 1332 The format handled in device 1330b processed.

Write-in management circuit 1333 can manage first kind operation.For example, write-in management circuit 1333 can be managed and is used for Write-in data are stored in the write operation in one or more memory devices 1310.In this example, write-in management circuit 1333 can be located at for will be transferred to the write-in of one or more memory devices 1310 from the received write-in data of host 1100a On path.

First kind operation can be managed by reading management circuit 1335.For example, use can be managed by reading management circuit 1335 The outside of controller 1330b is output to (for example, read operation of the output to host 1100a) in data will be read.In the example In, reading management circuit 1335 can be for being transferred to the reading data exported from one or more memory devices 1310 On the read path of the outside of controller 1330b.

For first kind operation is executed, data field management circuit 1337 can obtain one or more memory devices Information, write-in data and/or the reading data of at least one of 1310 state.Write-in management circuit 1333 and reading management Circuit 1335 can execute first kind operation, then can manage circuit 1337 to data field and provide the information of various states. Data field, which manages circuit 1337, can be based on information obtained, to monitor and one or more memory devices 1310 and control The associated state of the operation of device 1330b.

Processor 1339 may include one or more processing cores.Processor 1339 can be held according to the operation of processing core The program code of row software SW and/or firmware FW.The program code that processor 1330 can execute software SW and/or firmware FW comes Handle Second Type operation.

Order and data can be transmitted with the packet unit of stream.For this purpose, in some example embodiments, host interface Layer 1331a may include packing device PCZ.Packing device PCZ can will be from the received order and data of host 1100a and additional information (for example, the destination of data packet, address, flow identifier and/or error checking position etc.) is combined to generate data packet PCW1 or number According to packet PCR1.

When from host 1100a receive writing commands and write-in data when, packing device PCZ can be generated including head (H), The data packet PCW1 of data portion (D) and tail portion (T).For example, head may include the information of writing commands, data portion may include Data are written.Tail portion may include the information terminated suitable for designation date portion.

When receiving reading order from host 1100a, the data packet including head (H) is can be generated in packing device PCZ PCR1.Head may include the information of reading order.Data are likely not to have received about read operation, therefore in certain situations Under, data packet PCR1 can not include data portion and tail portion.

Packing device PCZ may include hardware circuit, which is configured as basis from the received order of host 1100a Data packet PCW1 or data packet PCR1 is generated with data.5 it will be described more fully with and be handled in controller 1330b referring to Fig.1 Data packet example arrangement.

Write-in management circuit 1333 may include the first internal buffer 1333a and buffer manager for use 1333b.Write-in management Circuit 1333 can receive data packet PCW1 or data packet PCR1.When the head of data packet PCW1 or data packet PCR1 include about When the information of order, write-in management circuit 1333 can judge that received data packet is related with write operation with reference head Or it is associated with read operation.

When write-in management circuit 1333 receives data packet PCW1 associated with write operation, the first internal buffer It includes various information in data packet PCW1 and write-in data that 1333a, which can be buffered,.For example, the first internal buffer 1333a can To include the memory device of such as SRAM.Buffer-manager 1333b can manage the buffer area of the first internal buffer 1333a Distribution so that not causing danger or conflicting when the first internal buffer 1333a stores information.

Write-in management circuit 1333 can be based on the write-in data buffered in the first internal buffer 1333a, by data Packet PCW2 is transferred to memory interface layer 1332.Memory interface layer 1332 can be come true with the head (H) of reference data packet PCW2 The physical address of the memory block of fixed storage write-in data.Write-in data can be transferred to target storage by memory interface layer 1332 Device device, the target memory device include the memory block of identified physical address.Therefore, write-in data can be stored In one or more memory devices 1310.

When executing write operation, write-in management circuit 1333 can will be mapped to from the received logical address of host 1100a Physical address.Physical address to be mapped can be from by write-in management circuit 1333, data field management circuit 1337 and/or processing It is selected in the list for the available physical address that device 1339 manages.In some example embodiments, write-in management circuit 1333 can be examined Characteristic or the flow identifier of write-in data are considered to obtain physical address to be mapped.Write-in data can be stored in one or more In the memory block of the physical address of mapping in a memory device 1310.

Write-in management circuit 1333 can manage circuit 1337 to data field and provide the logical address and mapping received The information of physical address.Data field management circuit 1337 can manage the logical address and physical address in buffer storage 1350 Between corresponding relationship information.Buffer storage 1350 can store the information of corresponding relationship, as the first metadata.It will ginseng Example write operation is further described according to Figure 16 to Figure 19.

On the other hand, when write-in management circuit 1333 receives data packet PCR1 associated with read operation, write-in Data packet PCR1 can be transferred to data field management circuit 1337 by management circuit 1333.For example, write-in management circuit 1333 can be with It is configured as routing the data packet received based on the additional information of the data packet received.Write-in management circuit 1333 may be used as the switch of transmission order and data.

Data field management circuit 1337 can be closed with reference to the corresponding of the first metadata being stored in buffer storage 1350 System, to obtain physical address corresponding with data packet PCR1.That is, can produce or quote when managing first kind operation One metadata.The data packet PCR2 of the information including physical address obtained can be generated in data field management circuit 1337.Number Data packet PCR2 can be transferred to memory interface layer 1332 according to domain management circuit 1337.

Referring to the head (H) of data packet PCR2, reading order can be transferred to target storage by memory interface layer 1332 Device device, the target memory device include the memory block of physical address obtained.Therefore, it can be filled from target memory It sets output and reads data.The data packet PCR3 of reading data (D) including output can be supplied to by memory interface layer 1332 Read management circuit 1335.

Reading management circuit 1335 may include the second internal buffer 1335a.Second internal buffer 1335a can delay Punching includes the various information in data packet PCR3.For example, the second internal buffer 1335a may include the storage of such as SRAM Device device.Reading management circuit 1335 can be based on the reading data being buffered in the second internal buffer 1335a, by data packet PCR4 is transferred to host interface layer 1331a.

The reading data (D) that host interface layer 1331a can be included in data packet PCR4 are transferred to host 1100a. Correspondingly, the outside that data can be output to controller 1330b from one or more memory devices 1310 is read.

Each of write-in management circuit 1333, reading management circuit 1335 and data field management circuit 1337 can wrap It includes and is configured as executing the hardware circuit of operation that is described above and will be described below.Write-in management circuit 1333 reads pipe Reason circuit 1335 and data field management circuit 1337 can automatically process the first kind in the case where no processor 1339 is intervened Type operation.Order and data can be packaged with general format, therefore management circuit 1333 is written, reads management 1335 sum number of circuit According to the hardware circuit of each of domain management circuit 1337 data can be based in the case where no processor 1339 is intervened The additional information of packet manages the packet unit of stream.

When normal management first kind operation, processor 1339 can be not involved in first kind operation.In addition, processor 1339 can be not involved in following operation: generate data packet by packing device PCZ and along write paths and read path transport stream Packet unit.In addition, processor 1339, which can be not involved in, manages circuit 1337 for the storage of the first metadata by data field In buffer storage 1350 and circuit 1337 is managed by data field and reads the first metadata from buffer storage 1350.

When managing first kind operation, data field manages circuit 1337 can be from write-in management circuit 1333 and reading management Circuit 1335 obtains various information.Information obtained can indicate and one or more memory devices 1310 and controller The associated various states of the operation of 1330b, including mistake or abnormal.Data field management circuit 1337 can be based on obtained Information manages the intervention condition of the intervention for triggering processor 1339.

When mistake or exception occurs about first kind operation, controller 1330b's and/or storage device 1300b It may break down in operation.But first kind operation may include simple operation and may be not suitable for solve mistake or It is abnormal.Second Type operation may be needed to solve mistake or exception, and processor 1339 can be intervened and make to Second Type The processing of industry.

For example, can satisfy intervention condition when being directed to first kind operation generation mistake or exception.Data field management Circuit 1337 can provide notice to processor 1339 and be met with 1339 intervention condition of notifier processes device.When being not received by When notice, processor 1339 can be not involved in following operation: to the management of first kind operation, generation and transmission data packet and Manage the first metadata.

On the other hand, when receiving notice, processor 1339 can manage circuit 1337 to data field and provide management life It enables to handle Second Type operation.Administration order can indicate to hold at least one of write paths and/or read path Capable management operation.Notice and administration order may include in the head (H) of data packet PCC.

Processor 1339 can be communicated with buffer storage 1350 to handle Second Type operation.Buffer storage 1350 can To store the second metadata.When managing Second Type operation, the second metadata is can be generated or quoted.That is, processing Second metadata can be stored in buffer storage 1350 by device 1339, or can be read and be stored in buffer storage 1350 In the second metadata, to handle Second Type operation.

Data field management circuit 1337 can execute Second Type operation in response to administration order.That is, when hair When raw mistake or abnormal (for example, about first kind operation), processor 1339 can be intervened, and can be in processor 1339 Control under execute Second Type operation.When Second Type operation is accompanied by write operation and/or read operation, data field pipe Reason circuit 1337 can provide suitable order to write-in management circuit 1333 and/or reading management circuit 1335.

According to hardware automated framework, controller 1330b may include data field associated with first kind operation.Separately Outside, controller 1330b may include control domain associated with Second Type operation.Write-in management circuit 1333 and reading management Circuit 1335 can manage the first kind operation in data field, and processor 1339 can handle the second class in control domain Type operation.Data field management circuit 1337 can manage the first kind operation in data field, and can trigger processor 1339 intervention in control domain.

In centralized architecture, buffer-stored can be focused on including write-in data and all data flows for reading data Device 1350a, and processor 1339 can intervene both first kind operation and Second Type operation.In this case, it deposits The performance of storage device (for example, storage device 1300a) may depend on the performance of processor 1339 and gulping down for buffer storage 1350a The amount of spitting.On the other hand, in hardware automated framework, pass through individual specialized hardware in the case where processor 1339 is not involved in The simple operation of Circuit management can reduce the load of processor 1339 and buffer storage 1350b.

As shown in figure 14, write paths can be physically separate with read path.It therefore, can concurrently or synchronously or together When execute write operation and read operation.This can be further improved the performance for handling simple operation.

It in some cases, can be while processor 1339 handles Second Type operation by special hardware circuit management the One type of operation.That is, first kind operation can be concurrently or simultaneously managed with processing Second Type operation, without It is interfered because of Second Type operation.First kind operation can be by special hardware circuit management, without processor 1339 intervention, therefore first kind operation can be handled with Second Type job parallelism.

As described above, buffer storage 1350 can store the first metadata and the second metadata.Implement in some examples In example, the first metadata can be stored separately (for example, the memory block for storing the first metadata is with difference with the second metadata In the memory block for storing the second metadata).In some example embodiments, only data field management circuit 1337 can visit Ask both the first metadata and the second metadata, and processor 1339 only can manage the access of circuit 1,337 the by data field Binary data.According to such example embodiment, even if the first metadata and the second metadata manage circuit by data field respectively 1337 and processor 1339 independently manage, it is also ensured that the consistency and integrality of the first metadata and the second metadata.

Figure 15 is the concept map for showing the example arrangement of data packet of Figure 14 according to some example embodiments.

As described in referring to Fig.1 4, a data packet may include head, data portion and tail portion.Data portion may include write-in Data read data.

For example, head may include routing iinformation, the information of logical address LPN, the information of physical address PPN, order CMD Information, Flow Identifier information and/or status information etc..Routing iinformation can be with the destination of designation date packet, and can wrap Include such as component identifier or label.

Logical address LPN may include from the received address host 1100a, and physical address PPN may include and patrol Collect the physical address of address LPN mapping.Order CMD can be indicated by the type of the operation of data packet request.Flow Identifier information Can indicate include write-in data in data portion flow identifier.Status information can indicate and one or more memories The associated state of the operation of device 1310 and controller 1330b (for example, with wrong or abnormal associated state).

However, the head of a data packet may not include at least one item of information shown in figure 15.For example, physical address The information of PPN can not include from host interface layer 1331a be supplied to write-in management circuit 1333 data packet (for example, PCW1 in).For example, status information can not be included in and be transferred to one or more from host 1100a in order to data will be written and deposit Reservoir device 1310 and transmit in the data packet that generates or in order to which data will be read from one or more memory devices 1310 In the data packet generated to host 1100a.According to the purpose of data packet, the configuration on head differently can be changed or be repaired Change.

Tail portion may include the information for being suitable for designation date portion and terminating.For example, tail portion may include integrality/mistake inspection Information is looked into, data integrity feature (DIF), data integrity extend (DIX) and/or cyclic redundancy check (CRC) etc..So And the present disclosure is not limited thereto, tail portion can be configured as including other information.

One data packet may include the whole of head, data portion and tail portion.Alternatively, a data packet can not wrap Include at least one of head, data portion and/or tail portion.

For example, being transferred to one or more memory devices 1310 in order to data will be written from host 1100a and generating Data packet or in order to which the data that data are transferred to host 1100a from one or more memory devices 1310 and generate will be read Packet may include the whole of head, data portion and tail portion.For example, in order to by reading order from host 1100a be transferred to one or Multiple memory devices 1310 and generate data packet, from data field management circuit 1337 be provided to the notice number of processor 1339 It can only include head according to wrapping and being provided to the administration order data packet of data field management circuit 1337 from processor 1339.

However, providing above-described embodiment is for the ease of better understanding, it is not intended that the limitation disclosure.Data packet configuration It can be differently altered or modified, to manage first kind operation automatically by individual hardware circuit, without processor 1339 intervention.

III-C. example write operation

Figure 16 to Figure 18 is for describing to execute in the storage device 1300b in Figure 11 according to some example embodiments The block diagram of example write operation.Figure 19 is to describe to execute in the storage device 1300b in Figure 11 according to some example embodiments Example write operation flow chart.In order to make it easy to understand, will together referring to Fig.1 6 to Figure 19.

Referring to Fig.1 8, write-in management circuit 1333 can manage the corresponding relationship (figure between physical address and flow identifier 19 operation S305).Above-mentioned corresponding relationship can be substantially alike managed with the corresponding relationship CR described referring to Fig. 7 and Fig. 8. Storage region MR1 to MR4 can be configured as with it is essentially identical referring to described in Fig. 3 to Fig. 5.

For example, flow identifier " 1 " can correspond to the physical address of instruction storage region MR1 in corresponding relationship, and Flow identifier " 2 " can correspond to the physical address of instruction storage region MR2.Write-in data can be received in controller 1330b Before, above-mentioned corresponding relationship is managed in advance.

Referring to Fig.1 6, host interface layer 1331a can receive writing commands and write-in data (figure from host 1100a 19 operation S310).Write-in data can have specific flow identifier.

Packing device PCZ can be packaged writing commands and write-in data (the operation S320 of Figure 19).For example, packing device PCZ can To combine writing commands and write-in data to generate data packet PCW1 with additional information.For example, the head (H) of data packet PCW1 It may include the information of writing commands logical address and flow identifier, and the data portion (D) of data packet PCW1 may include writing Enter data.Data packet PCW1 can be provided to write-in management circuit 1333.

In some cases, the head of data packet PCW1 may include data type, data configuration and/or exception etc. Information.Write-in management circuit 1333 can be based on the information for including in packet PCW1 to determine whether managing each information and such as What each information of management.

Referring to Fig.1 7, for example, buffer manager for use 1333b can manage buffer index and logical address.Buffer index can be with Indicate the position of each buffer area of the first internal buffer 1333a.For example, when write-in associated with logical address " 0xA8 " When data D1 is buffered in the buffer area of buffer index " 1 ", buffer manager for use 1333b can manage buffer index and logically Location, so that buffer index " 1 " corresponds to logical address " 0xA8 ".

For example, buffer-manager 1333b may include the memory device for storing buffer index and logical address. Alternatively, the partial memory area of the first internal buffer 1333a can be used to manage buffer index in buffer manager for use 1333b And logical address.

First internal buffer 1333a can be by write-in data buffering in the buffer area of each buffer index.Figure 17 shows The only management write-in data in the buffer area of each buffer index are gone out.However, in some example embodiments, the first inside is slow Rush device 1333a can further manage with the accordingly associated other information of write-in data (for example, logical address, order and/or Flow identifier etc.).

When write-in management circuit 1333 receives data packet PCW1, buffer manager for use 1333b may be in response to data packet PCW1 checks the state of the first internal buffer 1333a.For example, buffer manager for use 1333b can be checked in the number received Whether it has been managed according to the logical address for including in packet PCW1.Therefore, buffer manager for use 1333b can be managed about reception phase With the risk of address or conflict (the operation S330 of Figure 19).

Meanwhile in some cases, the size of the write-in data received from host 1100a may with pass through write-once The program unit for operating the program unit data of storage is of different sizes.In this case, the first internal buffer 1333a can be with A plurality of write-in data are buffered, until having accumulated program unit data about specific flow identifier (the operation S340 of Figure 19).

When accumulating program unit data, available physical address can be distributed to program unit by write-in management circuit 1333 Data (the operation S350 of Figure 19).Therefore, logical address associated with every write-in data of program unit data can be by It is mapped to physical address.It can select the physical address to be distributed from the list of available physical address, the available physical Location is managed by write-in management circuit 1333, data field management circuit 1337 and/or processor 1339.

However, it is possible to select the physical address to be distributed based on the flow identifier of write-in data and corresponding relationship.It returns to Figure 18, buffer manager for use 1333b can manage the corresponding relationship between flow identifier and physical address.Corresponding relationship can be deposited Storage is in the memory device of buffer manager for use 1333b and/or the first internal buffer 1333a.

For example, when program unit data associated with data packet PCW1 has flow identifier " 1 ", it can be based on correspondence Relationship is the available physical address that program unit data distributes storage region MR1.Correspondingly, the head (H) of data packet PCW2 can To include the information of physical address, instruction includes the memory block in storage region MR1.

Back to Figure 16, data packet PCW3 can be supplied to data field management circuit 1337 by write-in management circuit 1333. The head (H) of data packet PCW3 may include the information of the physical address of logical address associated with writing address and distribution. Therefore, data field management circuit 1337 can be managed between logical address and physical address based on the data packet PCW3 received Corresponding relationship.Data field management circuit 1337 can manage the corresponding relationship (operation of Figure 19 in the first metadata MD1 S360).Buffer storage 1350b can store the first metadata MD1.

Write-in management circuit 1333 can prepare data packet PCW2 (the operation S360 of Figure 19) for program unit data.Data Packet PCW2 may include program unit data and the additional information for indicating distributed physical address.Write-in management circuit 1333 can Data packet PCW2 is transferred to memory interface layer 1332.Therefore, data are written and writing commands can be along write paths It is transmitted by write-in management circuit 1333 with the packet unit of stream.

The physical address of program unit data and distribution can be transferred to one or more 1310 (Figure 19 of memory device Operation S370).The write-in data that can be included in program unit data be transferred to by distribute physical address instruction Storage region.Therefore, write-in management circuit 1333 can manage write operation, so that write-in data are based on corresponding relationship and are deposited Storage is in storage region corresponding with flow identifier.

For example, returning to Figure 18, flow identifier can will be had by write-in management circuit 1333 based on the corresponding relationship The write-in data (or program unit data) of " 1 " are transferred to storage region MR1.Here it is possible to will have writing for flow identifier " 1 " Enter data (or program unit data) and be transferred to storage region MR1, whether is received with traffic identifier without tube controller 1330b Accord with the write-in data of " 2 ", " 3 " or " 4 ".Therefore, the write-in data of all flow identifiers can not be completely buffered at the same time, and Therefore the first internal buffer 1333a may be implemented as with low capacity.

In some example embodiments, by multiple between controller 1330b and one or more memory devices 1310 The interleaving access of Fig. 9 and/or the time-division multiplex transmission of Figure 10 can be used in the communication of channel C H.In some example embodiments, may be used With the embodiment to single stream using the example write operation similar to Figure 16 to Figure 19.It, can in these example embodiments Further to improve the performance of write operation.

III-D. it supplements

Figure 20 is the block diagram for showing the example arrangement of storage device 1300 of Fig. 1.The electronic system 1000 of Fig. 1 may include The electronic system 1000c of Figure 20.The storage device 1300 of Fig. 1 may include the storage device 1300c of Figure 20.

Figure 20 is compared with Figure 11 and Figure 14, in some example embodiments, packing device PCZ can be included in host In 1100b, without including in the host interface layer 1331b of controller 1330c.Packing device PCZ can be based in host 1100b Order CMD, data DAT and the address AD DR of middle generation generates data packet.Therefore, controller 1330c can be with host 1100b Exchange data packets PCW or PCR, and first kind operation can be managed based on data packet PCW or PCR pipe.

It can be configured and referring to Fig.1 1 to phase basic those of described in Figure 19 about Figure 20 other component not described With and with referring to Fig.1 1 to substantially alike being operated those of described in Figure 19.For simplicity, extra retouch will be omitted It states.

Such as tradition in the art, it can be described according to the module for executing described one or more functions With each embodiment is shown.These modules (unit or module etc. can be referred to herein as) by such as logic gate, integrated circuit, Microprocessor, microcontroller, storage circuit, passive electrical components, active electronic component, optical component, hard-wired circuitry etc. Analog circuit and/or digital circuit physically realize, and can be optionally by firmware and/or software-driven.These circuits It can be such as implementing in one or more semiconductor chips or on substrate support such as printed circuit board.Constitute module Circuit can be by specialized hardware or by processor (for example, one or more programmed microprocessor and associated circuit) It realizes, or the combination of the processor by the other function of the specialized hardwares and execution module of some functions of execution module To realize.Without departing from the scope of the disclosure, each module of each embodiment can be physically divided into two or more Multiple interactions and isolated module.Similarly, without departing from the scope of the disclosure, the module of each embodiment can To be physically combined into more complicated module.

Above description is intended to provide example arrangement used to implement the present disclosure and operation.In addition to above example embodiment it Outside, the scope of the present disclosure and spirit may include each implementation obtained and simply changing or modifying above example embodiment Mode.In addition, the scope of the present disclosure and spirit include being realized by the way that above example embodiment are subsequently easily altered or modified Each embodiment.

Claims

1. a kind of storage device, comprising:

Nonvolatile memory including storage region；And

Controller is configured that

It is communicated by multiple channels with the nonvolatile memory；

The corresponding relationship between physical address and flow identifier is managed, the physical address indicates the storage region, described Controller receives the first write-in data foregoing description corresponding relationship and is managed in advance；And

The nonvolatile memory is controlled, so that the first write-in data are stored in first among the storage region In storage region, described the is correspondingly managed with the first flow identifier of the first write-in data in the corresponding relationship The physical address of one storage region, wherein

No matter whether the controller receives the second write-in data with the second flow identifier, will based on the corresponding relationship The first write-in data are transferred to the nonvolatile memory.

2. storage device according to claim 1, in which:

Each of described nonvolatile memory includes memory block and a channel being connected in the multiple channel, And

Each of described storage region includes at least one memory block from selecting in the memory block connecting with same channels, With in the multiple channel whole channels or passage portion be optionally comprised in each of described storage region in association In memory block.

3. storage device according to claim 2, wherein the storage region respectively includes connecting from the same channels The different memory blocks selected in the memory block connect.

4. storage device according to claim 2, wherein every in the memory block for including in the nonvolatile memory One block size area corresponded on the nonvolatile memory.

5. storage device according to claim 1, wherein the corresponding relationship is according to the behaviour of the nonvolatile memory Make and changes.

6. storage device according to claim 1, wherein when the size of the first write-in data is big less than program unit Hour, other write-in data of the first write-in data and one or more with first flow identifier are collectively stored in In first storage region.

7. storage device according to claim 1, in which:

The controller is additionally configured to control the nonvolatile memory so that the second write-in data be stored in it is described In the second storage region among storage region, institute is correspondingly managed with second flow identifier in the corresponding relationship The physical address of the second storage region is stated, and

Including in second storage region memory block from include that memory block in first storage region is different.

8. storage device according to claim 7, wherein no matter whether the controller receives with third traffic identifier Data are written in the third of symbol, and the second write-in data are transferred to the nonvolatile memory based on the corresponding relationship.

9. a kind of storage device, comprising:

Nonvolatile memory including storage region；

Buffer storage is configured to buffered data；And

Controller is configured to be communicated with the nonvolatile memory and the buffer storage, so that the first write-in Data and the second write-in data are stored in the nonvolatile memory, in which:

The first write-in data with the first characteristic are stored in first among the storage region of the nonvolatile memory In storage region, and the with the second characteristic second write-in data are stored in the storage region of the nonvolatile memory In the second storage region in, and

Regardless of whether the second write-in data are buffered in the buffer storage, the first write-in data are transferred to The nonvolatile memory.

10. storage device according to claim 9, wherein in the first write-in data and the second write-in data It is buffered in front of the buffer storage, first storage region is determined in advance for storing with first characteristic Write-in data, and second storage region is determined in advance for storing the write-in data with second characteristic.

11. storage device according to claim 9, wherein the controller is additionally configured to: in the first write-in data Before being buffered in the buffer storage with the second write-in data, corresponding relationship is managed in advance, so that with described first Associated first flow identifier of characteristic corresponds to the physical address for indicating first storage region, and with it is described second special Property associated second flow identifier correspond to the physical address for indicating second storage region.

12. storage device according to claim 9, wherein when the size of the first write-in data is less than program unit When size, the buffer storage is additionally configured to the first write-in data and one or more with first characteristic Other write-in data buffer together, the program unit until accumulating described program cell size in association with first characteristic Data.

13. storage device according to claim 12, wherein the controller is additionally configured to and the non-volatile memories Device and the buffer storage are communicated, so that including the first write-in data and described one or more other write-in numbers According to described program cell data be stored in first storage region.

14. storage device according to claim 9, in which:

The controller is additionally configured to communicate by multiple channels with the nonvolatile memory,

Each of described nonvolatile memory includes memory block, and

Each of first storage region and the second storage region are complete in the multiple channel including being connected respectively to The memory block in portion channel or some channels.

15. storage device according to claim 14, wherein the memory block for including in first storage region with it is described The memory block for including in second storage region is different.

16. storage device according to claim 14, in which:

The first write-in data are stored in connecting among the memory block in first storage region included with first passage In the memory block connect, and

When the first passage is not idle, the second write-in data are stored in depositing of including in second storage region In the memory block being connect with second channel among storage area.

17. storage device according to claim 14, wherein by will be a plurality of via the multiple channel interleaving access Data are written and are transmitted to the nonvolatile memory from the controller.

18. storage device according to claim 9, in which:

The controller is additionally configured to communicate via the multiple channel with the nonvolatile memory,

The first frequency that the controller receives the clock of write-in data, which is higher than, non-volatile to be deposited for the controller with described The second frequency of the clock of communication between reservoir, and

The first frequency corresponds to the product of the quantity in the second frequency and the multiple channel.

19. storage device according to claim 9, in which:

First data width of the write-in data received by the controller is greater than via each of the multiple channel Second data width of the data of transmission, and

First data width corresponds to the product of the quantity in second data width and the multiple channel.

20. a kind of storage device, comprising:

Nonvolatile memory comprising storage region；And

Controller is configured to control the nonvolatile memory, so that the first write-in data are stored in the memory block The storage for being used to store the first write-in data is just predefined before receiving the first write-in data among domain In region, wherein

Regardless of whether receiving the second write-in data, the first write-in data are transferred to the nonvolatile memory.

21. storage device according to claim 20, in which:

The controller is additionally configured to: before the controller receives the first write-in data, management in advance is corresponding to be closed System, so that the characteristic of the first write-in data corresponds to the physical address for indicating the storage region, and

The first write-in data are transferred to the storage region based on the corresponding relationship.

22. storage device according to claim 21, wherein be based on the corresponding relationship, will have and be write with described first Another write-in data for entering the identical characteristic of characteristic of data are stored in the storage region.

23. storage device according to claim 20, wherein when the characteristic of the second write-in data is different from described the When the characteristic of one write-in data, the second write-in data are not stored in the storage region.

24. a kind of storage device, comprising:

Nonvolatile memory including storage region；And

Controller comprising:

Job management circuit is configured to management write operation, so that the with the first flow identifier first write-in data are deposited Storage is in the first storage region among the storage region of the nonvolatile memory, and the with the second flow identifier Two write-in data are stored in the second storage region among the storage region of the nonvolatile memory, and

Processor is configured to be managed operation, so that mistake associated with said write operation or abnormal is solved, In:

The job management circuit is additionally configured to manage write operation in the case where no processor is intervened, and

No matter whether the controller receives the second write-in data, the first write-in data that the controller is received It is transmitted to the nonvolatile memory.

25. storage device according to claim 24, wherein the job management circuit includes write-in management circuit, institute State write-in management circuit configuration are as follows: the controller receive it is described first write-in data and it is described second write-in data it Before, corresponding relationship is managed in advance, so that first flow identifier corresponds to the physical address for indicating first storage region, And second flow identifier corresponds to the physical address for indicating second storage region.