CN105024884A - System and method for debugging programmable logic device PLD - Google Patents
System and method for debugging programmable logic device PLD Download PDFInfo
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Abstract
The invention provides a system and a method for debugging a programmable logic device PLD. The method comprises the following steps that: a client sends a PLD debugging request to a service end according to user operations; the service end receives and forwards the PLD debugging request to a FPGA (Field Programmable Gate Array) hardware; the FPGA hardware executes the PLD debugging request, and captures debugging data; the service end receives and forwards the debugging data captured by the FPGA hardware to the client; the client receives the debugging data returned back by the service end. By the embodiment of the invention, the user can initiate debugging at the client, and can finish debugging and receive the debugging data through the service end, thereby, CS frame-based remote debugging of the PLD is realized, the problem that the existing PLD debugging technology is enslaved to JTAG (Joint Test Action Group) cable length and cannot perform remote debugging is solved, and use experience of the user is increased.
Description
Technical field
The present invention relates to programmable logic device field, particularly relate to a kind of Programmable logic design debug system and method.
Background technology
Programmable logic device (programmable logic device, PLD) as application-specific integrated circuit (ASIC) (Application Specific Integrated Circuit, ASIC) a kind of semi-custom circuit in field, the advantage of PLD is adopted to be that client can modification circuits as required in the design phase, until please oneself to design work, once design, client can be put into production immediately, only needs to utilize programme the simply PLD of required quantity of final software design document just passable; Wherein, upper plate debugging is the requisite stage in PLD development process, therefore, is the efficiency and the quality that improve exploitation, needs to adopt effectively, convenient, adjustment method accurately.
In the prior art, for realizing the object of real-time observed data, usually logic built analyzer in PLD, and by combined testing action group (Joint Test Action Group, JTAG) parallel port of debug terminal is connected in this logic analyzer by cable, debug terminal is controlled by analysis software the debug process of veneer logic, tune-up data is transferred on debug terminal, utilize analysis software just can see waveform in logic in real time.
But existing adjustment method needs to use JTAG cable to connect the limited length of FPGA, JTAG cable, cannot carry out remote debugging, secondly, because upper computer software monopolizes JTAG passage, can not reach multi-subscriber time shared and debug; And the interface that debug terminal communicates with PLD is single; Namely existing PLD adjustment method is limited by JTAG cable length and cannot carries out remote debugging, reduces the experience of user.
Therefore, how to provide a kind of can the Programmable logic design adjustment method of remote debugging, be those skilled in the art's technical problems urgently to be resolved hurrily.
Summary of the invention
The invention provides a kind of Programmable logic design debug system and method, can not the problem of remote debugging to solve existing PLD debugging technique.
The invention provides a kind of Programmable logic design debug system, it comprises: client, for sending PLD debug request to service end according to user operation, receives the tune-up data that service end returns; Service end, for receiving and forwarding PLD debug request to FPGA hardware, receive and forward FPGA hardware capture tune-up data to client; FPGA hardware, for performing PLD debug request, and captures tune-up data.
Further, client, also for carrying out filtering screening, combination, contrast process to tune-up data, shows the tune-up data after process by waveform, binary data and curve mode.
Further, client also for user network table and the binding of specific IP kernel, is generated new net meter file, and is sent by PLD debug request.
Further, client also for arranging trigger condition according to user operation, selecting the port checked and the data of gauze, the sampling number of capture-data, and is sent by PLD debug request.
Further, service end, also for storing tune-up data, when receiving client query request, is shown to client.
Further, when client is multiple, service end is after reception PLD debug request to FPGA hardware, also for judging whether FPGA hardware is performing PLD debug request, if so, then notify that client needs to wait for, if not, then FPGA hardware is issued to by driver module.
Further, client is connected by the nested word Socket of TCP/IP with service end, and service end and FPGA hardware are connected by hardware interface.
The invention provides a kind of Programmable logic design adjustment method, it comprises: client sends PLD debug request to service end according to user operation; Service end receives and forwards PLD debug request to FPGA hardware; FPGA hardware performs PLD debug request, and captures tune-up data; Service end receive and forward FPGA hardware capture tune-up data to client; Client receives the tune-up data that service end returns.
Further, also comprise: client carries out filtering screening, combination, contrast process to tune-up data, show the tune-up data after process by waveform, binary data and curve mode.
Further, also comprise: client user nets table and the binding of specific IP kernel, generates new net meter file, and is sent by PLD debug request.
Further, also comprise: the port that client arranges trigger condition according to user operation, selection is checked and the data of gauze, the sampling number of capture-data, and sent by PLD debug request.
Further, also comprise: service end stores tune-up data, when receiving client query request, shows to client.
Further, when client is multiple, service end is after reception PLD debug request to FPGA hardware, also comprise: judge whether FPGA hardware is performing PLD debug request, if so, then notify that client needs to wait for, if not, then FPGA hardware is issued to by driver module.
Further, client is connected by the nested word Socket of TCP/IP with service end, and service end and FPGA hardware are connected by hardware interface.
Beneficial effect of the present invention:
The invention provides a kind of PLD adjustment method, comprise client and service end, such user just can initiate debugging in client, and the reception of debugging and tune-up data is completed by service end, achieve the PLD remote debugging based on CS framework, solve existing PLD debugging technique be limited by JTAG cable length and the problem of remote debugging cannot be carried out, add the experience of user.
Accompanying drawing explanation
The structural representation of the PLD debug system that Fig. 1 provides for first embodiment of the invention;
The flow chart of the PLD adjustment method that Fig. 2 provides for second embodiment of the invention;
The flow chart of the PLD adjustment method that Fig. 3 provides for third embodiment of the invention;
Fig. 4 is the structural representation of client in third embodiment of the invention;
Fig. 5 is the flow chart that in third embodiment of the invention, client inserts kernel function;
Fig. 6 is the structural representation of service end in third embodiment of the invention;
Fig. 7 is the structural representation of FPGA hardware in third embodiment of the invention;
Fig. 8 is the form schematic diagram of Socket message in third embodiment of the invention.
Embodiment
Now by embodiment mode by reference to the accompanying drawings the present invention made and further annotate explanation.
First embodiment:
The structural representation of the PLD debug system that Fig. 1 provides for first embodiment of the invention, as shown in Figure 1, in the present embodiment, PLD debug system provided by the invention comprises:
Client 1, for sending PLD debug request to service end according to user operation, receives the tune-up data that service end returns;
Service end 2, for receiving and forwarding PLD debug request to FPGA hardware, receive and forward FPGA hardware capture tune-up data to client;
FPGA hardware 3, for performing PLD debug request, and captures tune-up data.
In certain embodiments, the client 1 in above-described embodiment, also for carrying out filtering screening, combination, contrast process to tune-up data, shows the tune-up data after process by waveform, binary data and curve mode.
In certain embodiments, the client 1 in above-described embodiment also for user network table and the binding of specific IP kernel, is generated new net meter file, and is sent by PLD debug request.
In certain embodiments, the client 1 in above-described embodiment also for arranging trigger condition according to user operation, selecting the port checked and the data of gauze, the sampling number of capture-data, and is sent by PLD debug request.
In certain embodiments, the service end 2 in above-described embodiment, also for storing tune-up data, when receiving client query request, is shown to client.
In certain embodiments, when client 1 is multiple, service end 2 in above-described embodiment is after reception PLD debug request to FPGA hardware, also for judging whether FPGA hardware is performing PLD debug request, if, then notify that client needs to wait for, if not, be then issued to FPGA hardware by driver module.
In certain embodiments, the client 1 in above-described embodiment is connected by the nested word Socket of TCP/IP with service end 2, and service end 2 and FPGA hardware 3 are connected by hardware interface.
Second embodiment:
The flow chart of the PLD adjustment method that Fig. 2 provides for second embodiment of the invention, as shown in Figure 2, in the present embodiment, PLD adjustment method provided by the invention comprises the following steps:
S201: client sends PLD debug request to service end according to user operation;
S202: service end receives and forwards PLD debug request to FPGA hardware;
S203:FPGA hardware performs PLD debug request, and captures tune-up data;
S204: service end receive and forward FPGA hardware capture tune-up data to client;
S205: client receives the tune-up data that service end returns.
In certain embodiments, the method in above-described embodiment also comprises: client carries out filtering screening, combination, contrast process to tune-up data, shows the tune-up data after process by waveform, binary data and curve mode.
In certain embodiments, the method in above-described embodiment also comprises: client user nets table and the binding of specific IP kernel, generates new net meter file, and is sent by PLD debug request.
In certain embodiments, the method in above-described embodiment also comprises: the port that client arranges trigger condition according to user operation, selection is checked and the data of gauze, the sampling number of capture-data, and is sent by PLD debug request.
In certain embodiments, the method in above-described embodiment also comprises: service end stores tune-up data, when receiving client query request, shows to client.
In certain embodiments, when client is multiple, service end in above-described embodiment is after reception PLD debug request to FPGA hardware, also comprise: judge whether FPGA hardware is performing PLD debug request, if, then notify that client needs to wait for, if not, be then issued to FPGA hardware by driver module.
In certain embodiments, the client in above-described embodiment is connected by the nested word Socket of TCP/IP with service end, and service end and FPGA hardware are connected by hardware interface.
Now in conjunction with embody rule scene, Fig. 3-Fig. 8 the present invention done and further annotate explanation.
3rd embodiment:
The flow chart of the PLD adjustment method that Fig. 3 provides for third embodiment of the invention, as shown in Figure 3, in the present embodiment, PLD adjustment method provided by the invention comprises the following steps:
S301: client 1 generates bit stream file.
In client 1, user network list file is carried out slotting core, and through comprehensive, after placement-and-routing, generate bit stream file.
S302: client 1 and service end 2 connect.
Input IP and the port of service end in client 1, set up and be connected with the Socket of service end 2.
S303: service end 2 and FPGA hardware 3 connect.
Service end 2 and FPGA hardware 3, connected by driver module and hardware interface.
S304: client 1 obtains the information of FPGA hardware 3.
Client 1 issues request obtains FPGA hardware 3 information to service end 2, and the information such as such as Device ID, UserCode, command length, FPGA device name, then shows the icon of FPGA on client 1A.
S305: client 1 sends bit stream file.
Client 1 selects FPGA icon on interface, and download bit stream in appointment FPGA, bit stream file is sent to service end 2 by ICP/IP protocol by client 1.
S306: service end 2 downloads bit stream file.
Bit stream file downloads in the chip of FPGA hardware by driving the agreement of layer by service end 2 again.
The tune-up data of FPGA inside caught by S307:FPGA hardware 3.
FPGA, according to the trigger condition arranged, captures the data satisfied condition, and is stored in internal RAM, by dynamically arranging trigger condition and sampled point in client 1, can then be issued to the configuration register of FPGA hardware.
S308: service end 2 obtains and sends tune-up data to client 1.
After data storage meets the requirements of sampled point, service end 2, with regard to the data of retaking of a year or grade FPGA internal RAM, stores in the local database, then sends to client 1.
S309: client 1 shows tune-up data.
The data display that service end sends is waveform, binary data and curve intuitively by client 1.User can pass through filtration, screening, combination, contrast etc., realizes the interfacial effect of logic analyzer, reaches the object of oneself debugging.
Multiple client 1 is in the request that issues in service end process, and have equal status, service end 2, according to the request arriving first the principle process different clients first processed, in order to process concurrent request, adopts mutual exclusion lock in service end 2.If current service end 2 is processing the request of the first client 1, and the second client 1 sends request to service end 2, then service end 2 is notifying that the second client 1 is waited for, until the request of the first client 1 completes.
Now the FPGA remote debugging system that the invention provides based on CS framework is introduced:
1, client:
As shown in Figure 4, in the present embodiment, client 1 comprises: first communication module 11, display module 12, data management module 12, slotting core module 14.Wherein, first communication module 11 is for sending request, and the data that reception service end returns; Display module 12 is for by FPGA data display being waveform, binary data and curve intuitively; Data management module 13, for the filtering screening, combination, contrast etc. of data, realizes the interfacial effect of logic analyzer; Insert core module 14 for user network table and specific IP kernel being bound, generate new net meter file, realize the function of similar logic analyzer, can trigger condition be set, select the data of port and the gauze (Net) checked, the sampling number etc. of capture-data.
Concrete, first communication module 11 has three major functions:
Obtain service end IP address and the port of display module 12 input, set up and ask with the Socket of service end.
By the request msg of data management module 13, send to the communication module 21 of service end 2.
Receive the FPGA tune-up data that service end 2 sends, and submit to data management module 13.
Display module 12 is the entrance of user operation and the window of FPGA tune-up data displaying:
The all of user interface issue request, are sent to data management module 13 with asynchronous information, and data module 13 converts it into command code, and are packaged into specific form (as shown in Figure 8), then submit to first communication module 11.
The FPGA tune-up data that data management module 13 will receive, submits to display module 12 and is illustrated on interface with the form of lines, chart, word.The operation that user can sort, combine, arranges screening conditions, compares lines, chart, word, these operations complete process by data management module 13.
Data management module 13 is nucleus modules of client 1, plays a part to connect first communication module 11, display module 12 and slotting core module 14, and is the center of data processing.
Insert core module 14: on display module 12, select user's design netlist file user.vm, insert core module 14 by after parsing user.vm, port (Port), gauze (Net) and pin (Pin) are illustrated on the window of display module 12, user can select Port, Net and Pin to be seen, and configuration parameter (trigger condition, trigger element, sampled point, storage condition etc.) carrys out the specific IP kernel of instantiation on display module 12, and generate core.v, use the comprehensive core.v of Synplify Pro to generate intermediate file core.vm.Finally use user.vm as top layer module, call core.vm and generate a user_ic.vm, complete slotting kernel function, as shown in Figure 5, repeat no more.
2, service end:
As shown in Figure 6, in the present embodiment, service end 2 comprises: second communication module 21, administration module 22, driver module 23, memory module 24.Wherein, second communication module 21 is resolved for client 1 data receiver, and data packing transmission waits work; Administration module 22 is the main modular of service end 2, the data that process different clients sends, and generate a task to process, when a task does not complete, new client-requested is had to come, just return and notify that client user waits for, client-requested is issued in FPGA by driver module by new task; Driver module 23 is for realizing the function with FPGA hardware communications.Driver module communicates with FPGA can by parallel port, USB port, network interface; Memory module 24 for storing the FPGA data of crawl, for inquiry and the displaying of client historical data.
Concrete,
Second communication module 21 monitors client Socket connection request, and connects with client, then distributes each client of Unique ID, and message queue is put in the request of client.If current message queue non-NULL, send message and wait for Client-Prompt user.
Administration module 22 is according to the message arrived first in the mode processing messages queue first processing (FIFO), resolve message bag (message shown in Fig. 8), obtain operand, operational order and business datum, and message bag is verified, then call diverse ways according to different operational orders, issue request to FPGA hardware module by driver module 24.Administration module 22 obtains hardware FPGA tune-up data by driver module 24, and the interface method then calling memory module 23 saves the data in database, finally sends to client after the encapsulation of FPGA tune-up data by communication module 21.
Digital independent between memory module 23 fulfillment database and administration module 22 and hold function.
Driver module 24 realizes conventional communication interface standard, such as USB, parallel port, RJ-45, RS-232, realizes and FPGA hardware communications.
3, FPGA hardware
FPGA hardware 3 mainly utilizes client that user network table and specific IP kernel are completed slotting core, after generating bit stream file, downloaded in fpga chip by bit stream file and run, FPGA is stored in needing the data of catching in RAM, and storage data are sent to service end according to specific format.
As shown in Figure 7, FPGA hardware 3 comprises: hardware interface 31, IP debugging core 32, internal RAM 33 and user's netlist data 34.Wherein,
Hardware interface 31 is FPGA hardware physical interfaces, is connected by hard wires with the driver module 24 of service end.
IP debugging core 32 is special I P Core, realizes the function of similar logic analyzer, and it is user's net table after client is by the slotting core of slotting core module generation, generates bit stream file, the logic finally run in FPGA.IP debugging core 32 is connected by FPGA global technique operator (GTP) with hardware interface 31, and the read-write realizing data is mutual.
The parameter that IP debugging core 32 will be arranged according to user, capture the tune-up data of user's netlist data 34, and be stored in internal RAM 33, when the data in internal RAM 33 reach sampling number, IP debugging core 32 reads the data in RAM, and sends to service end.
User's netlist data 34 is dynamic datas that user's design netlist performs in FPGA inside.
The on-line debugging method based on CS framework that the present embodiment provides, be linked into service end by client and realize remote debugging, realize the object of multiple user time-sharing debugging simultaneously, drive port to enrich, take into account the object of the flexibility of debugging, simplification and real-time simultaneously, improve the efficiency of debugging.
In summary, by enforcement of the present invention, at least there is following beneficial effect:
PLD debug system provided by the invention comprises client and service end, such user just can initiate debugging in client, and the reception of debugging and tune-up data is completed by service end, achieve the PLD remote debugging based on CS framework, solve existing PLD debugging technique be limited by JTAG cable length and the problem of remote debugging cannot be carried out, add the experience of user;
Further, the client of CS structure can arrange multiple as required, and solving existing adjustment method can not the defect of multi-subscriber time shared debugging, takes into account the object of the flexibility of debugging, simplification and real-time simultaneously, improves the efficiency of debugging;
Further, service end communicates based on hardware interface with FPGA hardware, solves the problem that existing adjustment method connecting interface is single.
Below be only the specific embodiment of the present invention; not any pro forma restriction is done to the present invention; every above execution mode is done according to technical spirit of the present invention any simple modification, equivalent variations, combination or modification, all still belong to the protection range of technical solution of the present invention.
Claims (14)
1. a Programmable logic design debug system, is characterized in that, comprising:
Client, for sending PLD debug request to service end according to user operation, receives the tune-up data that described service end returns;
Service end, for receiving and forwarding described PLD debug request to FPGA hardware, receives and forwards tune-up data that described FPGA hardware captures to described client;
FPGA hardware, for performing described PLD debug request, and captures described tune-up data.
2. Programmable logic design debug system as claimed in claim 1, it is characterized in that, described client, also for carrying out filtering screening, combination, contrast process to described tune-up data, shows the tune-up data after process by waveform, binary data and curve mode.
3. Programmable logic design debug system as claimed in claim 1, is characterized in that, described client also for user network table and the binding of specific IP kernel, is generated new net meter file, and sent by described PLD debug request.
4. Programmable logic design debug system as claimed in claim 3, it is characterized in that, described client also for arranging trigger condition according to user operation, selecting the port checked and the data of gauze, the sampling number of capture-data, and is sent by described PLD debug request.
5. Programmable logic design debug system as claimed in claim 1, it is characterized in that, described service end, also for storing described tune-up data, when receiving described client query request, is shown to described client.
6. the Programmable logic design debug system as described in any one of claim 1 to 5, it is characterized in that, when described client is multiple, described service end is after reception described PLD debug request to FPGA hardware, also for judging whether described FPGA hardware is performing PLD debug request, if so, then notify that described client needs to wait for, if not, then described FPGA hardware is issued to by driver module.
7. the Programmable logic design debug system as described in any one of claim 1 to 5, it is characterized in that, described client is connected by the nested word Socket of TCP/IP with described service end, and described service end and described FPGA hardware are connected by hardware interface.
8. a Programmable logic design adjustment method, is characterized in that, comprising:
Client sends PLD debug request to service end according to user operation;
Service end receives and forwards described PLD debug request to FPGA hardware;
FPGA hardware performs described PLD debug request, and captures described tune-up data;
Described service end receives and forwards the tune-up data extremely described client of described FPGA hardware crawl;
Described client receives the tune-up data that described service end returns.
9. Programmable logic design adjustment method as claimed in claim 8, it is characterized in that, also comprise: described client carries out filtering screening, combination, contrast process to described tune-up data, show the tune-up data after process by waveform, binary data and curve mode.
10. Programmable logic design adjustment method as claimed in claim 8, is characterized in that, also comprise: described client user nets table and the binding of specific IP kernel, generates new net meter file, and is sent by described PLD debug request.
11. Programmable logic design adjustment methods as claimed in claim 10, it is characterized in that, also comprise: the port that described client arranges trigger condition according to user operation, selection is checked and the data of gauze, the sampling number of capture-data, and sent by described PLD debug request.
12. Programmable logic design adjustment methods as claimed in claim 8, is characterized in that, also comprise: described service end stores described tune-up data, when receiving described client query request, showing to described client.
13. Programmable logic design adjustment methods as described in any one of claim 8 to 12, it is characterized in that, when described client is multiple, described service end is after reception described PLD debug request to FPGA hardware, also comprise: judge whether described FPGA hardware is performing PLD debug request, if so, then notify that described client needs to wait for, if not, then described FPGA hardware is issued to by driver module.
14. Programmable logic design adjustment methods as described in any one of claim 8 to 12, it is characterized in that, described client is connected by the nested word of TCP/IP with described service end, and described service end and described FPGA hardware are connected by hardware interface.
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| CN106650006A (en) * | 2016-11-17 | 2017-05-10 | 深圳市紫光同创电子有限公司 | Programmable logic device debugging method and system, and electronic design automation terminal |
| WO2020259523A1 (en) * | 2019-06-28 | 2020-12-30 | 深圳市紫光同创电子有限公司 | Host and method for communicating with fpga, and fpga interface chip |
| CN112255534A (en) * | 2020-10-14 | 2021-01-22 | 天津津航计算技术研究所 | IP core module debugging system based on FPGA |
| CN112541313A (en) * | 2020-12-24 | 2021-03-23 | 山东高云半导体科技有限公司 | Method and device for configuring trigger expression for logic analysis state |
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