CN114756423B - Software and hardware combined fault injection device and method for EDAC (electronic design automation) - Google Patents
Software and hardware combined fault injection device and method for EDAC (electronic design automation) Download PDFInfo
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Abstract
The invention discloses a fault injection device and method combining software and hardware aiming at EDAC (electronic design automation), wherein the device comprises upper-layer software, a read-write data and control bus, an error correction module, a fault injection circuit and a storage medium; the upper layer software reads and writes the storage medium through the read-write data and the control bus, the error correction module is connected between the read-write data and the control bus and the storage medium in series, and the error correction module is used for generating an error correction code corresponding to the write-in data and modifying and correcting the data and the error correction code; according to the scheme, an error correction switch module for switching an error correction module is added in the original design, and the working states of an error injection module and an error reading module of the error correction code are controlled; and when fault injection is carried out, the error correction module or the error correction code error injection module is closed, so that data fault injection and error correction code fault injection to the storage medium are realized.
Description
Technical Field
The invention relates to the technical field of integrated circuit safety Detection, in particular to a fault injection device And a fault injection method combining software And hardware aiming at Error Detection And Correction (EDAC).
Background
The fault injection technology is a technology for evaluating the effectiveness of fault-tolerant design development and is a technology for simulating the generation of faults. At present, a plurality of fault injection methods are mainly classified into a software fault injection method, a hardware fault injection method and a simulation fault injection method according to implementation modes. For fault simulation of the SEU (Sustainable Energy Utility) effect, bit data flips are mainly produced in the memory cells. For a storage device with a fault-tolerant function, the storage device generally consists of a data storage space and an error correction data storage space, if software is used for directly aiming at a certain address, and the data of the corresponding error correction data storage space is required to be modified, so that the original data is damaged, and the simulation of the benefit of the SEU is difficult to realize.
In view of the above, document [1] proposes an embedded hardware fault injection method, in which a related fault injection circuit is added to a circuit to achieve the purpose of fault injection.
The method carries out SEU fault injection aiming at a storage space with an error correction function, wherein the SEU fault injection comprises fault injection of data bits and fault injection of error correction code bits; a fault injection module is required to be added into a designed circuit, and the problems of online fault injection and detection are realized in a software and hardware matching mode.
[1] Xinminrui, a fault-tolerant RISC processor architecture study for space-oriented applications [ D ]. northwest university of industry.
Disclosure of Invention
In the prior art, the invention aims to provide a fault injection device which is convenient to install and reasonable in structure.
In order to achieve the purpose, the invention provides the following technical scheme:
a fault injection device combining software and hardware aiming at EDAC comprises upper layer software, a read-write data and control bus, an error correction module, a fault injection circuit and a storage medium;
the upper layer software reads and writes the storage medium through the read-write data and the control bus, the error correction module is connected between the read-write data and the control bus and the storage medium in series, and the error correction module is used for generating an error correction code corresponding to the write-in data and modifying and correcting the read-out error data through the generated error correction code;
the fault injection circuit comprises an error correction code error injection module, an error correction switch module and an error correction code reading module; the error injection module of the error correcting code is connected in series between the storage medium and the error correcting module and is used for turning over a bit in the error correcting code; the error correction switch module is connected with upper-layer software and is used for controlling the on and off of the error correction module, the error correction code error injection module and the error correction code reading module; the error correction code reading module is connected with the error injection module of the error correction code and is used for reading the error correction code in the storage medium.
Further, the storage medium includes a data storage area for storing data and an error correction code storage area for storing an error correction code.
Furthermore, the error correcting code reading module reads the error correcting code in the error correcting code storage area and is used for confirming whether the error correcting code is modified or not; and the error correcting code reading module is connected with upper-layer software through an error correcting switch module.
In addition, the invention also provides a fault injection method aiming at the combination of software and hardware of the EDAC, which comprises the following specific steps:
when data fault injection is carried out on the storage medium, an error correction module is started, and the error injection function of the error correction code error injection module is closed; controlling upper software to write data into the storage medium and writing the error correction code generated by the error correction module into the storage medium; controlling upper software to read data of a certain address, closing the error correction function of an error correction circuit, turning over a certain bit in the data, and writing the turned data into the address; controlling upper-layer software to read out the data in the address and the error correcting code related to the data, and verifying that the fault injection circuit can realize the function of data fault injection if the read data in the address is different from the original data; then, controlling the upper layer software to start an error correction module through an error correction switch module, controlling the upper layer software to read out the data in the address and an error correction code related to the data, and controlling the error correction module to correct the read error data; if the read data in the address is the same as the original data, the error correction function of the error correction module is verified;
when error correction code fault injection is carried out on the storage medium, an error correction module is started, and the error injection function of the error correction code error injection module is started; controlling upper software to write data into a certain address of the storage medium and controlling an error correction module to generate an error correction code corresponding to the data; then, controlling an error injection module of the error correcting code to overturn a certain bit in the error correcting code and write the bit into a storage medium; then, controlling upper software to read out the data of the address and the corresponding error correcting code and process the data through an error correcting module, sending the error correcting code into an error correcting code reading module to be read, and controlling an error correcting switch module to upload the error correcting code to the upper software; and comparing the written and read data with the error correcting code, and if the error correcting code corresponding to the data is different from the read error correcting code and the written and read data is unchanged, indicating that the error injection module can modify bit bits of the error correcting code, and verifying that the fault injection circuit can realize the function of fault injection on the error correcting code.
Furthermore, the upper layer software controls the on and off of the error injection module, the error switch module and the error reading module of the error correction code through the software configuration of the error correction switch module.
Furthermore, in error correction code fault injection, the upper layer software compares the read data with the written data, generates an error correction code corresponding to the data according to an error correction code generation algorithm, compares the error correction code with the read error correction code, and judges whether the read error correction code is modified.
By adopting the technical scheme, compared with the prior art, the invention has the beneficial effects that:
in the scheme, an error correction switch module for switching an error correction module is added in the original design, and the working states of an error injection module and an error reading module of the error correction code are controlled; and when fault injection is carried out, the error correction module or the error correction code error injection module is closed, so that data fault injection and error correction code fault injection to the storage medium are realized.
The fault injection device adopts a fault injection technology combining EDAC and software and hardware, can conveniently and flexibly perform analog simulation of fault injection on hardware platforms such as computers, achieves the effect of fault injection by changing stored values in a storage medium, and can meet the requirements of engineering and experiments by operating the fault injection device; the reliability of the fault-tolerant technology is verified and evaluated by aiming at the EDAC and the fault injection technology combining software and hardware, so that the verification period is greatly shortened, and great convenience is brought to the development process of the hardware.
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In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the description below are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic structural framework diagram of the fault injection device of the present invention.
FIG. 2 is a flow chart illustrating data fault injection according to the present invention.
FIG. 3 is a flow chart of error correction code fault injection according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in one of fig. 1 to fig. 3, the present solution provides a fault injection apparatus combining software and hardware for EDAC, which includes upper layer software, a read-write data and control bus, an error correction module, a fault injection circuit, and a storage medium;
referring to fig. 1, the upper layer software reads and writes the storage medium through the read/write data and the control bus, and the error correction module is connected in series between the read/write data and the control bus and the storage medium and is used for generating an error correction code corresponding to the write data and modifying and correcting the read error data through the generated error correction code;
the fault injection circuit comprises an error correction code error injection module, an error correction switch module and an error correction code reading module; the error injection module of the error correcting code is connected in series between the storage medium and the error correcting module and is used for turning over a bit in the error correcting code; the error correction switch module is connected with the upper layer software and is used for controlling the on and off of the error correction module, the error correction code error injection module and the error correction code reading module; the error correction code reading module is connected with the error injection module and is used for reading the error correction code in the storage medium.
The upper layer software controls the error correction switch module by using software configuration, so that the on and off of the error correction module, the error correction code error injection module and the error correction code reading module are realized; according to the fault injection circuit, performing fault injection of data or fault injection of an error correcting code, controlling upper-layer software to control the on-off of an error correcting module and an error injection module of the error correcting code through a software configuration error correcting switch module so as to realize that a certain bit of the data and the error correcting code is turned over and written into a storage medium; the fault injection circuit can independently turn over the error correcting code or a certain bit of data and write the error correcting code into the storage medium, so that SEU benefit simulation of the storage medium is realized; meanwhile, the error correction capability of the error correction module for fault simulation of the SEU effect is effectively checked.
Wherein the storage medium includes a data storage area for storing data and an error correction code storage area for storing an error correction code; the upper layer software reads and writes the stored data in the data storage area through the read-write data and the control bus, and writes the error correction code generated by the error correction module and corresponding to the data into the error correction code storage area, and the error correction module and the error correction code reading module can both read the error correction code in the error correction code storage area.
Generally, the error correction code storage area is software-inaccessible; therefore, the scheme is additionally provided with an error injection module and an error reading module of the error correction code, and the error injection module and the error reading module are used for fault injection and fault injection inquiry of the storage medium.
The error correction code reading module is used for reading out the error correction code in the error correction code storage region, confirming whether a bit in the error correction code is turned over or not and confirming the modification effect of the error injection module of the error correction code on the error correction code through the error correction code reading module; the error correcting code reading module is connected with the upper layer software through the error correcting switch module, so that the upper layer software realizes a closed loop for turning over and confirming a certain bit in the error correcting code, and the fault injection efficiency of the error correcting code is greatly improved.
In addition, the invention also provides a fault injection method, which comprises the following specific steps:
referring to fig. 2, when the upper layer software performs data failure injection to the storage medium,
(a) the upper layer software utilizes the software to configure the error correction switch module to start the error correction module and close the error injection function of the error correction code error injection module;
(b) controlling upper software to write data into the storage medium and writing the error correction code generated by the error correction module into the storage medium;
(c) controlling upper software to read data D of the address A, and configuring an error correction switch module by using the software so as to close the error correction function of the error correction module; turning a bit in the data D by upper software to generate data D ', and writing the modified data D' into the address A;
(d) controlling upper software to read out the data in the address A and an error correcting code M related to the data; if the data D' in the address A is different from the original data D, verifying that the fault injection circuit can realize the function of data fault injection;
(e) the upper layer software controls the error correction switch module to start the error correction module through software configuration, controls the upper layer software to read out the data in the address A and the error correction code M related to the data, and controls the error correction module to correct the read data D' so as to generate data D; if the data in the address is the same as the original data, the error correction function of the error correction module is verified;
therefore, the data fault injection of the storage medium is realized through the mutual matching of the upper layer software and the fault injection circuit, the data D of the address A in the data storage area of the storage medium can be independently modified, the value of the error correcting code M is not influenced, and the SEU effect of a certain bit in the data storage area of the storage medium is effectively simulated; meanwhile, the error correction function of the error correction module on the data in the data storage area is verified.
Referring to fig. 3, when error correction code fault injection is performed on a storage medium,
(a) the upper layer software utilizes the software configuration error correction switch module to start the error correction module and start the error injection function of the error correction code error injection module;
(b) controlling upper software to write data E into an address B of a storage medium and generating an error correction code N corresponding to the data through an error correction module;
(c) a certain bit in the error correcting code N is turned over through an error correcting code error injection module, so that an error correcting code N' is generated and written into an error correcting code storage area of the storage medium;
(d) controlling upper-layer software to read the data E of the address B and the corresponding error correcting code N ' and process the data E through an error correcting module, sending the error correcting code N ' into the error correcting code reading module to read, and controlling an error correcting switch module to upload the error correcting code N ' to the upper-layer software;
(e) and comparing the written and read data with the error correcting code, and if the error correcting code corresponding to the data is different from the read error correcting code and the written and read data is unchanged, indicating that the error correcting code error injection module can perform bit inversion on the error correcting code, and verifying that the fault injection circuit can realize the function of fault injection on the error correcting code.
Further, the upper layer software compares the data read from the address B with the data written to the address B, generates an error correction code N corresponding to the data E for the data E of the address B according to an error correction code generation algorithm, and compares the error correction code N with the read error correction code N', and determines whether the read error correction code is modified.
Therefore, error correction code fault injection is carried out on the storage medium through mutual matching of the upper layer software and the fault injection circuit, the error correction code N corresponding to the data E in the error correction code storage area of the storage medium can be independently modified, and the value of the data E is not influenced; and furthermore, the SEU effect of a certain bit in the error correction code storage area of the storage medium is effectively simulated, and meanwhile, the error correction function of the error correction module on the error correction code in the error correction code storage area is verified.
In summary, the scheme adds an error correction switch module for switching the error correction module in the original design, and controls the working states of the error injection module and the error reading module of the error correction code; and when fault injection is carried out, the error correction module or the error correction code error injection module is closed, so that data fault injection and error correction code fault injection to the storage medium are realized.
The invention adopts the fault injection technology aiming at EDAC and combining software and hardware, can conveniently and flexibly carry out analog simulation of fault injection on hardware platforms such as computers, achieves the effect of fault injection by changing the stored value in the storage medium, and can meet the requirements of engineering and experiments by the operation of the fault injection circuit. The reliability of the fault-tolerant technology is verified and evaluated by aiming at the EDAC and the fault injection technology combining software and hardware, so that the verification period is greatly shortened, and great convenience is brought to the development process of the hardware.
The above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (5)
1. A software and hardware combined fault injection device for EDAC is characterized in that: the device comprises upper software, a read-write data and control bus, an error correction module, a fault injection circuit and a storage medium; the upper layer software reads and writes the storage medium through the read-write data and the control bus, the error correction module is connected between the read-write data and the control bus and the storage medium in series, and the error correction module is used for generating an error correction code corresponding to the write-in data and modifying and correcting the read-out error data through the generated error correction code;
the fault injection circuit comprises an error correction code error injection module, an error correction switch module and an error correction code reading module; the error injection module of the error correcting code is connected in series between the storage medium and the error correcting module and is used for turning over a bit in the error correcting code; the error correction switch module is connected with upper-layer software and is used for controlling the on and off of the error correction module, the error correction code error injection module and the error correction code reading module; the error correction code reading module is connected with the error injection module of the error correction code and is used for reading the error correction code in the storage medium;
the upper layer software is used for comparing the read data with the written data and judging whether the read data is modified or not; and generating an error correction code corresponding to the written data according to an error correction code generation algorithm, comparing the error correction code with the read error correction code, and judging whether the read error correction code is modified.
2. The EDAC hardware and software combined fault injection device of claim 1, wherein: the storage medium includes a data storage area for storing data and an error correction code storage area for storing an error correction code.
3. The EDAC hardware and software combined fault injection device of claim 1, wherein: and the error correction code reading module reads the error correction codes in the error correction code storage area and is connected with upper-layer software through the error correction switch module.
4. A method for fault injection of hardware and software of an EDAC, which is applied to the apparatus of any one of claims 1 to 3, wherein: the fault injection method comprises the following steps:
when data fault injection is carried out on the storage medium, an error correction module is started, and the error injection function of the error correction code error injection module is closed; controlling upper software to write data into the storage medium and writing the error correction code generated by the error correction module into the storage medium; controlling upper software to read data of a certain address, closing the error correction function of an error correction circuit, turning over a certain bit in the data, and writing the turned data into the address; controlling upper-layer software to read out the data in the address and the error correcting code related to the data, and verifying that the fault injection circuit can realize the function of data fault injection if the read data in the address is different from the original data; then, controlling the upper layer software to start an error correction module through an error correction switch module, controlling the upper layer software to read out the data in the address and an error correction code related to the data, and controlling the error correction module to correct the read error data; if the read data in the address is the same as the original data, the error correction function of the error correction module is verified;
when error correction code fault injection is carried out on the storage medium, an error correction module is started, and the error injection function of the error correction code error injection module is started; controlling upper software to write data into a certain address of the storage medium and controlling an error correction module to generate an error correction code corresponding to the data; then, controlling an error injection module of the error correcting code to overturn a certain bit in the error correcting code and write the bit into a storage medium; then, controlling upper software to read out the data of the address and the error correcting code corresponding to the address and process the data through an error correcting module, sending the error correcting code into the error correcting code reading module for reading, and controlling an error correcting switch module to upload the error correcting code to the upper software; comparing the written and read data with the error correcting code, and if the error correcting code corresponding to the data is different from the read error correcting code and the written and read data is unchanged, indicating that the error injection module can modify bit bits of the error correcting code, verifying that the fault injection circuit can realize the function of fault injection on the error correcting code;
in the error correction code fault injection, the upper layer software compares the read data with the written data, generates an error correction code corresponding to the written data according to an error correction code generation algorithm, compares the error correction code with the read error correction code, and judges whether the read error correction code is modified.
5. The EDAC hardware and software combined fault injection method according to claim 4, wherein: the upper layer software controls the on and off of the error injection module, the error correction switch module and the error correction code reading module through the software configuration of the error correction switch module.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6886116B1 (en) * | 2001-07-26 | 2005-04-26 | Emc Corporation | Data storage system adapted to validate error detection logic used in such system |
| CN108766501A (en) * | 2018-05-31 | 2018-11-06 | 西安微电子技术研究所 | A kind of the storage failure injection design and verification method fault-tolerant with EDAC |
| CN213210202U (en) * | 2020-07-08 | 2021-05-14 | 维尔世创(北京)科技有限公司 | Integrated trouble injection case that has multichannel test channel |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9436546B2 (en) * | 2014-04-22 | 2016-09-06 | Freescale Semiconductor, Inc. | Apparatus for error detection in memory devices |
| CN108710551B (en) * | 2018-04-28 | 2021-12-07 | 北京轩宇信息技术有限公司 | SPARC processor-based single event upset fault injection test method and system |
-
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- 2022-06-16 CN CN202210681117.5A patent/CN114756423B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6886116B1 (en) * | 2001-07-26 | 2005-04-26 | Emc Corporation | Data storage system adapted to validate error detection logic used in such system |
| CN108766501A (en) * | 2018-05-31 | 2018-11-06 | 西安微电子技术研究所 | A kind of the storage failure injection design and verification method fault-tolerant with EDAC |
| CN213210202U (en) * | 2020-07-08 | 2021-05-14 | 维尔世创(北京)科技有限公司 | Integrated trouble injection case that has multichannel test channel |
Non-Patent Citations (1)
| Title |
|---|
| 星载机检错纠错模拟系统设计与实现;张志洲，李东阳;《实验室研究与探索》;20180731;第37卷(第7期);第72-80页 * |
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