CN104835535A - Solid disc self-adaptive error correction method and system - Google Patents

Abstract

The invention discloses a solid disc self-adaptive LDPC (Low-Density Parity-Check) error correction method which comprises the following steps: (1) initializing, namely, before data is input into a solid disc, performing block erase operation, and initializing error correction code identifiers of all erased blocks; (2) performing solid disc self-adaptive error correction encoding, namely, encoding written original data to generate codes; and (3) performing solid disc decoding, namely, (3.1) judging whether read operation is performed or not, if read operation is performed, turning to a step (3.2), otherwise, ending the operation; (3.2) judging whether an error correction code identifier Bi of a block i with reading pages is 0 or not; (3.3) if Bi is 0, correcting errors in all pages in the block i by using weak LDPC codes; (3.4) performing solid disc self-adaptive error correction code switching operation; and (3.5) if Bi is 1, correcting errors of all pages in the block i by using strong LDPC codes. The solid disc self-adaptive LDPC error correction method is applicable to the field of solid disc error correction, the error correction property of LDPC is improved and brought into sufficient play, and the reliability of stored data is improved.

Description

A kind of solid-state disk adaptive error correction method and system

Technical field

The invention belongs to solid-state disk error correcting technique field, particularly, relate to a kind of solid-state disk adaptive error correction method and system.

Background technology

Along with popularizing of electronic equipment various in daily life, solid-state disk is widely used as a kind of memory device, ensures that the safety of data in solid-state disk seems and becomes more and more important.It is extremely important how error correcting code as the important measures that guarantee data security plays maximal efficiency.

The flash chip manufacturing process of solid-state disk inside has developed into the level of 10 nanometers, and mean that the unit size of flash chip inside is more and more less, noise also increases accordingly, needs more powerful error correcting code.Flash chip has multiple layer of structure to form, and minimum read-write unit is page (Page), and multiple pages form a block (Block).Flash chip first will carry out erase operation before write data, and erase unit is block.Block after erasing becomes white space, can write relevant data message.Error correcting code decode procedure is had to pass through, to ensure that the data read are reliable data when flash memory reads data.If mistake appears in data, then carry out error correction correction by error correcting code.In addition, the noise be subject at different times flash chip is also different, and thus corrupt data rate is also different.Under universal law, early stage flash chip error rate is very low, and to the increase of later stage along with erasable number of times, the growth of data retention over time, corrupt data rate also increases accordingly.

Low density parity check code (Low-Density Parity-Check code, LDPC) has powerful error correcting capability.LDPC is formed primarily of scrambler and code translator.Scrambler is responsible for that the data of write flash memory are carried out coding and is generated LDPC code word.LDPC code word is made up of raw data and LDPC check information.Code translator is then responsible for carrying out decoding error correction to LDPC code word.Code translator mainly contains two kinds of results and exports: one is successfully decoded, illustrates that the data exported do not have mistake; Two is decoding failures, and illustrate that ldpc decoder can not correct the mistake in LDPC code word, the data of output contain error message.Different LDPC code rates has different error-correcting performances, and the higher error correcting capability of code check is more weak.High code rate LDPC code is as weak LDPC code, and its error correcting capability is not as low code rate LDPC code.Under normal circumstances, solid-state disk uses the LDPC code of the strongest error correcting capability, to ensure solid-state disk data security in the worst cases, so just there is the strongest LDPC error correcting code error correcting capability redundancy phenomena, also can affect the readwrite performance of solid-state disk, cause the waste of solid-state disk error correction energy consumption.

Summary of the invention

The object of the invention is according to solid-state disk internal flash chip data error situation different, the LDPC code of suitable error correcting capability is adopted to carry out error correction, reach the object improving LDPC code error correction usefulness, reduce the redundancy of single LDPC code error-correcting performance, improve reading performance and reducing its decoding energy consumption of solid-state disk simultaneously.

To achieve these goals, the present invention constructs a kind of method of automatically switch weak LDPC code and strong LDPC code, decrease and only use strong LDPC code and the redundancy of the LDPC error-correcting performance produced, decrease the error correction energy consumption that solid-state disk uses LDPC code simultaneously, and improve the accuracy that solid-state disk use Different L DPC code carries out error correction, ensure that the reliability of solid-state disk internal data.The present invention is using high code rate LDPC code as weak LDPC code, and low code rate LDPC code is as strong LDPC code.

According to one aspect of the present invention, provide a kind of solid-state disk adaptive error correction method, comprise the steps:

(1) initialization: solid-state disk, before input data, carries out block erase operation, to write data, and the error correcting code identifier B of all erase blocks of initialization _i=0, wherein i=0,1 ..., n, n represent the quantity of solid-state disk erase block;

(2) solid-state disk adaptive error correction coding, comprising:

(2.1) when one page raw data R is written into solid-state disk flash chip, according to the generator matrix G of weak LDPC code ₁coding is carried out to raw data R and obtains code word C ₁=R × G ₁, code word C ₁remove raw data R and obtain weak LDPC code check information P ₁;

(2.2) by the generator matrix G of strong LDPC code ₂to one page raw data R coding generated codeword

C ₂=R × G ₂, code word C ₂remove raw data R and obtain strong LDPC code check information P ₂;

(2.3) one page raw data R and P ₁, P ₂code word C=(R, the P of composition one page ₁, P ₂);

(2.4) the code word C generated is write in flash chip;

(3) solid-state disk decode procedure, comprising:

(3.1) judged whether read operation, if there is read operation, turned to (3.2), otherwise terminated;

(3.2) the error correcting code identifier B reading page place block i is judged _iwhether be 0;

(3.3) if B _ibe 0, then in block i, all pages adopt weak LDPC code to carry out error correction;

(3.4) solid-state disk self-adaptation error correcting code blocked operation, comprising:

(3.4.1) in if block i, one page uses weak LDPC code error correction failure, the error correcting code identifier B of assignment block i _i=1, and forward step (3.5) to;

(3.4.2) after if block i uses strong LDPC code to carry out error correction, if block i is wiped free of, the error correcting code identifier B of assignment block i _i=0, and forward step (3.2) to;

(3.5) if B _ibe 1, then in block i, all pages adopt strong LDPC code to carry out error correction.

According to another aspect of the present invention, additionally provide a kind of solid-state disk self-adaptation error correction system, described system comprises as lower module: solid-state disk initialization module, adaptive error correction coding module, solid-state disk decoding module, wherein:

Described solid-state disk initialization module, for before input data, carries out block erase operation to solid-state disk, to write data, and the error correcting code identifier B of all erase blocks of initialization _i=0, wherein i=0,1 ..., n, n represent the quantity of solid-state disk erase block;

Described solid-state disk adaptive error correction coding module, for carrying out adaptive error correction coding to raw data, particularly: when one page raw data R is written into solid-state disk flash chip, according to the generator matrix G of weak LDPC code ₁coding is carried out to raw data R and obtains code word C ₁=R × G ₁, code word C ₁remove raw data R and obtain weak LDPC code check information P ₁; By the generator matrix G of strong LDPC code ₂to one page raw data R coding generated codeword C ₂=R × G ₂, code word C ₂remove raw data R and obtain strong LDPC code check information P ₂; One page raw data R and P ₁, P ₂code word C=(R, the P of composition one page ₁, P ₂); The code word C generated is write in flash chip;

Described solid-state disk decoding module, comprises and reads judge module, error correcting code identification module, weak LDPC code correction module, self-adaptation error correcting code handover module and strong LDPC code correction module, wherein:

Describedly reading judge module, for having judged whether read operation, if there is read operation, turning to (3.2), otherwise terminate;

Described error correcting code identification module, for judging the error correcting code identifier B reading page place block i _iwhether be 0;

Described weak LDPC code correction module, if for B _ibe 0, then adopt weak LDPC code to carry out error correction to pages all in block i;

Described self-adaptation error correcting code handover module, for performing solid-state disk self-adaptation error correcting code blocked operation, is specially: in if block i, one page uses weak LDPC code error correction failure, the error correcting code identifier B of assignment block i _i=1, and forward described strong LDPC code correction module to; After if block i uses strong LDPC code to carry out error correction, if block i is wiped free of, the error correcting code identifier B of assignment block i _i=0, and forward described error correcting code identification module to;

Described strong LDPC code correction module, if for B _ibe 1, then adopt strong LDPC code to carry out error correction to pages all in block i.

In sum, the beneficial effect of technical solution of the present invention is:

Propose a kind of solid-state disk self-adaptation LDPC error correction optimization method, the method can automatically switch according to not coexisting between strong and weak two kinds of LDPC error correcting codes of solid-state disk error rate.Only use compared with single LDPC error correction code approach with traditional, effectively can play the error-correcting performance of different LDPC error correcting codes, reduce the error-correcting performance redundancy that single LDPC error correcting code causes, by the method, error correction is carried out to solid-state disk and effectively can improve and read performance.Because when using high code check LDPC error correcting code, the code word size of generation obviously diminishes, the threshold voltage detecting period caused, the codeword transmission time, decoding time has corresponding minimizing.Simultaneously relative to single LDPC error correcting code, the decoding energy consumption of self-adaptation LDPC error correction method also can significantly reduce.

Accompanying drawing explanation

Fig. 1 is the treatment scheme schematic diagram of self-adaptation error correction algorithm of the present invention;

Fig. 2 is weak LDPC code and strong LDPC code cataloged procedure schematic diagram;

Fig. 3 is weak LDPC code and strong LDPC code decode procedure schematic diagram;

Fig. 4 is solid-state disk block error correcting code adaptive handoff algorithms schematic diagram;

Fig. 5 is self-adaptation error correction system structural representation of the present invention.

Embodiment

In order to make object of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.In addition, if below in described each embodiment of the present invention involved technical characteristic do not form conflict each other and just can mutually combine.

In the present invention, the LDPC code of high code check represents weak LDPC code, and the LDPC code of low bit-rate represents strong LDPC code.

As shown in Figure 1, be the treatment scheme schematic diagram of self-adaptation error correction algorithm of the present invention, described error correction algorithm comprises the steps:

(1) initialization is specially:

Solid-state disk, before input data, carry out block erase operation, to write data.The error correcting code identifier B of all erase blocks of initialization _i=0 (i=0,1 ..., n), n represents the quantity of solid-state disk block;

(2) the specific coding process of solid-state disk adaptive error correction method is:

(2.1) as shown in Figure 2, when one page raw data R is written into solid-state disk flash chip, according to the generator matrix G of weak LDPC code ₁coding is carried out to raw data R and obtains code word C ₁=R × G ₁, code word C ₁remove raw data R and obtain weak LDPC code check information P ₁;

(2.2) by the generator matrix G of strong LDPC code ₂to one page raw data R coding generated codeword

C ₂=R × G ₂, code word C ₂remove raw data R and obtain strong LDPC code check information P ₂;

(2.3) one page raw data R and P ₁, P ₂code word C=(R, the P of composition one page ₁, P ₂);

(2.4) the code word C generated is write in flash chip;

(3) solid-state disk decode procedure comprises the steps:

(3.1) judged whether read operation, if there is read operation, turned to (3.2), otherwise terminate this algorithm;

(3.2) the error correcting code identifier B reading page place block i is judged _iwhether be 0;

(3.3) if B _ibe 0, then in block i, all pages adopt weak LDPC code to carry out error correction, and weak LDPC code error correction is specific as follows:

(3.3.1) as shown in Figure 3, obtain by one page raw data R and weak LDPC code checking data P ₁the code word C of composition ₁;

(3.3.2) to code word C ₁in each binary digit b _icalculate log-likelihood ratio LLR _ivalue

${\mathrm{LLR}}_i=\ln \frac{{\∫}_{A_i}{P}^{\left(i\right)}(b_i=1|V_i)}{{\∫}_{A_i}{P}^{\left(i\right)}(b_i=0|V_i)}---\left(1\right)$

Wherein V _irepresent sense voltage value, A _irepresent the regional extent value at sense voltage place, P ⁽ⁱ⁾x () represents i-th threshold voltage perception Gaussian function;

(3.3.3) the LLR information obtained is input to weak LDPC check matrix H ₁in variable node in, as LDPC decoding initial information;

(3.3.4) check matrix H ₁in each variable node and check-node carry out iterative processing decoding information each other, iterative information only at variable node and check-node in check matrix H ₁in the inter-node transmission of annexation each other;

If (3.3.5) decode the weak LDPC decoding vector C ' obtained ₁with the code word C of input ₁equal, export successfully decoded and successfully export data.If reach maximum iterations but decoding vector C ' ₁with enter code word C ₁etc., then do not export decoding failure and terminate weak LDPC decode procedure;

If (3.3.6) weak LDPC code error correction failure, then forward step (3.4) to and perform solid-state disk self-adaptation error correcting code blocked operation;

(3.4) solid-state disk self-adaptation error correcting code blocked operation, specific as follows:

(3.4.1) as shown in Figure 4, in if block i, one page uses weak LDPC code error correction failure, the error correcting code identifier B of assignment block i _i=1, and forward step (3.5) to;

(3.4.2) after if block i uses strong LDPC code to carry out error correction, if block i is wiped free of, the error correcting code identifier B of assignment block i _i=0, and forward step (3.2) to;

(3.5) if B _ibe 1, then in block i, all pages adopt strong LDPC code to carry out error correction, and strong LDPC code error correction is specific as follows:

(3.5.1) obtain by raw data R and strong LDPC code checking data P ₂the code word C of composition ₂;

(3.5.2) to code word C ₂in each binary digit b _jcalculate log-likelihood ratio LLR _jvalue

${\mathrm{LLR}}_j=\ln \frac{{\∫}_{A_j}{P}^{\left(j\right)}(b_j=1|V_j)}{{\∫}_{A_j}{P}^{\left(j\right)}(b_j=0|V_j)}---\left(2\right)$

Wherein V _jrepresent sense voltage value, A _jrepresent the regional extent value at sense voltage place, P ^(j)x () represents a jth threshold voltage perception Gaussian function;

(3.5.3) the LLR information obtained is input to strong LDPC check matrix H ₂in variable node in, as LDPC decoding initial information;

(3.5.4) check matrix H ₂in each variable node and check-node carry out iterative processing decoding information each other, iterative information only at variable node and check-node in check matrix H ₂in the inter-node transmission of annexation each other;

If (3.5.5) decode the strong LDPC decoding vector C ' obtained ₂with the code word C of input ₂equal, export successfully decoded and successfully export data.If reach maximum iterations but decoding vector C ' ₂with enter code word C ₂etc., then do not export decoding failure and terminate strong LDPC decode procedure.

Further, as shown in Figure 5, present invention also offers a kind of solid-state disk self-adaptation error correction system, described system comprises as lower module: solid-state disk initialization module, adaptive error correction coding module, solid-state disk decoding module, wherein:

Described solid-state disk initialization module, for before input data, carries out block erase operation to solid-state disk, to write data, and the error correcting code identifier B of all erase blocks of initialization _i=0, wherein i=0,1 ..., n, n represent the quantity of solid-state disk erase block;

Described solid-state disk adaptive error correction coding module, for carrying out adaptive error correction coding to raw data, particularly: when one page raw data R is written into solid-state disk flash chip, according to the generator matrix G of weak LDPC code ₁coding is carried out to raw data R and obtains code word C ₁=R × G ₁, code word C ₁remove raw data R and obtain weak LDPC code check information P ₁; By the generator matrix G of strong LDPC code ₂to one page raw data R coding generated codeword C ₂=R × G ₂, code word C ₂remove raw data R and obtain strong LDPC code check information P ₂; One page raw data R and P ₁, P ₂code word C=(R, the P of composition one page ₁, P ₂); The code word C generated is write in flash chip;

Described solid-state disk decoding module, comprises and reads judge module, error correcting code identification module, weak LDPC code correction module, self-adaptation error correcting code handover module and strong LDPC code correction module, wherein:

Describedly reading judge module, for having judged whether read operation, if there is read operation, turning to (3.2), otherwise terminate;

Described error correcting code identification module, for judging the error correcting code identifier B reading page place block i _iwhether be 0;

Described weak LDPC code correction module, if for B _ibe 0, then adopt weak LDPC code to carry out error correction to pages all in block i;

Described self-adaptation error correcting code handover module, for performing solid-state disk self-adaptation error correcting code blocked operation, is specially: in if block i, one page uses weak LDPC code error correction failure, the error correcting code identifier B of assignment block i _i=1, and forward described strong LDPC code correction module to; After if block i uses strong LDPC code to carry out error correction, if block i is wiped free of, the error correcting code identifier B of assignment block i _i=0, and forward described error correcting code identification module to;

Described strong LDPC code correction module, if for B _ibe 1, then adopt strong LDPC code to carry out error correction to pages all in block i.

Further, described weak LDPC code correction module specifically comprises weak LDPC code word and obtains submodule, weak LDPC code likelihood ratio calculating sub module, the generation of weak LDPC code initial information submodule, weak LDPC code iterative processing submodule, weak LDPC code successfully decoded judgement submodule and weak LDPC code error correction switching submodule, wherein:

Described weak LDPC code word obtains submodule, for obtaining by one page raw data R and weak LDPC code checking data P ₁the code word C of composition ₁;

Described weak LDPC code likelihood ratio calculating sub module, for code word C ₁in each binary digit b _icalculate log-likelihood ratio LLR _ivalue

${\mathrm{LLR}}_i=\ln \frac{{\∫}_{A_i}{P}^{\left(i\right)}(b_i=1|V_i)}{{\∫}_{A_i}{P}^{\left(i\right)}(b_i=0|V_i)}$

Wherein: V _irepresent sense voltage value, A _irepresent the regional extent value at sense voltage place, P ⁽ⁱ⁾x () represents i-th threshold voltage perception Gaussian function;

Described weak LDPC code initial information generates submodule, for the LLR obtained information is input to weak LDPC check matrix H ₁in variable node in, as LDPC decoding initial information;

Described weak LDPC code iterative processing submodule, for performing check matrix H ₁in each variable node and check-node carry out iterative processing decoding information each other, iterative information only at variable node and check-node in check matrix H ₁in the inter-node transmission of annexation each other;

The successfully decoded judgement submodule of described weak LDPC code, for judging if decode the weak LDPC decoding vector C ' obtained ₁with the code word C of input ₁equal, export successfully decoded and export data.If reach maximum iterations but decoding vector C ' ₁with enter code word C ₁etc., then do not export decoding failure and terminate weak LDPC decode procedure;

Described weak LDPC code error correction switching submodule, if for weak LDPC code error correction failure, then forward described self-adaptation error correcting code handover module to and perform solid-state disk self-adaptation error correcting code blocked operation.

Further, described strong LDPC code correction module specifically comprises strong LDPC code word and obtains submodule, strong LDPC code likelihood ratio calculating sub module, strong LDPC code initial information generation submodule, strong LDPC code iterative processing submodule, the strong successfully decoded judgement submodule of LDPC code, wherein:

Described strong LDPC code word obtains submodule, for obtaining by raw data R and strong LDPC code checking data P ₂the code word C of composition ₂;

Described strong LDPC code likelihood ratio calculating sub module, for code word C ₂in each binary digit b _jcalculate log-likelihood ratio LLR _jvalue

${\mathrm{LLR}}_j=\ln \frac{{\∫}_{A_j}{P}^{\left(j\right)}(b_j=1|V_j)}{{\∫}_{A_j}{P}^{\left(j\right)}(b_j=0|V_j)}$

Wherein V _jrepresent sense voltage value, A _jrepresent the regional extent value at sense voltage place, P ^(j)x () represents a jth threshold voltage perception Gaussian function;

Described strong LDPC code initial information generates submodule, for the LLR obtained information is input to strong LDPC check matrix H ₂in variable node in, as LDPC decoding initial information;

Described strong LDPC code iterative processing submodule, for performing check matrix H ₂in each variable node and check-node carry out iterative processing decoding information each other.Iterative information only at variable node and check-node in check matrix H ₂in the inter-node transmission of annexation each other;

The successfully decoded judgement submodule of described strong LDPC code, if the strong LDPC decoding vector C ' obtained for decoding ₂with the code word C of input ₂equal, export successfully decoded and export data.If reach maximum iterations but decoding vector C ' ₂with enter code word C ₂etc., then do not export decoding failure and terminate strong LDPC decode procedure.

Those skilled in the art will readily understand; the foregoing is only preferred embodiment of the present invention; not in order to limit the present invention, all any amendments done within the spirit and principles in the present invention, equivalent replacement and improvement etc., all should be included within protection scope of the present invention.

Claims (6)

1. a solid-state disk adaptive error correction method, is characterized in that, described method comprises the steps:

(1) initialization: solid-state disk, before input data, carries out block erase operation, to write data, and the error correcting code identifier B of all erase blocks of initialization _i=0, wherein i=0,1 ..., n, n represent the quantity of solid-state disk erase block;

(2) solid-state disk adaptive error correction coding, comprising:

(2.1) when one page raw data R is written into solid-state disk flash chip, according to the generator matrix G of weak LDPC code ₁coding is carried out to raw data R and obtains code word C ₁=R × G ₁, code word C ₁remove raw data R and obtain weak LDPC code check information P ₁;

(2.2) by the generator matrix G of strong LDPC code ₂to one page raw data R coding generated codeword C ₂=R × G ₂, code word C ₂remove raw data R and obtain strong LDPC code check information P ₂;

(2.3) one page raw data R and P ₁, P ₂code word C=(R, the P of composition one page ₁, P ₂);

(2.4) the code word C generated is write in flash chip;

(3) solid-state disk decode procedure, comprising:

(3.1) judged whether read operation, if there is read operation, turned to (3.2), otherwise terminated;

(3.2) the error correcting code identifier B reading page place block i is judged _iwhether be 0;

(3.3) if B _ibe 0, then in block i, all pages adopt weak LDPC code to carry out error correction;

(3.4) solid-state disk self-adaptation error correcting code blocked operation, comprising:

(3.4.1) in if block i, one page uses weak LDPC code error correction failure, the error correcting code identifier B of assignment block i _i=1, and forward step (3.5) to;

(3.4.2) after if block i uses strong LDPC code to carry out error correction, if block i is wiped free of, the error correcting code identifier B of assignment block i _i=0, and forward step (3.2) to;

(3.5) if B _ibe 1, then in block i, all pages adopt strong LDPC code to carry out error correction.

2. the method for claim 1, is characterized in that, described step (3.3) specifically comprises:

(3.3.1) obtain by one page raw data R and weak LDPC code checking data P ₁the code word C of composition ₁;

(3.3.2) to code word C ₁in each binary digit b _icalculate log-likelihood ratio LLR _ivalue

${\mathrm{LLR}}_i=\ln \frac{{\∫}_{A_i}{P}^{\left(i\right)}(b_i=1|V_i)}{{\∫}_{A_i}{P}^{\left(i\right)}(b_i=0|V_i)}$

Wherein V _irepresent sense voltage value, A _irepresent the regional extent value at sense voltage place, P ⁽ⁱ⁾x () represents i-th threshold voltage perception Gaussian function;

(3.3.3) the LLR information obtained is input to weak LDPC check matrix H ₁in variable node in, as LDPC decoding initial information;

(3.3.4) check matrix H ₁in each variable node and check-node carry out iterative processing decoding information each other, iterative information only at variable node and check-node in check matrix H ₁in the inter-node transmission of annexation each other;

If (3.3.5) decode the weak LDPC decoding vector C ' obtained ₁with the code word C of input ₁equal, export successfully decoded and successfully export data, if reach maximum iterations but decoding vector C ' ₁with enter code word C ₁etc., then do not export decoding failure and terminate weak LDPC decode procedure;

If (3.3.6) weak LDPC code error correction failure, then forward step (3.4) to and perform solid-state disk self-adaptation error correcting code blocked operation.

3. method as claimed in claim 1 or 2, it is characterized in that, described step (3.5) specifically comprises:

(3.5.1) obtain by raw data R and strong LDPC code checking data P ₂the code word C of composition ₂;

(3.5.2) to code word C ₂in each binary digit b _jcalculate log-likelihood ratio LLR _jvalue

${\mathrm{LLR}}_j=\ln \frac{{\∫}_{A_j}{P}^{\left(j\right)}(b_j=1|V_j)}{{\∫}_{A_j}{P}^{\left(j\right)}(b_j=0|V_j)}$

Wherein V _jrepresent sense voltage value, A _jrepresent the regional extent value at sense voltage place, P ^(j)x () represents a jth threshold voltage perception Gaussian function;

(3.5.3) the LLR information obtained is input to strong LDPC check matrix H ₂in variable node in, as LDPC decoding initial information;

(3.5.4) check matrix H ₂in each variable node and check-node carry out iterative processing decoding information each other, iterative information only at variable node and check-node in check matrix H ₂in the inter-node transmission of annexation each other;

If (3.5.5) decode the strong LDPC decoding vector C ' obtained ₂with the code word C of input ₂equal, export successfully decoded and successfully export data, if reach maximum iterations but decoding vector C ' ₂with enter code word C ₂etc., then do not export decoding failure and terminate strong LDPC decode procedure.

4. a solid-state disk self-adaptation error correction system, is characterized in that, described system comprises as lower module: solid-state disk initialization module, adaptive error correction coding module, solid-state disk decoding module, wherein:

Described solid-state disk initialization module, for before input data, carries out block erase operation to solid-state disk, to write data, and the error correcting code identifier B of all erase blocks of initialization _i=0, wherein i=0,1 ..., n, n represent the quantity of solid-state disk erase block;

Described solid-state disk adaptive error correction coding module, for carrying out adaptive error correction coding to raw data, particularly: when one page raw data R is written into solid-state disk flash chip, according to the generator matrix G of weak LDPC code ₁coding is carried out to raw data R and obtains code word C ₁=R × G ₁, code word C ₁remove raw data R and obtain weak LDPC code check information P ₁; By the generator matrix G of strong LDPC code ₂to one page raw data R coding generated codeword C ₂=R × G ₂, code word C ₂remove raw data R and obtain strong LDPC code check information P ₂; One page raw data R and P ₁, P ₂code word C=(R, the P of composition one page ₁, P ₂); The code word C generated is write in flash chip;

Described solid-state disk decoding module, comprises and reads judge module, error correcting code identification module, weak LDPC code correction module, self-adaptation error correcting code handover module and strong LDPC code correction module, wherein:

Describedly reading judge module, for having judged whether read operation, if there is read operation, turning to (3.2), otherwise terminate;

Described error correcting code identification module, for judging the error correcting code identifier B reading page place block i _iwhether be 0;

Described weak LDPC code correction module, if for B _ibe 0, then adopt weak LDPC code to carry out error correction to pages all in block i;

Described self-adaptation error correcting code handover module, for performing solid-state disk self-adaptation error correcting code blocked operation, is specially: in if block i, one page uses weak LDPC code error correction failure, the error correcting code identifier B of assignment block i _i=1, and forward described strong LDPC code correction module to; After if block i uses strong LDPC code to carry out error correction, if block i is wiped free of, the error correcting code identifier B of assignment block i _i=0, and forward described error correcting code identification module to;

Described strong LDPC code correction module, if for B _ibe 1, then adopt strong LDPC code to carry out error correction to pages all in block i.

5. system as claimed in claim 4, it is characterized in that, described weak LDPC code correction module specifically comprises weak LDPC code word and obtains submodule, weak LDPC code likelihood ratio calculating sub module, the generation of weak LDPC code initial information submodule, weak LDPC code iterative processing submodule, weak LDPC code successfully decoded judgement submodule and weak LDPC code error correction switching submodule, wherein:

Described weak LDPC code word obtains submodule, for obtaining by one page raw data R and weak LDPC code checking data P ₁the code word C of composition ₁;

Described weak LDPC code likelihood ratio calculating sub module, for code word C ₁in each binary digit b _icalculate log-likelihood ratio LLR _ivalue wherein: V _irepresent sense voltage value, A _irepresent the regional extent value at sense voltage place, P ⁽ⁱ⁾x () represents i-th threshold voltage perception Gaussian function;

Described weak LDPC code initial information generates submodule, for the LLR obtained information is input to weak LDPC check matrix H ₁in variable node in, as LDPC decoding initial information;

Described weak LDPC code iterative processing submodule, for performing check matrix H ₁in each variable node and check-node carry out iterative processing decoding information each other, iterative information only at variable node and check-node in check matrix H ₁in the inter-node transmission of annexation each other;

The successfully decoded judgement submodule of described weak LDPC code, for judging if decode the LDPC decoding vector C ' obtained ₁with the code word C of input ₁equal, export successfully decoded and successfully export data; If reach maximum iterations but decoding vector C ' ₁with enter code word C ₁etc., then do not export decoding failure and terminate weak LDPC decode procedure;

Described weak LDPC code error correction switching submodule, if for weak LDPC code error correction failure, then forward described self-adaptation error correcting code handover module to and perform solid-state disk self-adaptation error correcting code blocked operation.

6. the system as described in claim 4 or 5, it is characterized in that, described strong LDPC code correction module specifically comprises strong LDPC code word and obtains submodule, strong LDPC code likelihood ratio calculating sub module, strong LDPC code initial information generation submodule, strong LDPC code iterative processing submodule, the strong successfully decoded judgement submodule of LDPC code, wherein:

Described strong LDPC code word obtains submodule, for obtaining by raw data R and strong LDPC code checking data P ₂the code word C of composition ₂;

Described strong LDPC code likelihood ratio calculating sub module, for code word C ₂in each binary digit b _jcalculate log-likelihood ratio LLR _jvalue wherein V _jrepresent sense voltage value, A _jrepresent the regional extent value at sense voltage place, P ^(j)x () represents a jth threshold voltage perception Gaussian function;

Described strong LDPC code initial information generates submodule, for the LLR obtained information is input to strong LDPC check matrix H ₂in variable node in, as LDPC decoding initial information;

Described strong LDPC code iterative processing submodule, for performing check matrix H ₂in each variable node and check-node carry out iterative processing decoding information each other, iterative information only at variable node and check-node in check matrix H ₂in the inter-node transmission of annexation each other;

The successfully decoded judgement submodule of described strong LDPC code, if the strong LDPC decoding vector C ' obtained for decoding ₂with the code word C of input ₂equal, export successfully decoded and successfully export data; If reach maximum iterations but decoding vector C ' ₂with enter code word C ₂etc., then do not export decoding failure and terminate strong LDPC decode procedure.