CN107423161A - Applied to the adaptive LDPC code error-correcting code system and method in flash memory - Google Patents
Applied to the adaptive LDPC code error-correcting code system and method in flash memory Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
- G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C2029/0411—Online error correction
Abstract
The present invention discloses a kind of adaptive LDPC code error-correcting code system being applied in flash memory and method, can improve the error correcting capability of the error correcting code of flash memories, the stability of protection data storage and improve flash memories service life.LDPC code is changed into adaptive coding and decoding by this method, improves the adaptability of flash memory storage controller, also greatly strengthen the error correcting capability of flash memory storage controller, while improves flash memories service life.
Description
Technical field
The present invention relates to a kind of adaptive LDPC code error-correcting code system being applied in flash memory and method, belong to sudden strain of a muscle
Storage control field.
Background technology
In the various applications for needing progress signal transmission, error correcting code can be often used, error correcting code can make signal transmission errors
When receiving terminal be able to right the wrong and obtain correct signal.Error correcting code can apply in many systems, in a communications system,
Signal may be disturbed when transmitting by channel effect and noise, so as to cause the data stored in flash memory device
Through incorrect.The data stored in flash memory device are the data after error correcting code device code, for flash memory storage
For control device, error correcting code is required One function unit.Increasingly advanced, the memory cell with the technique of memory
Volume is less and less, and the data that memory cell is stored also gradually are increasing, and cause flash memories in reading process
Caused error probability constantly raises, thus decodes mechanism using suitable, stronger error correction code in flash controller, especially
It is necessary.
In addition, the fine or not key for weighing a flash memory storage controller is its adaptability, it can support multiple manufacturers
With the flash memories of different process.Especially when the technique of flash memories is more advanced, volume is smaller, and flash memory cell
The data of storage also increase, and cause flash memories also constantly to increase in error probability caused by reading.However, flash memory is deposited
The error correcting code decoding capability of storage controller is that an important factor for whether flash memory storage controller is qualified determined.Therefore, flash memory storage
It is inexorable trend demand that controller, which has an adaptable error correcting code,.
LDPC（Low Density Parity Check, low-density checksum）Code be Robert Gallager in
A kind of packeting error-correcting code with sparse check matrix proposed in thesis for the doctorate for 1962.It is suitable for almost all letters
Road, its performance approach shannon limit, and describe and realize simply, decode simple and practicable parallel work-flow, are adapted to hardware to realize.
LDPC code has huge application potential, deep space communication, fiber optic communication, satellite communication, satellite digital video, digital watermarking,
It is used widely in magnetic optical/Hologram Storage, movement and fixed radio communication, cable modulating/demodulating and digital subscriber.According to
The technique of flash memory device is increasingly advanced, and the error correcting capability of the error correcting code in flash memories control device is also required to increase
By force.In current flash memories control device, main error correcting code is BCH code, with increasing for error probability, BCH code
Space requirement and operational capability are also gradually increased；With the raising of flash memory storage technique, the error correcting capability of BCH code is gradual
Be not suitable for the development and its application of flash technology, so needing that error correcting capability is stronger, more flexible and adaptable error correcting code.Institute
To select LDPC code to replace BCH code be that comparison is appropriate.
The content of the invention
The technical problem to be solved in the present invention is to provide a kind of adaptive LDPC code error correction being applied in flash memory
Code system and method, the error correcting capability of the error correcting code of flash memories is improved, protect the stability of data storage.
In order to solve the technical problem, the technical solution adopted by the present invention is：It is a kind of to be applied in flash memory
Adaptive LDPC code error-correcting code system, including main frame, flash memory storage controller and flash memories, set in flash memory storage controller
There is adaptive LDPC code decoder, adaptive LDPC code decoder includes Multi-Stage Encoder, self-adaptive regulator, hard-decision decoding
Device, soft decision decoder, error detector, decision device I, decision device II, data processor and pulse restorer, Multi-Stage Encoder
It is connected between main frame and flash memories, while the input of Multi-Stage Encoder is connected with self-adaptive regulator, for basis
Self-adaptive regulator is encoded accordingly；Hard decision decoders, soft decision decoder input with self-adaptive regulator,
Decision device I is connected, and the input of soft decision decoder is connected with data processor, decision device I, data processor it is another
End connection flash memories, hard decision decoders judge whether to hard-decision decoding according to decision device I, and are adjusted according to adaptive
Device is saved to judge the check matrix decoded, soft decision decoder judges whether to soft-decision decoding according to decision device I, leads to
The check bit information for crossing acquisition data processor output is calculated so as to be decoded, and judges to carry out according to self-adaptive regulator
The check matrix of decoding；Hard decision decoders and the output end of soft decision decoder are connected to decision device II, decision device II's
Output is respectively connecting to self-adaptive regulator, main frame and error detector, and error detector is connected to sudden strain of a muscle by pulse restorer
Deposit memory, determining device II is used to judging whether successful and error in data the digit of LDPC code wrong, error detector according to
Decision device II fails to judge to decode, and recovers the error in data in flash memories using pulse restorer.
The adaptive LDPC code error-correcting code system of the present invention being applied in flash memory, soft decision decoder include
One-level decoder, two level decoder and three-level decoder.
The adaptive LDPC code error-correcting code system of the present invention being applied in flash memory, hard decision decoders, one
Level decoder, two level decoder, the error correcting capability of three-level decoder strengthen successively.
The adaptive LDPC code error-correcting code system of the present invention being applied in flash memory, flash memories are in standard
On the basis of data bit and check bit, a part of data bit is used as check bit.
The adaptive LDPC code error-correcting code system of the present invention being applied in flash memory, Multi-Stage Encoder pass through
It is Gallager building method, the building method of generalized L DPC codes, Mackay building method, combinatorics structured approach, limited several
What building method is realized；Hard decision decoders and soft decision decoder are using bit reversal method and product decoding algorithm, minimum and product
Decoding algorithm, maximum likelihood decoding algorithm, the decoding architecture realized with hardware circuit, processor realization of being arranged in pairs or groups with software or hardware
The mode of decoding is realized.
The invention also discloses a kind of adaptive LDPC error correction code approach being applied in flash memory, methods described bag
Adaptive coding flow and adaptive decoding flow are included, the process of adaptive coding flow is：a01）, according to error detector come
Choose corresponding encoder；a02）, to codeword information carry out corresponding encoded；a03）, the data and check code that have encoded are stored
To depositing soon in memory；The process of adaptive decoding flow is：b01）, codeword information is read from flash memories；b02）, enter
Row decoding judges, if meeting hard-decision decoding performs step 3, if meeting soft-decision decoding performs step 7；b03）, read
The hard information of code word；b04）, utilize corresponding LDPC code hard-decision decoding；b05）, carry out decoding judgement, if success if terminate
Decoding, if unsuccessful enter judgement in next step；b06）, if do not continue decoding if terminate to decode, if continue decoding if hold
Row step 7；b07）, read the Soft Inform ation of code word, and carry out corresponding data processing；b08）, utilize corresponding LDPC code soft-decision
Decoding；b09）, decoding judge, terminate to decode if successfully decoded, if it is unsuccessful enter in next step adjudicate；b10）If,
Do not continue decoding then to terminate to decode, if continuing to decode, start error detector and judge decoding error；b11）, according to mistake
Detector carries out pulse-recovery to flash memory internal data；b12）, repeat step 7 and 8；b13）, iteration reaches certain time
When number still LDPC code decodes unsuccessful, directly terminate decoding process.
Beneficial effects of the present invention：The adaptive LDPC code error-correcting code system of the present invention being applied in flash memory
The error correcting capability of the error correcting code of flash memories, the stability for protecting data storage can be improved with method and improve flash memory storage
Device service life.LDPC code is changed into adaptive coding and decoding by this method, improves the adaptability of flash memory storage controller,
The error correcting capability of flash memory storage controller is greatly strengthen, while improves flash memories service life.
Brief description of the drawings
Fig. 1 is the functional block diagram of flash-memory storage system；
Fig. 2 is the structural representation of adaptive LDPC code decoder；
Fig. 3 is Multi-Stage Encoder and hard decision decoders, the entire block diagram of soft decision decoder；
Fig. 4 is the flash memory village summer time data storage comparison diagram after standard and adjustment.
Embodiment
The present invention is described further with specific embodiment below in conjunction with the accompanying drawings.
Embodiment 1
LDPC code is one kind of linear block codes, and it has all characteristics of linear block codes.LDPC code can be divided into rule
（regular-LDPC）With it is irregular（irregular-LDPC）Two major classes.Assuming that check matrix H0For m × n rank matrixes, rule
LDPC code can be denoted as (n, j, k), and wherein n is code length, and j is the weight of check matrix each column（1 number in arranging, is referred to as arranged
Weight (column weight), k are the weight that check matrix is often gone（1 number at once, referred to as row weight (row weight)）,
And typically there is j>2, k>j.And 1 number of the check matrix each row and column of irregular LDPC codes is incomplete same.LDPC
The iterative decoding method of code is broadly divided into two kinds：One kind is hard-decision method, and one kind is soft decision method.Hard-decision bits are turned over
What shifting method transmitted in an iterative process is binary system hard information, and soft decision method transmits in an iterative process is and probability
Related real number Soft Inform ation.Hard-decision method is simple to operate, is easy to hardware realization, but error-correcting performance is general；Soft decision method
Better performances, but implementation complexity is higher.The present embodiment proposes that a kind of adaptive LDPC code being applied in flash memory is entangled
Error code system.
As shown in figure 1, being the functional block diagram of flash-memory storage system, adaptive LDPC code solution is included in flash memory storage controller
Code device.Flash memory storage controller is mainly responsible for the read-write of data and storage and the other functions of data.Flash memory storage controller from
Main frame obtains data and carries out encoding operation by adaptive LDPC code decoder, then by caused data Cun Chudao flash memory storages
In device.If main frame goes for the data in flash memories, it is necessary to which flash memory storage controller is read from flash memories
Take out, carry out decoding computing by adaptive LDPC code decoder and produce data input to main frame.
As shown in Fig. 2 being the structural representation of adaptive LDPC code decoder, adaptive LDPC code decoder includes multistage
Encoder, self-adaptive regulator, hard decision decoders, soft decision decoder, error detector, decision device I, decision device II, number
According to processor and pulse restorer, Multi-Stage Encoder is connected between main frame and flash memories, while Multi-Stage Encoder is defeated
Enter end to be connected with self-adaptive regulator, for being encoded accordingly according to self-adaptive regulator；Hard decision decoders, soft-decision
The input of decoder is connected with self-adaptive regulator, decision device I, and the input of soft decision decoder and data processing
Device is connected, decision device I, the other end connection flash memories of data processor, and hard decision decoders are according to decision device I judgements
No carry out hard-decision decoding, and the check matrix decoded is judged according to self-adaptive regulator, soft decision decoder according to
Decision device I judges whether to soft-decision decoding, by obtain data processor export check bit information carry out calculate so as to
Decoded, the check matrix for judging to be decoded according to self-adaptive regulator；Hard decision decoders and soft decision decoder
Output end is connected to decision device II, and decision device II output is respectively connecting to self-adaptive regulator, main frame and error detector,
Error detector is connected to flash memories by pulse restorer, determining device II be used to judging LDPC code wrong it is whether successful with
And the digit of error in data, error detector judges decoding failure according to decision device II, and is recovered using pulse restorer
Error in data in flash memories.
The effect of each several part is：Multi-Stage Encoder is encoded accordingly according to self-adaptive regulator.Hard decision solution
Code device is to judge whether to hard-decision decoding according to decision device I, and judges to apply that school according to self-adaptive regulator
Matrix is tested to be decoded.Soft decision decoder is to judge whether to soft-decision decoding according to decision device I, by obtaining number
Corresponding computing is carried out so as to be decoded according to the corresponding information of check bit of processor output, and according to self-adaptive regulator
To judge to be decoded using that check matrix.Self-adaptive regulator carries out making corresponding tune according to decision device II
Section, so as to carry out the coding and decoding of higher level, makes data storage reliable.Data processor is for handling flash memories
Corresponding data after the data of middle storage are quantified is handled, and it improves data processing speed, so as to improve the decoding time,
Reduce decoding delay, improve LDPC code decoding performance.Error detector mainly judges decoding failure according to decision device II,
Recover the error in data in flash memories using pulse restorer.Pulse restorer is according to error detector electron injection
Corresponding grid increases and recovered error in data.Determining device I is mainly to judge to decode using what mode.Determining device II
For judging whether successful and its error in data the digit of LDPC code decoding.
As shown in figure 3, it is Multi-Stage Encoder and hard decision decoders, the structural representation of soft decision decoder.Soft-decision
Decoder includes one-level decoder, two level decoder and three-level decoder.Multistage LDPC code is primarily used to adaptive different
The error correction digit of LDPC code.Flash memories are with different technique, gradually increased erasable number, flash memories storage number
Can gradually it increase according to the probability of error；So multistage LDPC code is needed to adapt to the change of flash memories.LDPC code is more in Fig. 3
Level encoder mainly according to the probability of corrupt data in flash memories carries out corresponding coded treatment, it and LDPC code
Each rank decoder is mutually corresponding.LDPC code hard decision decoders speed is fast in Fig. 3, limited error recovery capability, and it can only entangle
Just a certain amount of wrong digit, it carries out corresponding hard-decision decoding according to the coding of different stage.In Fig. 3, LDPC code is soft to be sentenced
Certainly decoding is divided into three ranks, and the error correcting capability of each rank is different, and the error correcting capability of one-level decoder is more than hard decision solution
Code, two level decoder are better than one-level decoder, and three-level decoder is better than two level decoder.Multistage LDPC code design improves flash memory
The service life of memory, and enhance flash controller adaptability.
As shown in figure 4, the flash memories data storage comparison diagram for this patent.In Fig. 4, standard is deposited for flash memories
Store up the standard drawing of data, the certain proportion that its data bit and check bit are set according to the different technique of flash memories.Adjust
It is to increase corresponding check bit in order to increase error correcting capability according to multistage LDPC code and make flash memories reliability more after whole
The adjustment that height, service life are longer and carry out.A part of memory space is sacrificed for flash memories and increases reliability
It is worth with service life.
In the present embodiment, LDPC code Multi-Stage Encoder can use various algorithms and the code device of software and hardware architecture real
It is existing, for example, LDPC code encoder can use Gallager building method, the building method of generalized L DPC codes, Mackay
The modes such as building method, combinatorics structured approach, finite geometry building method are realized.
LDPC code decoder can use the decoding apparatus of various algorithms and software and hardware architecture to realize, for example, LDPC code solution
Code device can use bit reversal method and product decoding algorithm, minimum and product decoding algorithm, maximum likelihood decoding algorithm, with hardware
The decoding architecture of circuit realiration, realized in a manner of software or hardware collocation processor realize decoding etc..
Embodiment 2
A kind of adaptive LDPC code error correction code approach being applied in flash memories is proposed in the present embodiment.Adaptive LDPC code
Error correcting code carries out the digit of adaptivity regulation error correction according to the error probability and different process of flash memories data storage.
The adaptive LDPC code error correcting code of this method extended error correction digit can improve the reliability of data and flash memories automatically
Service life.The adaptivity of this method is mainly reflected in the Multi-Stage Encoder and multi-stage decoder of LDPC code, and its basis is detectd
Sniffing misses device to automatically adjust error correction digit, so as to adjust coded system and its decoding process.This programme is specifically divided into coding
Flow and decoding process, idiographic flow are as follows.
Adaptive LDPC code coding flow：
（1）Corresponding encoder is chosen according to error detector；
（2）Corresponding encoded is carried out to codeword information；
（3）The data and check code encoded are stored into flash memories.
Adaptively LDPC code decoding process is specially：
（1）Codeword information is read from flash memories；
（2）Decoding judgement is carried out, if meeting hard-decision decoding execution（3）If meet soft-decision decoding execution（7）；
（3）Read the hard information of code word；
（4）Utilize corresponding LDPC code hard-decision decoding；
（5）Decoding judgement is carried out, if successfully terminating to decode, if unsuccessful enter judgement in next step；
（6）If being not desired to continue decoding end decoding, if it is desired to continuing to decode, go to（7）；
（7）The Soft Inform ation of code word is read, and carries out corresponding data processing；
（8）Utilize corresponding LDPC code soft-decision decoding；
（9）Decoding judges, if successfully decoded terminates to decode, if unsuccessful enter judgement in next step；
（10）If not continuing decoding terminates decoding, if continuing to decode, start error detector；
（11）Pulse-recovery is carried out to flash memories internal data according to error detector；
（12）Repeat（7）、（8）Process；
（13）If reaching certain iterations, LDPC code decoding is unsuccessful, directly terminates decoding process.
Present invention is generally directed to the error correcting capability for the error correcting code for improving flash memories, protect data storage stability and
Improve flash memories service life.LDPC code is changed into adaptive coding and decoding improves the adaptation of flash memory storage controller
Property, the error correcting capability of flash memory storage controller is also greatly strengthen, while improve flash memories service life.
Described above is only that the general principle of the present invention and preferred embodiment, those skilled in the art do according to the present invention
The improvement and replacement gone out, belongs to protection scope of the present invention.
Claims (6)
1. a kind of adaptive LDPC code error-correcting code system being applied in flash memory, including main frame, flash memory storage controller
And flash memories, it is characterised in that：Adaptive LDPC code decoder, adaptive LDPC code solution are provided with flash memory storage controller
Code device include Multi-Stage Encoder, self-adaptive regulator, hard decision decoders, soft decision decoder, error detector, decision device I,
Decision device II, data processor and pulse restorer, Multi-Stage Encoder are connected between main frame and flash memories, while multistage
The input of encoder is connected with self-adaptive regulator, for being encoded accordingly according to self-adaptive regulator；Hard decision solution
Code device, the input of soft decision decoder are connected with self-adaptive regulator, decision device I, and the input of soft decision decoder
End be connected with data processor, decision device I, data processor the other end connect flash memories, hard decision decoders according to
Decision device I judges whether to hard-decision decoding, and judges the check matrix decoded according to self-adaptive regulator, soft to sentence
Certainly decoder judges whether to soft-decision decoding according to decision device I, the check bit information exported by obtaining data processor
Calculated so as to be decoded, the check matrix for judging to be decoded according to self-adaptive regulator；Hard decision decoders and soft
The output end of Decision Decoding device is connected to decision device II, and decision device II output is respectively connecting to self-adaptive regulator, main frame
And error detector, error detector are connected to flash memories by pulse restorer, determining device II is used to judge LDPC code
Whether successful and error in data the digit of wrong, error detector judges decoding failure according to decision device II, and utilizes arteries and veins
Restorer is rushed to recover the error in data in flash memories.
2. the adaptive LDPC code error-correcting code system according to claim 1 being applied in flash memory, its feature exist
In：Soft decision decoder includes one-level decoder, two level decoder and three-level decoder.
3. the adaptive LDPC code error-correcting code system according to claim 2 being applied in flash memory, its feature exist
In：Hard decision decoders, one-level decoder, two level decoder, the error correcting capability of three-level decoder strengthen successively.
4. the adaptive LDPC code error-correcting code system according to claim 1 being applied in flash memory, its feature exist
In：Flash memories are used as check bit on the basis of received data bit and check bit, by a part of data bit.
5. the adaptive LDPC error-correcting code systems according to claim 1 being applied in flash memory, its feature exist
In：Multi-Stage Encoder passes through Gallager building method, the building method of generalized L DPC codes, Mackay building method, group
Close and learn structured approach, finite geometry building method is realized；Hard decision decoders and soft decision decoder are using bit reversal method and product
Decoding algorithm, minimum and product decoding algorithm, maximum likelihood decoding algorithm, the decoding architecture realized with hardware circuit, with software or
Hardware collocation processor realizes that the mode of decoding is realized.
A kind of 6. adaptive LDPC code error correction code approach being applied in flash memory, it is characterised in that：Compiled including adaptive
Code stream journey and adaptive decoding flow, the process of adaptive coding flow are：a01）, chosen according to error detector it is corresponding
Encoder；a02）, to codeword information carry out corresponding encoded；a03）, encoded data and check code storage to soon storage
In device；The process of adaptive decoding flow is：b01）, codeword information is read from flash memories；b02）, carry out decoding and sentence
It is disconnected, if meeting hard-decision decoding performs step 3, if meeting soft-decision decoding performs step 7；b03）, read code word it is hard
Information；b04）, utilize corresponding LDPC code hard-decision decoding；b05）, carry out decoding judgement, if success if terminate to decode, such as
Fruit is unsuccessful to enter judgement in next step；b06）, if do not continue decoding if terminate to decode, if continue decoding if perform step 7；
b07）, read the Soft Inform ation of code word, and carry out corresponding data processing；b08）, utilize corresponding LDPC code soft-decision decoding；
b09）, decoding judge, terminate to decode if successfully decoded, if it is unsuccessful enter in next step adjudicate；b10）If, do not continue
Decoding then terminates to decode, if continuing to decode, starts error detector and judges decoding error；b11）, according to error detector
Pulse-recovery is carried out to flash memory internal data；b12）, repeat step 7 and 8；b13）, iteration reach certain number still
When LDPC code decoding is unsuccessful, directly terminate decoding process.
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| PCT/CN2017/119349 WO2019019550A1 (en) | 2017-07-24 | 2017-12-28 | Self-adaptive ldpc code error correction code system and method applied to flash memory |
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| CN109087683A (en) * | 2018-07-26 | 2018-12-25 | 西京学院 | A kind of NAND Flash solid-state storage adaptive error control method |
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| CN109739682A (en) * | 2018-12-21 | 2019-05-10 | 山东华芯半导体有限公司 | Applied to the adaptive polar code error-correcting code system and method in flash controller |
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| CN111294061A (en) * | 2020-02-11 | 2020-06-16 | 上海威固信息技术股份有限公司 | Decoding soft decision delay reduction method for original bit error rate perception |
| CN113517896A (en) * | 2021-07-08 | 2021-10-19 | 华中科技大学 | Encoding/decoding method, apparatus and system for phase modulation type holographic memory system |
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| WO2019019550A1 (en) * | 2017-07-24 | 2019-01-31 | 山东华芯半导体有限公司 | Self-adaptive ldpc code error correction code system and method applied to flash memory |
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| CN108880564B (en) * | 2018-06-26 | 2021-09-24 | 清华大学 | Low-density parity check code decoding method with cache fault-tolerant capability |
| CN109032524A (en) * | 2018-07-26 | 2018-12-18 | 浪潮电子信息产业股份有限公司 | A kind of method and relevant apparatus of bad block label |
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| CN109087683B (en) * | 2018-07-26 | 2021-08-17 | 西京学院 | NAND Flash solid state storage self-adaptive error control method |
| CN109739682A (en) * | 2018-12-21 | 2019-05-10 | 山东华芯半导体有限公司 | Applied to the adaptive polar code error-correcting code system and method in flash controller |
| CN109739682B (en) * | 2018-12-21 | 2021-04-02 | 山东华芯半导体有限公司 | Self-adaptive polar code error correcting code system and method applied to flash memory controller |
| CN110232002A (en) * | 2019-08-09 | 2019-09-13 | 深圳市硅格半导体有限公司 | A kind of method, system and device for promoting flash memory and reading accuracy |
| CN111294061A (en) * | 2020-02-11 | 2020-06-16 | 上海威固信息技术股份有限公司 | Decoding soft decision delay reduction method for original bit error rate perception |
| CN111294061B (en) * | 2020-02-11 | 2021-01-05 | 上海威固信息技术股份有限公司 | Decoding soft decision delay reduction method for original bit error rate perception |
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