CN103888148A - LDPC hard decision decoding method for dynamic threshold value bit-flipping - Google Patents

LDPC hard decision decoding method for dynamic threshold value bit-flipping Download PDF

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CN103888148A
CN103888148A CN201410105530.2A CN201410105530A CN103888148A CN 103888148 A CN103888148 A CN 103888148A CN 201410105530 A CN201410105530 A CN 201410105530A CN 103888148 A CN103888148 A CN 103888148A
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hard decision
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syndrome
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CN103888148B (en
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高美洲
李峰
张洪柳
刘大铕
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Shandong Sinochip Semiconductors Co Ltd
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    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105Decoding
    • H03M13/1108Hard decision decoding, e.g. bit flipping, modified or weighted bit flipping

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  • Engineering & Computer Science (AREA)
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Abstract

The invention discloses an LDPC hard decision decoding method for dynamic threshold value bit-flipping. An initial flipping threshold value T is determined, a dynamic threshold value, namely, a dynamic flipping threshold value is adopted, the flipping threshold value is changed into the dynamic threshold value so that the misflipping probability can be reduced, the number of times of iterations of decoding is reduced, and bit-flipping decoding of an LDPC is efficient. Meanwhile, the error correcting capability of the LDPC is improved. The error correcting capability of the LDPC hard decision decoding method is better than that of a standard bit-flipping method.

Description

A kind of LDPC code Hard decision decoding method of dynamic threshold bit reversal
Technical field
The present invention relates to the bit reversal building method of a kind of LDPC (Low Density Parity Check, low density parity check code) Hard decision decoding device.
Background technology
Need to carry out in the application of signal transmission various, often can adopt error correcting code (ECC, Error Correcting Code), can make signal transmission errors time, righted the wrong and obtain correct signal at receiving terminal.
Error correcting code can be applied in many systems, in communication system, may be subject to the interference of channel effect and interchannel noise, thereby cause the data of storing in flash memory device incorrect when signal transmission.The data of storing in flash memory device are the data after error correcting code device code, and for flash memory storage control device, error correcting code is an essential functional unit.
Along with the technique of memory is more and more advanced, memory cell volume is more and more less, and the data that memory cell is stored are also increasing gradually, causes flash memories constantly to raise reading the error probability producing in process.Therefore, the error correcting code error correcting capability of flash memories control device is to determine the whether qualified key factor of storage control device.But, in flash memory storage control device, adopt stronger error correcting code to need higher operand and longer operation time, thereby the application of increase flash memories control device is very restricted.
LDPC code is a kind of packeting error-correcting code with sparse check matrix that Robert Gallager proposed in thesis for the doctorate in 1962.Almost be applicable to all channels, its performance is approached shannon limit, and describes and realize simple, and the simple and practicable parallel work-flow of decoding, is applicable to hardware and realizes.
LDPC code has huge application potential, in deep space communication, optical fiber communication, satellite communication, satellite digital video, digital watermarking, magnetic/light/Hologram Storage, movement and fixed radio communication, cable modulating/demodulating and digital subscriber, is used widely.
More and more advanced according to the technique of flash memory device, the error correcting capability of the error correcting code in flash memories control device also needs to strengthen.In current flash memories control device, main error correcting code is BCH code, along with increasing of error probability, and BCH code space requirement and operational capability are also increased gradually; Along with the raising of flash memory storage technique, the error correcting capability of BCH code has been not suitable for the development of flash technology gradually, so need the error correcting code that error correcting capability is stronger.It is more appropriate selecting LDPC code to replace BCH code.
In the Hard decision decoding device of LDPC code, the setting of bit reversal threshold value T, plays vital effect to the Hard decision decoding of LDPC code, and it affects the error correcting capability of LDPC code and its decoding rate.
Increase the iterations of decoding if what bit reversal threshold value T set crosses conference, thereby affect decoding rate.
If the too small meeting that bit reversal threshold value T sets causes mistake upset just to increase like this iterations of decoding, thereby affects decoding rate.
For irregular check matrix, choose fixing bit reversal threshold value T, thereby can cause like that the very large mistake probability that overturns greatly to increase the iterations of decoding, serious in the situation that, cause decoding failure.
When the error rate of code element in sequence Z reaches certain value, use fixing bit reversal threshold value T to carry out decoding, decoder iterations is much can successfully not carry out decoding.
Summary of the invention
Based on dynamic threshold, the object of the present invention is to provide a kind of LDPC code Hard decision decoding method of dynamic threshold bit reversal, improve decoding rate and error correcting capability.
The present invention is by the following technical solutions:
A LDPC code Hard decision decoding method for dynamic threshold bit reversal, determines an initial turn threshold T, comprises the following steps:
1) read codeword sequence, according to codeword sequence computing syndrome;
2) judge whether syndrome is zero, if zero, iteration stopped, output codons sequence; Otherwise enter step 3)
3) each symbol bits to each code word in codeword sequence, calculates the number that does not meet check equations that this symbol bits participates in;
4) calculate turn threshold: along with increasing of iterations, turn threshold T successively decreases, and obtains current turn threshold;
5) if the number of ungratified check equations is greater than current turn threshold, corresponding symbol bits is overturn, and calculates the syndrome of the rear corresponding codeword sequence of upset;
6) repeating step 2), 3), 4) and 5), until successfully decoded, or while reaching maximum iteration time, output decoding failure.
The LDPC code Hard decision decoding method of above-mentioned dynamic threshold bit reversal, current turn threshold T:
T=j(b-c·m)/a;
In formula: it is that m represents current for which time iteration, j is that symbol bits is corresponding when prostatitis column weight, and a, b, c are experience normal number.
The LDPC code Hard decision decoding method of above-mentioned dynamic threshold bit reversal, determines an initial turn threshold T, and the step of overturning in iteration is as follows:
A) according to hard decision sequence Z=[z 0, z 1..., z n-1] computing syndrome S=[s 0, s 1..., s m-1]:
s m = Σ n = 0 N - 1 H mn z n T mod 2 , m = 0,1 , . . . , M - 1 ;
Wherein H mntest matrix, if syndrome S=0 stops iteration, output hard decision sequence Z also shows successfully decodedly, otherwise enters b);
B) to each symbol bits z n, calculate the number f of the ungratified check equations of its participation n:
f n = Σ m = 0 M - 1 s m H mn , n = 0,1 , . . . , N - 1
If f n> T, z overturns n, obtain new hard decision sequence Z;
C) repeat a) and b) until successfully decoded, or reach maximum iteration time and show decoding failure;
Hard decision sequence is step 5) codeword sequence that obtains after upset.
According to the present invention, adopt dynamic threshold, namely dynamic turn threshold, becomes dynamic threshold by turn threshold and can reduce the probability that mistake is overturn, and has also reduced the iterations of decoding, makes the bit-flipping decoding of LDPC code more efficient; Also the error correcting capability that has improved LDPC code, the present invention strengthens to some extent than the error correcting capability of the bit reversal method of standard simultaneously.
Accompanying drawing explanation
Fig. 1 is the theory diagram of flash memories memory control device.
Fig. 2 is LDPC symbol bits upset decoding flow chart.
Embodiment
LDPC code is the one of linear block codes, and it has all characteristics of linear block codes.LDPC code can be divided into rule (regular-LDPC) and irregular (irregular-LDPC) two large class hypothesis check matrix H 0for m × n rank matrix, regular LDPC code can be remembered and is (n, j, k), wherein n is code length, j is weight (i.e. 1 the number in row of the every row of check matrix, be called for short column weight (column weight), k is weight (1 the number at once of the every row of check matrix, be called for short row heavy (row weight)), and generally have j>2,1 number of the check matrix each row and column of k>j and irregular LDPC codes is incomplete same.
The interative encode method of LDPC code is broadly divided into two kinds: one is hard-decision method, and one is soft decision method.What hard-decision bits method for turning transmitted in iterative process is binary system hard information, and soft decision method transmits in iterative process is and the soft information of real number of probability correlation.Hard-decision method is simple to operate, be easy to hardware and realize, but error-correcting performance is general; Soft decision method better performances, but implementation complexity is higher.This programme improves mainly for Hard decision decoding device and improves its error correction energy ability.The detailed process of the hard-decision bits upset interpretation method of LDPC code is introduced as follows.
Bit reversal method is taken turns in iteration every, first according to the value of last round of hard decision sequence computing syndrome.If all syndrome is 0, stop iteration, and show successfully decoded, otherwise the number of the check equations that the syndrome of calculating each bit participation is 1, the bit reversal that check equations number is greater than certain predetermined threshold threshold value T will be participated in not meeting, obtain a new hard decision sequence, then enter next round iteration, until successfully decoded or reach maximum iteration time and show decoding failure.Suitably select the size of threshold value T, can reach best decoding performance.
Hard decision sequence is the sequence after the sequence that needs decoding of decoder reception is overturn through bit reversal method.
Fig. 1 is the functional block diagram after an embodiment of flash memory storage control device simplifies.In flash memory storage controller, comprise LDPC code decoder.Flash memory storage controller is mainly responsible for the read-write of data and the storage of data and other function.
Flash memory storage controller obtains that data are encoded computing through LDPC code decoder and the data that produce store into flash memories from main frame.If the data that main frame goes in flash memories need flash memory storage controller to read out from flash memories, decode computing and produce data and input to main frame through LDPC code decoder.
Fig. 2 is the LDPC code coding method flow chart of dynamic threshold (in literary composition, dynamic threshold, turn threshold, dynamic turn threshold and bit reversal threshold value represent the title of same threshold value under different environments for use, those skilled in the art will readily understand) bit reversal.Obtain codeword sequence by flash memory storage controller from flash memories, ldpc code decoder reads this codeword sequence.The whole decode procedure of LDPC code as can be seen from Figure 2.Determine an initial turn threshold T, thereby its process is as follows:
(1) read after codeword sequence, according to codeword sequence computing syndrome;
(2) judge whether syndrome S is zero, and zero stops iteration if, output codons sequence also shows successfully decodedly, otherwise enters (3);
(3) each symbol bits to each code word in each codeword sequence, calculates the number of the ungratified check equations of its participation;
(4) adopt the mode of successively decreasing to determine new turn threshold;
(5), if ungratified check equations number is greater than new turn threshold, corresponding code word is overturn;
(6) repeat (2), (3), (4) and (5) until successfully decoded, or reach maximum iteration time and show decoding failure.
Code element: usually represent a binary digit with identical symbol of the time interval in digital communication, the signal in such time interval is called (binary system) code element.And this interval is called as Baud Length.Code word (code word) is made up of some code elements.
The Essential Terms that are this area about used term, it is not explained in detail, as syndrome, according to the general explanation of Principle of Communication, be Linear codes (n, k) syndrome of code, if the error correcting capability of this yard is t, all error patterns that weight is less than or equal to t so have unique syndrome (syndrome) corresponding with it.
About turn threshold, adopt given formula to successively decrease, amount of calculation is smaller, but representative bad, can not effectively represent the present situation of decoding.
On the method basis of the bit-flipping decoding of LDPC code, the LDPC code coding method of a kind of dynamic threshold bit reversal of proposition.Principle is, LDPC code is in the time carrying out bit-flipping decoding, and its turn threshold is a fixed value, the upset easily making the mistake in decode procedure, thus the iterations that has increased decoder makes decoding time long.For the more effective bit-flipping decoding that utilizes LDPC code, this case has proposed a kind of Hard decision decoding method of LDPC code of dynamic threshold bit reversal.Idiographic flow as shown in Figure 2.
In the Hard decision decoding device of LDPC code, the setting of bit reversal threshold value T, plays vital effect to the Hard decision decoding of LDPC code, and it affects the error correcting capability of LDPC code and its decoding rate.
Increase the iterations of decoding if what bit reversal threshold value T set crosses conference, thereby affect decoding rate.
If the too small meeting that bit reversal threshold value T sets causes mistake upset just to increase like this iterations of decoding, thereby affects decoding rate.
For irregular check matrix, choose fixing bit reversal threshold value T, thereby can cause like that the very large mistake probability that overturns greatly to increase the iterations of decoding, serious in the situation that, cause decoding failure.
When the error rate of code element in sequence Z reaches certain value, use fixing bit reversal threshold value T to carry out decoding, decoder iterations is much can successfully not carry out decoding.
The Hard decision decoding method of the LDPC code of a kind of dynamic threshold bit reversal that this programme proposes can effectively be avoided above-mentioned problem.The interpretation method of this patent can reduce the iterations of decoding, thereby has increased decoding rate; Also error correcting capability can be improved, more mistake in sequence Z can be entangled.
The formula of dynamic threshold: T=j (b-cm)/a.Wherein T is threshold value, and which time iteration m is, j is column weight, and a, b, c are experience normal number (technique of constant and flash memories and the mistake that need to entangle are relevant).
Wherein a, b, c are empirical, for constant, in formula, do not affect dynamic threshold " dynamically " characteristic, and as initial threshold can be thought the fixed threshold under normal condition, the fixed threshold that those skilled in the art determines accordingly, by obtaining the dynamic threshold directly related with iterations and column weight with the correlation of column weight and iterations, thereby can effectively reduce amount of calculation, improve decoding efficiency.Because experience Changshu is on " dynamically " not impact, therefore, do not repeat them here.
The column weight j of dynamic threshold T and check matrix, decoder are that number of times, the empirical of which time iteration is closely bound up.The column weight of check matrix is the limiting value of dynamic threshold, and it is less that the larger dynamic threshold T of decoder iterations changes space, the erroneous decision that empirical need to be corrected by flash memories technique and sequence Z.The iteration of decoder each time, the code element in sequence Z can judge and determine whether overturning according to the dynamic threshold of each code element, carries out multiple code elements at every turn and overturns.
Syndrome is check matrix H mnwith sequence Z transposition product the results are shown in following formula s m.
Bit reversal method concrete steps are as follows:
(a) according to hard decision sequence Z=[z 0, z 1..., z n-1] computing syndrome S=[s 0, s 1..., s m-1]:
s m = Σ n = 0 N - 1 H mn z n T mod 2 , m = 0,1 , . . . , M - 1
Wherein H mntest matrix, if syndrome S=0 stops iteration, output hard decision sequence Z also shows successfully decodedly, otherwise enters (b).
(b) to each symbol bits z n, calculate the number f of the ungratified check equations of its participation n:
f n = Σ m = 0 M - 1 s m H mn , n = 0,1 , . . . , N - 1
If f n> T, z overturns n, obtain new hard decision sequence Z.
(c) repeat (a) and (b) until successfully decoded, or reach maximum iteration time and show decoding failure.
Can find out, bit reversal method is simple hard-decision method, only needs logical operation, realizes very simple.

Claims (3)

1. a LDPC code Hard decision decoding method for dynamic threshold bit reversal, determines an initial turn threshold T, it is characterized in that, comprises the following steps:
1) read codeword sequence, according to codeword sequence computing syndrome;
2) judge whether syndrome is zero, if zero, iteration stopped, output codons sequence; Otherwise enter step 3)
3) each symbol bits to each code word in codeword sequence, calculates the number that does not meet check equations that this symbol bits participates in;
4) calculate turn threshold: along with increasing of iterations, turn threshold T successively decreases, and obtains current turn threshold; ;
5) if the number of ungratified check equations is greater than current turn threshold, corresponding symbol bits is overturn, and calculates the syndrome of the rear corresponding codeword sequence of upset;
6) repeating step 2), 3), 4) and 5), until successfully decoded, or while reaching maximum iteration time, output decoding failure.
2. the LDPC code Hard decision decoding method of dynamic threshold bit reversal according to claim 1, is characterized in that current turn threshold T:
T=j(b-c·m)/a;
In formula: it is that m represents current for which time iteration, j is that symbol bits is corresponding when prostatitis column weight, and a, b, c are experience normal number.
3. the LDPC code Hard decision decoding method of dynamic threshold bit reversal according to claim 1 and 2, determines an initial turn threshold T, it is characterized in that, the step of overturning in iteration is as follows:
A) according to hard decision sequence Z=[z 0, z 1..., z n-1] computing syndrome S=[s 0, s 1..., s m-1]:
s m = Σ n = 0 N - 1 H mn z n T mod 2 , m = 0,1 , . . . , M - 1 ;
Wherein H mntest matrix, if syndrome S=0 stops iteration, output hard decision sequence Z also shows successfully decodedly, otherwise enters b);
B) to each symbol bits z n, calculate the number f of the ungratified check equations of its participation n:
f n = Σ m = 0 M - 1 s m H mn , n = 0,1 , . . . , N - 1
If f n> T, z overturns n, obtain new hard decision sequence Z;
C) repeat a) and b) until successfully decoded, or reach maximum iteration time and show decoding failure;
Hard decision sequence is step 5) codeword sequence that obtains after upset.
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US12052033B2 (en) 2022-07-13 2024-07-30 Apple Inc. Scheduling of iterative decoding depending on soft inputs

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102004053656A1 (en) * 2004-09-10 2006-03-30 Technische Universität Dresden Signal processing system for signals with block based error protection codes has LDPC decoder in receiver end encoder in transmitter module
US20080028274A1 (en) * 2006-07-25 2008-01-31 Communications Coding Corporation Universal error control coding scheme for digital communication and data storage systems
CN102970047A (en) * 2012-12-01 2013-03-13 电子科技大学 Low density parity check (LDPC) code weighting gradient descent bit flipping and decoding algorithm based on average amplitude
CN103281090A (en) * 2013-05-29 2013-09-04 华南理工大学 Mixed modified weighted bit-flipping LDPC decoding algorithm

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103888148B (en) * 2014-03-20 2016-10-26 山东华芯半导体有限公司 A kind of LDPC code Hard decision decoding method of dynamic threshold bit reversal

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102004053656A1 (en) * 2004-09-10 2006-03-30 Technische Universität Dresden Signal processing system for signals with block based error protection codes has LDPC decoder in receiver end encoder in transmitter module
US20080028274A1 (en) * 2006-07-25 2008-01-31 Communications Coding Corporation Universal error control coding scheme for digital communication and data storage systems
CN102970047A (en) * 2012-12-01 2013-03-13 电子科技大学 Low density parity check (LDPC) code weighting gradient descent bit flipping and decoding algorithm based on average amplitude
CN103281090A (en) * 2013-05-29 2013-09-04 华南理工大学 Mixed modified weighted bit-flipping LDPC decoding algorithm

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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CN104283571A (en) * 2014-09-06 2015-01-14 复旦大学 LDPC decoder based on random calculation
CN104283571B (en) * 2014-09-06 2018-04-03 复旦大学 It is a kind of based on the ldpc decoder calculated at random
CN107135006A (en) * 2016-02-26 2017-09-05 爱思开海力士有限公司 Error-Correcting Circuit and error correcting method
CN107135006B (en) * 2016-02-26 2020-10-23 爱思开海力士有限公司 Error correction circuit and error correction method
CN108270517A (en) * 2016-12-30 2018-07-10 慧荣科技股份有限公司 Decoding method for decoding received information and related decoding device
CN108270517B (en) * 2016-12-30 2021-07-27 慧荣科技股份有限公司 Decoding method for decoding received information and related decoding device
US10917113B2 (en) 2016-12-30 2021-02-09 Silicon Motion, Inc. Decoding method and related apparatus
CN107423161B (en) * 2017-07-24 2019-07-02 山东华芯半导体有限公司 Applied to the adaptive LDPC code error-correcting code system and method in flash memory
WO2019019550A1 (en) * 2017-07-24 2019-01-31 山东华芯半导体有限公司 Self-adaptive ldpc code error correction code system and method applied to flash memory
CN107423161A (en) * 2017-07-24 2017-12-01 山东华芯半导体有限公司 Applied to the adaptive LDPC code error-correcting code system and method in flash memory
CN109818625B (en) * 2017-11-21 2022-10-21 慧荣科技股份有限公司 Low density parity check code decoder
CN109818625A (en) * 2017-11-21 2019-05-28 慧荣科技股份有限公司 Low-density parity checks code decoder and relevant method
CN110391815B (en) * 2018-04-18 2023-08-18 深圳大心电子科技有限公司 Decoding method and storage controller
CN110391815A (en) * 2018-04-18 2019-10-29 深圳大心电子科技有限公司 Coding/decoding method and store controller
CN108563534B (en) * 2018-04-24 2021-09-14 山东华芯半导体有限公司 LDPC decoding method suitable for NAND flash memory
CN108563534A (en) * 2018-04-24 2018-09-21 山东华芯半导体有限公司 LDPC interpretation methods suitable for nand flash memory
CN109412611A (en) * 2018-09-12 2019-03-01 珠海妙存科技有限公司 A method of reducing LDPC error floor
CN109412611B (en) * 2018-09-12 2022-06-10 珠海妙存科技有限公司 Method for reducing LDPC error code flat layer
CN109347485A (en) * 2018-09-29 2019-02-15 山东存储之翼电子科技有限公司 Construct the method and LDPC code Compilation Method of LDPC check matrix
CN109660263A (en) * 2018-11-22 2019-04-19 华中科技大学 A kind of LDPC code interpretation method suitable for MLC NAN flash memory
CN109660263B (en) * 2018-11-22 2022-07-05 华中科技大学 LDPC code decoding method suitable for MLC NAND flash memory
CN110572164A (en) * 2019-09-29 2019-12-13 深圳忆联信息系统有限公司 LDPC decoding method, apparatus, computer device and storage medium
CN110572164B (en) * 2019-09-29 2023-02-10 深圳忆联信息系统有限公司 LDPC decoding method, apparatus, computer device and storage medium
CN113345513A (en) * 2020-03-02 2021-09-03 美光科技公司 Configuring iterative error correction parameters using criteria from previous iterations
CN113342568A (en) * 2020-03-02 2021-09-03 美光科技公司 Iterative error correction with adjustable parameters after a threshold number of iterations
CN113345513B (en) * 2020-03-02 2024-08-20 美光科技公司 Configuring iterative error correction parameters using criteria from a previous iteration
CN111654292B (en) * 2020-07-20 2023-06-02 中国计量大学 Dynamic threshold-based split simplified polarization code continuous elimination list decoder
CN111654292A (en) * 2020-07-20 2020-09-11 中国计量大学 Split simplified polar code continuous elimination list decoder based on dynamic threshold
CN112003626B (en) * 2020-08-31 2023-11-10 武汉梦芯科技有限公司 LDPC decoding method, system and medium based on navigation message known bits
CN112003626A (en) * 2020-08-31 2020-11-27 武汉梦芯科技有限公司 LDPC decoding method, system and medium based on known bits of navigation message
CN114629505A (en) * 2021-08-03 2022-06-14 深圳宏芯宇电子股份有限公司 Decoding method, decoding device, equipment and storage device
CN114629505B (en) * 2021-08-03 2024-08-27 深圳宏芯宇电子股份有限公司 Decoding method, decoding device, equipment and storage device
WO2023246473A1 (en) * 2022-06-24 2023-12-28 华为技术有限公司 Decoding method, chip and related apparatus
CN116192166A (en) * 2023-04-28 2023-05-30 南京创芯慧联技术有限公司 Iterative decoding method, iterative decoding device, storage medium and electronic equipment
CN116192166B (en) * 2023-04-28 2023-08-01 南京创芯慧联技术有限公司 Iterative decoding method, iterative decoding device, storage medium and electronic equipment
CN116505961B (en) * 2023-06-29 2023-09-29 深圳大普微电子科技有限公司 Decoding method and related device
CN116505961A (en) * 2023-06-29 2023-07-28 深圳大普微电子科技有限公司 Decoding method and related device

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