CN114629505A

CN114629505A - Decoding method, decoding device, equipment and storage device

Info

Publication number: CN114629505A
Application number: CN202110889582.3A
Authority: CN
Inventors: 不公告发明人
Original assignee: Hosin Global Electronics Co Ltd
Current assignee: Hosin Global Electronics Co Ltd
Priority date: 2021-08-03
Filing date: 2021-08-03
Publication date: 2022-06-14

Abstract

The application discloses a decoding method, a decoding device, equipment and a storage medium, wherein the method comprises the following steps: carrying out preset processing on the codeword to be decoded to obtain a hard decision sequence; calculating a syndrome vector S according to the hard decision sequence and a check matrix H of a code word to be decoded, wherein H ═ H_m,n]_M×N，h_m,nIs the element of the mth row and the nth column; if the syndrome vector is equal to the all-zero vector, outputting a hard decision sequence; otherwise, counting the sum element h_m,nBit z corresponding to 1_nParticipate in the calculation and make S_mNumber f not equal to 0_n(ii) a If f_nIf the bit is greater than or equal to the flip threshold, the bit z is set_nThe level of the data is turned to obtain a new hard decision sequence, and the turning threshold is adjusted according to the number of continuous non-turned bits or the number of continuous turned bits; and adding 1 to the iteration times, and performing the next iteration calculation on the updated hard decision sequence. The method has the advantages of fast algorithm convergence, high decoding efficiency, high decoding accuracy and reduced calculation amount.

Description

Decoding method, decoding device, equipment and storage device

Technical Field

The present application relates to the field of encoding and decoding technologies, and in particular, to a decoding method, a decoding device, a decoding apparatus, and a storage device.

Background

Low Density Parity Check (LDPC) codes are linear codes defined by a Check matrix, and have been widely used in the fields of deep space communications, optical fiber communications, satellite digital video, audio broadcasting, and the like.

Bit Flipping (BF) decoding is a hard decision decoding method proposed by Gallager, which is applied to LDPC code decoding, and the decoding method flips only one Bit having the largest Flipping weight in each iteration process. Under the limited iteration times, the bit number which can be corrected by BF decoding is very limited, and the algorithm is slow in convergence, so that the decoding efficiency is not high.

Disclosure of Invention

In view of this, the present application provides a decoding method, a decoding apparatus, a device and a storage medium, so as to solve the problem of low decoding efficiency of the existing decoding method.

The decoding method provided by the embodiment of the application comprises the following steps:

the method comprises the steps of presetting a codeword to be decoded to obtain a hard decision sequence z ═ z₀，z₁，…，z_N-1]；

Calculating a syndrome vector S according to the hard decision sequence and a check matrix H of the code word to be decoded, wherein H ═ H_m，n]_M×N，h_m，nM is 0, 1,.. M-1, N is 0, 1,. N-1 for the elements in the mth row and nth column of the check matrix;

S＝(S₀，S₁，...，S_M-1)^T；

if the syndrome vector is equal to an all-zero vector, outputting the hard decision sequence; otherwise, counting the sum element h_m,nBit z corresponding to 1_nParticipate in the calculation and make S_mNumber f not equal to 0_n；

If f_nIf the bit is larger than or equal to the turnover threshold, the bit z is set_nThe level of the data is turned over to obtain a new hard decision sequence, wherein the turning threshold is adjusted according to the number of continuous bits which are not turned over or the number of continuous bits which are turned over;

adding 1 to the iteration times, returning to the check matrix H according to the hard decision sequence and the code word to be decoded, and calculating a syndrome vector S; so as to perform the next iteration calculation on the updated hard decision sequence.

Optionally, the adjusting the flipping threshold according to the number of consecutive bits that are not flipped includes:

and if the number of the continuous non-overturned bits is larger than or equal to a first preset threshold, reducing the overturning threshold.

Optionally, if the number of consecutive bits that are not flipped is greater than or equal to a first preset threshold, then turning down the flipping threshold includes:

and if the number of the continuous non-inverted bits is larger than or equal to a first preset threshold value, subtracting 1 from the inversion threshold value.

Optionally, the adjusting the flipping threshold according to the number of bits that are continuously flipped further includes:

and if the number of the continuously turned bits is larger than or equal to a second preset threshold value, adjusting the turning threshold value to be larger.

Optionally, if the number of continuously flipped bits is greater than or equal to a second preset threshold, increasing the flipping threshold includes:

and if the number of the continuously turned bits is larger than or equal to a second preset threshold, adding 1 to the turning threshold.

Optionally, the check matrix includes a plurality of cyclic matrices, where the cyclic matrices are obtained by cyclically shifting elements in a base matrix, and the elements in the base matrix are obtained by shifting an identity matrix.

Optionally, the obtaining a hard decision sequence after performing preset processing on the codeword to be decoded includes:

modulating the code word to be decoded to obtain a first sequence;

acquiring a second sequence of the first sequence after channel processing;

and obtaining the hard decision sequence according to the second sequence.

An embodiment of the present application further provides a decoding apparatus, including:

a preprocessing module, configured to perform a preset process on a codeword to be decoded to obtain a hard decision sequence z ═ z₀，z₁，…，z_N-1]；

A calculating module, configured to calculate a syndrome vector S according to the hard decision sequence and a check matrix H of the codeword to be decoded, where H ═ H_m，n]_M×N，h_m，nM is 0, 1,.. M-1, N is 0, 1,. N-1 for the elements in the mth row and nth column of the check matrix;

S＝(S₀，S₁，...，S_M-1)^T；

a statistical module, configured to output the hard decision sequence if the syndrome vector is equal to a full zero vector; otherwise, the sum element h is counted_m，nBit z corresponding to 1_nParticipate in the calculation and make S_mNumber f not equal to 0_n；

A flip module for the number f_nIf the bit is larger than or equal to the turnover threshold, the bit z is set_nThe level of the data is turned over to obtain a new hard decision sequence, and the turning threshold is adjusted according to the number of continuous bits which are not turned over or the number of continuous bits which are turned over;

the counting module is used for adding 1 to the iteration times, returning to the check matrix H according to the hard decision sequence and the code word to be decoded, and calculating a syndrome vector S; so as to perform the next iteration calculation on the updated hard decision sequence.

An embodiment of the present application further provides an apparatus, including: the decoding device comprises a memory and a processor, wherein the memory stores a computer program, and the computer program realizes the flow in the decoding method provided by the application when being executed by the processor.

The present application also provides a computer-readable storage medium, on which a computer program is stored, which, when executed on a computer, causes the computer to execute the procedures in the decoding method provided in the present application.

As described above, the decoding method according to the embodiment of the present application inverts all bits that reach the inversion threshold, and has fast algorithm convergence and high decoding efficiency. In addition, because the turning threshold of the embodiment of the application is dynamically adjusted according to the number of continuous non-turned bits or the number of continuous turned bits, under the adjustment strategy, the turning threshold can be adjusted in real time according to the polluted condition of each section of the code word to be decoded, the decoding accuracy rate is considered under the condition of improving the decoding efficiency, and whether the turning threshold is adjusted once or not is not required to be judged according to the turning number of each group of bits, so that the calculated amount is reduced.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a flowchart illustrating a decoding method according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a decoding process;

FIG. 3 is a decoding schematic;

FIG. 4 is a flowchart illustrating another decoding method according to an embodiment of the present application;

fig. 5 is a schematic diagram illustrating threshold adjustment of a decoding method according to an embodiment of the present application;

FIG. 6 is a comparison between the decoding method of the present application and the conventional decoding method;

FIG. 7 is a block diagram of a decoding apparatus according to an embodiment of the present application;

fig. 8 is a schematic structural diagram of an apparatus according to an embodiment of the present application.

Detailed Description

The technical solutions of the present application are described below clearly and completely by way of examples, and it is obvious that the described examples are only a part of the examples of the present application, and not all of the examples. The following embodiments and their technical features may be combined with each other without conflict.

The embodiment of the application provides a decoding method, which is applied to decoding of an LDPC code, and a flow diagram is shown in fig. 1, where the decoding method includes:

s101, after the code word to be decoded is subjected to preset processing, a hard decision sequence z ═ z is obtained₀，z₁，…，z_N-1]。

The LDPC code, which is one of linear block codes, is a binary codeword. In the process of transmitting the code word to be decoded, the channel preprocesses the code word to be decoded, and in the preprocessing process, the code word to be decoded is polluted by noise to different degrees.

In one embodiment, a hard decision is made on a sequence of channel outputs, e.g., a 1 greater than 0 element and a 0 less than 0 element in the output sequence, resulting in a hard decision sequence z ═ z₀，z₁，…，z_N-1]. It will be appreciated that the hard decision sequence is a binary sequence.

S102, calculating a syndrome vector S according to the hard decision sequence and a check matrix H of the code word to be decoded, wherein H ═ H_m，n]_M×N，h_m，nM-1, which is an element in the mth row and the nth column of the check matrix, wherein M is 0, 1; n-1, 0, 1.

S＝(S₀，S₁，...，S_M-1)^T；

The LDPC code is composed as shown in fig. 2, a transmitted N-bit LDPC codeword C to be decoded is composed of information bits (K-bit information symbols) and check bits (M-bit check symbols), and error correction and decoding are performed at a receiving end by using a rule between the check bits and the information bits.

LDPC codes are determined by their sparse check matrix H, which has dimension M × N, i.e., H ═ H_m，n]_M×N，h_m，nThe elements of the mth row and the nth column of the check matrix are shown, wherein each column of H has gamma '1', each row has rho '1', and the rest elements are"0", i.e., the column weight of the check matrix H is γ, and the row weight is ρ. Each row of the check matrix H represents a check constraint equation, and the number of rows represents the number of check equations.

If the length of an LDPC code is several kilobits or even longer, the check matrix needs to occupy a large storage space, and thus the check matrix needs to be constructed. In some embodiments, the check matrix may be constructed by a Gallager random construction method, specifically, a check matrix of the LDPC code is constructed by random permutation and combination using the determined sparse matrices with fixed row weights and column weights. The check matrix may also be constructed by a quasi-cyclic construction method, specifically, a check matrix of the LDPC code is constructed by using a group of cyclic matrices, for example, a unit matrix is selected as a quasi-cyclic LDPC code (QC-LDPC). In one embodiment, the identity matrix is subjected to element displacement to obtain a base matrix, the base matrix is circularly displaced to the left to form a cyclic matrix, each cyclic matrix forms a final check matrix, and only the base matrix is stored, so that the storage space is greatly reduced. If the dimension of each sub-matrix is D × D, the check matrix column weight is γ, and the row weight is ρ, then dimension M of the check matrix is D × γ, and N is D × ρ.

An LDPC code iterative decoding process can be represented by using a Tanner graph shown in fig. 3, message iteration is performed between a variable node and a check node between a check symbol and an information symbol through the check equation, and a sequence obtained after each iterative error correction is a new hard decision sequence. If the correct code word is not obtained after one-time decoding, carrying out next iteration on the new hard decision sequence obtained this time until the new hard decision sequence meeting the requirement of z x H is found^T＝0^TAnd (all 0 vectors) code words, namely the code words meet all check equations, and the output information z is the decoded code words.

In one embodiment, the iterative computation process is as follows: hard decision sequence z ═ z according to LDPC code₀，z₁，…，z_N-1]And a check matrix H of the LDPC code, and calculating a syndrome vector S. Check matrix H ═ H_m，n]_M×N，h_m，nThe element of the mth row and the nth column of the check matrix;

S＝(S₀，S₁，...，S_M-1)^T＝zH^T

wherein S is_mThe specific calculation method is as follows:

i.e. the value S of each element in the syndrome vector S_mIs equal to the row (mth row) vector [ H ] of the hard decision sequence z corresponding to the check matrix H_m，1，h_m，2，...，h_m，n]Divided by 2 and left. The element in the syndrome vector S is 0 or 1.

S103, if the syndrome vector is equal to the all-zero vector, outputting a hard decision sequence; otherwise, counting the sum element h_m，nBit z corresponding to 1_nParticipate in the calculation and make S_mNumber f not equal to 0_n。

S_mThe calculation result of (A) represents whether the mth check equation is satisfied, if S is satisfied_mIf 0, it means that the hard decision sequence z satisfies the mth check equation, if S_mAnd 0, the hard decision sequence z does not satisfy the mth check equation. When S is 0^TAnd then, namely when the calculation result of the syndrome vector S is an all-zero vector, the hard decision sequence z meets all constraint relations in the check matrix, which indicates that the decoding is successful, and the hard decision sequence z can be output.

When S appears in syndrome vector S_mNot equal to 0, and there may be multiple elements in the syndrome vector S that are not equal to 0. Counting each bit z in a hard decision sequence_nParticipate in the calculation and make S_mNumber f not equal to 0_n；

For example, if S₁₀Not equal to 0 and the elements n-3 and n-5 in the 10 th row of the check matrix are both 1, then z in the hard decision sequence z is₃And z₅Participate in calculating S₁₀Correspond toF of (a)₃And f₅Respectively increased by 1. If S₁₅Not equal to 0 and the element with n equal to 3 in the 15 th row of the check matrix is 1, then z is₃Participate in calculating S₁₅Corresponding to f₃The calculation continues to increase by 1. At this time, z₃Number f of unsatisfied check equations ₃2, respectively the 10 th and 15 th check equations, z₅Number f of unsatisfied check equations ₅1, the 10 th check equation.

S104, if f_nIf the bit is greater than or equal to the flip threshold, the bit z is set_nThe level of the bit is inverted to obtain a new hard decision sequence, wherein the inversion threshold is adjusted according to the number of continuous non-inverted bits or the number of continuous inverted bits.

Will bit z_nParticipate in the calculation and make S_mNumber f not equal to 0_nComparing with a turning threshold T1 if f_nGreater than or equal to the flip threshold, bit z is set_nIs inverted. And obtaining a new hard decision sequence after completing the turnover according to the turnover rule. The flipping threshold is adjusted according to the number of continuous un-flipped bits or the number of continuous flipped bits.

For example, when the number of bits that are continuously flipped is relatively large, for example, greater than or equal to the second preset threshold, the sensitivity may be reduced, the flipping threshold is appropriately adjusted to be large, false flipping is avoided, and the decoding accuracy is improved; for another example, when the number of bits that are continuously flipped is smaller than the second preset threshold, the current flipping threshold may be kept unchanged; for example, if the number of consecutive non-inverted bits is greater than or equal to the first preset threshold, the inversion threshold may be adjusted smaller according to a predetermined manner, so as to increase the convergence rate and improve the decoding efficiency.

In a particular embodiment, e.g. bit z₇₅A plurality of check equations are involved in the calculation, namely, the 74 th column (n is 75) in the check matrix contains a plurality of elements 1, wherein the calculation results S of the 1 st, 5 th, 19 th, 31 th, 55 th and 89 th check equations₁，S₅，S₁₉，S₃₁，S₅₅，S₈₉Is not equal to zero, then z₇₅Unsatisfied checking equation number f _n6, if the current rollover threshold T1 is 5, i.e., f_n> T1, bit z is flipped₇₅And 1 is inverted to 0. According to the method, if z₇₅～z₈₅If the second preset threshold is 10, and the number of bits that are continuously flipped at this time is greater than the second preset threshold, the flipping threshold T1 is increased by 5, for example, T1 may be increased by 1.

And S105, adding 1 to the iteration times, and returning to S102 to perform the next iteration calculation on the updated hard decision sequence.

After the hard decision sequence z is turned over to obtain a new hard decision sequence, the step returns to S102, and the new hard decision sequence is substituted into the check equation S_mA new round of iterative computation is performed.

In one embodiment, if the iteration number k is less than the predetermined iteration number threshold k_maxIf k is k +1, the process returns to S102, and a new round of iterative calculation is performed. If k is not less than k_maxDecoding may be terminated, indicating a decoding failure.

In the iterative decoding process, only one bit with the maximum flipping weight is flipped, which results in very limited number of bits that can be corrected by flipping decoding under limited iteration number, slow algorithm convergence, and low decoding efficiency. According to the decoding method, the bits reaching the turning threshold are turned, algorithm convergence is fast, and decoding efficiency is high. And because the turning threshold of the embodiment of the application is dynamically adjusted according to the number of continuous non-turned bits or the number of continuous turned bits, the turning threshold can be adjusted in real time according to the polluted condition of each section of the code word to be decoded under the adjustment strategy, the decoding accuracy rate is considered under the condition of improving the decoding efficiency, and whether the turning threshold is adjusted once or not is not required to be judged according to the turning number of each group of bits, so that the calculated amount is reduced.

An embodiment of the present application provides another decoding method, a flowchart of which is shown in fig. 4, the decoding method includes:

s401, modulating the code word to be decoded to obtain a first sequence.

Referring to fig. 2, a binary codeword c to be decoded with K information bits, M check bits, and N total length is transmitted through a channel [ c ═ c₀，c₁，…，c_N-1]. In one embodiment, the channel takes a mean of 0 and a variance of σ²＝N₀The additive white gaussian noise channel (AWGN) of/2 is modulated by Binary Phase Shift Keying (BPSK). Modulating the code word to be decoded to obtain a first sequence x ═ x₀，x₁，…，x_N-1]Wherein x is_n＝1-2c_n，0≤n≤N-1。

S402, acquiring a second sequence of the first sequence after channel processing.

In one embodiment, the first sequence x is contaminated by gaussian noise after being transmitted through the channel, if the variance of gaussian noise is v_nThen the first sequence x passes through an additive white gaussian noise channel to output a second sequence r ═ r₀，r₁，…，r_N-1]Wherein r is_n＝x_n+v_n，0≤n≤N-1。

And S403, obtaining a hard decision sequence according to the second sequence, and dividing the bit in the hard decision sequence into Q groups according to the structure of the check matrix, wherein Q is more than or equal to 2.

And carrying out hard decision on the second sequence. In one embodiment, the hard decision rule is: if r is_nGreater than or equal to 0, then z_nIf r is 0_nIf < 0, then z_nN is more than or equal to 1 and less than or equal to 0 and less than or equal to N-1, and the second sequence is subjected to hard decision to obtain a hard decision sequence z which is more than or equal to [ z [₀，z₁，…，z_N-1]。

In one embodiment, the LDPC codeword c may be grouped in advance, for example, into Q groups, and after the LDPC codeword c is output by a channel and is subjected to hard decision, Q groups of hard decision sequences z including corresponding sequences are obtained. For example, the first Q-1 groups have the same bit length and are all L0, and the last group has a bit length of N- (Q-1) L0.

S404, initializing iteration times and a flipping threshold, setting an iteration time threshold, and setting a first preset threshold T2 corresponding to the number of continuous non-flipped bits and a second preset threshold T3 corresponding to the number of continuous flipped bits.

In one embodiment, the initial iteration number k may be set to 1, and the maximum iteration number threshold k may be set_max50, an initial rollover threshold T1-5, a first preset threshold T2-35, and a second preset threshold T3-30 may be set.

S405, according to the hard decision sequence z ═ z₀，z₁，…，z_N-1]And a check matrix H, and calculating a syndrome vector S, H ═ H_m，n]_M×N，h_m，nIs the element of the mth row and nth column of the check matrix.

S102 may be referred to in this step, and this embodiment is not described again.

S406, if the syndrome vector is equal to the all-zero vector, outputting a hard decision sequence; otherwise, counting the sum element h_m，nBit z corresponding to 1_nParticipate in the calculation and make S_mNumber f not equal to 0_n。

S103 may be referred to in this step, and this embodiment is not described again.

S407, if f_nGreater than or equal to the flip threshold, bit z is set_nThe level of the bit is turned to obtain a new hard decision sequence, wherein the turning threshold is adjusted according to the number of continuous non-turned bits or the number of continuous turned bits in the hard decision sequence.

Sequentially checking elements in the hard decision sequence, turning over the bits meeting the turning-over condition, and counting the number N of the continuously turned-over bits in real time₁And the number of consecutive non-toggled bits N₂。

In one embodiment, when the number of continuous non-inverted bits is greater than or equal to a first preset threshold, subtracting 1 from the inverted threshold, and taking the inverted threshold after subtracting 1 as the inverted threshold in the subsequent bit check; in one embodiment, when the number of bits that are continuously flipped is greater than or equal to a second preset threshold, adding 1 to the flipping threshold, and using the flipping threshold after adding 1 as the flipping threshold of the subsequent bit check; in an embodiment, when the number of bits that are not flipped continuously is smaller than a first preset threshold, or the number of bits that are flipped continuously is smaller than a second preset threshold, the flipping threshold may be kept unchanged, and the same flipping threshold is used for subsequent bit verification.

And S408, adding 1 to the iteration times, returning to the step S405, and performing iterative computation on the new hard decision sequence.

Step S105 may be referred to in this step, and this embodiment is not described again.

In the decoding method of the embodiment of the application, to improve the storage space, the code words to be decoded or the hard decision sequences are grouped according to the structure of the check matrix, in the process of checking and iterating the hard decision sequences, the turning threshold is adjusted according to the number of continuous non-turned bits or the number of continuous turned bits, so that in each iteration, the turning threshold is in dynamic adjustment, and each iteration can turn over the corresponding bits in a better mode.

The present application is described in further detail below with reference to a specific embodiment.

Taking the check matrix H comprising 4 × 40 sub-matrices as an example, where the dimension of the sub-matrix is 45 × 45, then the dimension of H is: the decoding process is as follows, where M is 4 × 45 equals 180, N is 40 × 45 equals 1800, the length of the binary LDPC codeword is 1800, and the number M of check equations equals 180:

s501, initializing, wherein the current iteration number k is 1, and the maximum iteration number k_maxThe switching threshold T1 is 5, the first preset threshold T2 is 35, and the second preset threshold T3 is 30.

S502, the initial hard decision sequence z¹＝[z₀，z₁，…，z₁₈₀₀]And sequentially dividing the initial hard decision sequence into 40 groups, wherein each group has 45 bits, and performing iterative decoding on the initial hard decision sequence.

S502, calculating a syndrome vector S, if S¹＝0^TIf decoding is successful, z is output¹. Otherwise, S503 is executed.

S503，Count each bit z_nParticipate in the calculation and make S_mNumber f not equal to 0_nReferring to fig. 5, the abscissa represents the bit length, the ordinate represents the threshold, and each peak in the graph represents a bit flip, which is only a schematic diagram.

For each bit, if f_nAnd if the bit is more than or equal to 5, the bit is overturned. From z₀Initially, the number of consecutive non-flipped bits N is initialized₁Initializing the number of successively flipped bits N as 0₂When z is 0₅The number of consecutive non-inverted bits N when the first bit is level-inverted₁From 5 (z)₀～z₄Not flipped) becomes 0, counting is restarted, and the number of bits N flipped consecutively is N₂From 0 to 1, and when z₆～z₁₅All need to be turned over, then N₂Gradually increases from 1 to 11, and is at z₁₆When not turned over, N₂From 11 to 0, N₁It changes from 0 to 1.

In FIG. 5, point A (if corresponding to z)₈₅) Previously, since the number of consecutive non-toggled bits does not exceed the first preset threshold 35, and the number of consecutive toggles does not exceed the second preset threshold 30, the toggle threshold T1 ═ 5 remains unchanged. When z is₈₇Not flipped and the number of consecutive non-flipped bits reaches 35, at which point the flipping threshold is decremented by 1 and T1 equals 4.

According to the above rule, point B in FIG. 5 (if corresponding to z)₁₈₆) When the number of continuous non-inverted bits reaches 35, subtracting 1 from the inversion threshold, and T1 being 3; in FIG. 5 point C (if corresponding to z)₂₃₁) The number of consecutive flips reaches 30, the flip threshold is increased by 1, and T1 is equal to 4.

And analogizing in turn, decoding the rest groups and outputting a new hard decision sequence z after turning²。

S504, execute k + 1-2, return to step S502, and place the hard decision sequence z in²Substituting the formula for next iterative decoding.

The comparison graph of the decoding method and the effect of the traditional method for fixing the turnover threshold is shown in fig. 6, and under the condition of the same iteration times, the method can correct more bits and has higher decoding efficiency. And the flipping threshold is adjusted according to the number of continuously flipped bits or the number of continuously non-flipped bits, the change of the flipping threshold may occur in each group, but not necessarily at the last bit of each group, and the flipping threshold is adjusted in real time. Since it is not necessary to determine whether to adjust the flipping threshold once for the number of flips per group of bits, the amount of computation can be reduced.

As shown in fig. 7, the code decoding apparatus 700 includes a preprocessing module 701, a calculating module 702, a counting module 703, a flipping module 704, and a counting module 705.

A preprocessing module 701, configured to perform preset processing on a codeword to be decoded to obtain a hard decision sequence z ═ z₀，z₁，…，z_N-1]；

A calculating module 702, configured to calculate a syndrome vector S according to the hard decision sequence and a check matrix H of the codeword to be decoded, where H ═ H_m，n]M_×N，h_m，nM is 0, 1,.. M-1, N is 0, 1,. N-1 for the elements in the mth row and nth column of the check matrix;

S＝(S₀，S₁，...，S_M-1)^T；

a statistical module 703, configured to output the hard decision sequence if the syndrome vector is equal to an all-zero vector; otherwise, counting the sum element h_m，nBit z corresponding to 1_nParticipate in the calculation and make S_mNumber f not equal to 0_n；

A flip module 704 for if f_nIf the bit is larger than or equal to the turnover threshold, the bit z is set_nThe level of the data is turned over to obtain a new hard decision sequence, and the turning threshold is adjusted according to the number of continuous bits which are not turned over or the number of continuous bits which are turned over;

a counting module 705, configured to add 1 to the iteration number, and return to the check matrix H according to the hard decision sequence and the codeword to be decoded, to calculate a syndrome vector S; so as to perform the next iteration calculation on the updated hard decision sequence.

An embodiment of the present application further provides an apparatus, a schematic structural diagram of which is shown in fig. 8, where the apparatus 800 includes: a memory 801 and a processor 802, wherein the memory 801 has a computer program stored thereon, and the computer program implements a flow in the decoding method provided by the embodiment when executed by the processor 802.

Embodiments of the present application further provide a readable storage medium, on which a computer program is stored, and when the computer program is executed on a computer, the computer program causes the computer to execute the procedures in the decoding method provided in the present application.

The above-mentioned embodiments are only examples of the present application, and not intended to limit the scope of the present application, and all equivalent structures or equivalent flow transformations made by the contents of the specification and the drawings, such as the combination of technical features between the embodiments and the direct or indirect application to other related technical fields, are also included in the scope of the present application.

Claims

1. A decoding method, comprising:

S＝(S₀，S₁，...，S_M-1)^T；

if the syndrome vector is equal to an all-zero vector, outputting the hard decision sequence; otherwise, counting the sum element h_m，nBit z corresponding to 1_nParticipate in the calculation and make S_mNumber f not equal to 0_n；

If f_nIf the bit is larger than or equal to the turnover threshold, the bit z is set_nThe level of the data is turned to obtain a new hard decision sequence, wherein the turning threshold is adjusted according to the number of continuous non-turned bits or the number of continuous turned bits;

2. The decoding method according to claim 1, wherein the flipping threshold is adjusted according to a number of consecutive non-flipped bits, comprising:

3. The decoding method according to claim 2, wherein the adjusting the rollover threshold to be smaller if the number of consecutive non-rollover bits is greater than or equal to a first preset threshold comprises:

4. The decoding method according to claim 1, wherein the flipping threshold is adjusted according to a number of bits that are flipped consecutively, further comprising:

5. The decoding method according to claim 4, wherein if the number of bits that are flipped consecutively is greater than or equal to a second predetermined threshold, then adjusting the flipping threshold to be larger comprises:

6. The decoding method according to claim 1, wherein the check matrix comprises a plurality of cyclic matrices, wherein the cyclic matrices are obtained by cyclically shifting elements in a base matrix, and wherein the elements in the base matrix are obtained by shifting an identity matrix.

7. The decoding method according to claim 1, wherein the obtaining of the hard decision sequence after the pre-setting processing of the codeword to be decoded comprises:

modulating the code word to be decoded to obtain a first sequence;

acquiring a second sequence of the first sequence after channel processing;

and obtaining the hard decision sequence according to the second sequence.

8. A decoding apparatus, comprising:

S＝(S₀，S₁，...，S_M-1)^T；

a statistic module, configured to output the hard decision sequence if the syndrome vector is equal to an all-zero vector; otherwise, counting the sum element h_m，nBit z corresponding to 1_nParticipate in the calculation and make S_mNumber f not equal to 0_n；

A flip module for the number f_nIf the bit is larger than or equal to the turnover threshold, the bit z is set_nThe level of the data is turned to obtain a new hard decision sequence, and the turning threshold is adjusted according to the number of continuous non-turned bits or the number of continuous turned bits;

9. An apparatus, characterized in that the apparatus comprises: memory and a processor, wherein the memory has stored thereon a computer program which, when executed by the processor, implements the transcoding method of any of claims 1-7.

10. A storage device comprising a decoding device according to claim 8 or performing a decoding method according to any one of claims 1-7.