CN114050898B - QKD negotiation method based on HLS and LDPC code construction - Google Patents
QKD negotiation method based on HLS and LDPC code construction Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/08—Key distribution or management, e.g. generation, sharing or updating, of cryptographic keys or passwords
- H04L9/0816—Key establishment, i.e. cryptographic processes or cryptographic protocols whereby a shared secret becomes available to two or more parties, for subsequent use
- H04L9/0838—Key agreement, i.e. key establishment technique in which a shared key is derived by parties as a function of information contributed by, or associated with, each of these
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/63—Joint error correction and other techniques
- H03M13/635—Error control coding in combination with rate matching
- H03M13/6362—Error control coding in combination with rate matching by puncturing
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
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Abstract
The invention discloses a QKD negotiation method based on HLS and LDPC code construction, which comprises the following steps: acquiring a key X or Y to be corrected; estimating the error rate to obtain the initial error rate of the key to be corrected; obtaining a mother code matrix H and a target code rate R according to the initial error rate; judging whether the target code rate needs to be punched, jumping to a) without punching, and jumping to b) without punching: a) The data to be corrected is directly subjected to LDPC decoding, the LDPC decoder is optimized and generated based on an HLS tool, and error correction is completed after decoding is finished; b) Reading the punching vector from a pre-stored ROM, adding 0 to the corresponding position P of the data to be decoded, raising the code rate to the target code rate R, and performing LDPC decoding to finish error correction. The invention obtains the optimal punching position by using the grouping ordering algorithm, reduces the decoding performance loss caused by the code rate improvement by randomly selecting the punching position, and improves the error correction efficiency and the decoding success rate.
Description
Technical Field
The invention relates to the technical field of key negotiation of a QKD system, in particular to a QKD negotiation method constructed based on HLS and LDPC codes.
Background
During the communication process, the QKD is affected by channel noise or EVE interception, so that the keys obtained by the legal communication parties are inconsistent, and in order to share the same key, information negotiation is required to perform error correction on the key. Since error correction is the unit of greatest computational consumption in post-processing, it is a bottleneck to achieving high throughput post-processing capability. And with the development of semiconductor devices and single photon detectors thereof, higher key generation rates also place higher demands on the QKD post-processing.
In an actual QKD system, the initial bit error rate of the channel varies within a larger range, and the fixed bit LDPC code can only achieve higher negotiation efficiency in a narrower bit error rate interval. To accommodate the variation of the channel error rate, LDPC codes with multiple code rates can be added, which may put higher demands on hardware resources.
Traditional FPGA-based hardware designs require a designer to write RTL, which is a cumbersome task, requires detailed descriptions of the transmission of each gate and requires repeated debugging to meet the desired timing relationships, and has problems of low throughput and poor negotiation efficiency.
Disclosure of Invention
The invention aims to provide a QKD negotiation method which is high in throughput rate and negotiation efficiency and is constructed based on HLS and LDPC codes.
The technical solution for realizing the purpose of the invention is as follows: a QKD negotiation method based on HLS and LDPC code construction comprises the following steps:
step 1, obtaining a key X or Y to be corrected;
step2, estimating the error rate, and obtaining the initial error rate of the key to be corrected;
step 3, obtaining a mother code matrix H and a target code rate R according to the initial error rate;
Step 4, judging whether the target code rate needs to be punched or not, jumping to step 5 without punching, and jumping to step 6 without punching;
step 5, directly performing LDPC decoding on the data to be corrected, wherein the LDPC decoder is optimized and generated based on an HLS tool, and jumping to step 7 after decoding is finished;
Step 6, reading the punching vector from a pre-stored ROM, carrying out 0-giving operation on the corresponding position P of the data to be decoded, and carrying out LDPC decoding after the code rate is increased to the target code rate R;
And 7, completing error correction.
Compared with the prior art, the invention has the remarkable advantages that:
(1) The selected punching position for code rate improvement uses a grouping ordering algorithm, and compared with the traditional randomly selected position, the punching position generated by the algorithm improves decoding performance;
(2) By pre-storing the punching vectors in the ROM, the information negotiation can be performed under the higher negotiation efficiency by the adjustable code rate, the information leakage in the negotiation process is reduced, and the code rate of the system is improved;
(3) Compared with the error correction decoder in the prior art, the throughput rate of the decoder can reach 136Mbps;
(4) When the hardware architecture of the decoder is realized, a high-level comprehensive tool is adopted for realizing, so that the realization process of the decoder is greatly accelerated, and the workload of hardware realization is reduced.
Drawings
Fig. 1 is a flowchart of a QKD negotiation method based on HLS and LDPC code construction in accordance with the present invention.
Fig. 2 is a diagram of a decoder hardware architecture implemented using HLS in accordance with the present invention.
Fig. 3 is a diagram showing decoding negotiation efficiency results according to the present invention.
Detailed Description
The invention provides a Quantum Key Distribution (QKD) negotiation method with adjustable high throughput rate and code rate, which is constructed based on an advanced synthesis tool (HLS) and a Low Density Parity Check (LDPC) code.
Referring to fig. 1, the QKD negotiation method constructed based on HLS and LDPC codes of the present invention includes the steps of:
step 1, obtaining a key X or Y to be corrected;
step2, estimating the error rate, and obtaining the initial error rate of the key to be corrected;
step 3, obtaining a mother code matrix H and a target code rate R according to the initial error rate;
Step 4, judging whether the target code rate needs to be punched or not, jumping to step 5 without punching, and jumping to step 6 without punching;
step 5, directly performing LDPC decoding on the data to be corrected, wherein the LDPC decoder is optimized and generated based on an HLS tool, and jumping to step 7 after decoding is finished;
Step 6, reading the punching vector from a pre-stored ROM, carrying out 0-giving operation on the corresponding position P of the data to be decoded, and carrying out LDPC decoding after the code rate is increased to the target code rate R;
And 7, completing error correction.
Further, in step 3, the mother code matrix H and the target code rate R are obtained according to the initial error rate, which is specifically as follows:
The mother code matrix H is a check matrix with 1/2 code rate and 2/3 code rate specified by IEEE 802.16E standard, wherein the target code rate R is determined by the initial error rate obtained in the step 2, and the corresponding relation between the initial error rate and the target code rate is as follows:
when the initial error rate is 11% -9%), the target code rate R1=0.5;
When the initial error rate is [9% -8%), the target code rate R2=0.55;
When the initial error rate is 8% -6.61%), the target code rate R3=0.60;
When the initial error rate is 6.61% -5%), the target code rate R4=2/3;
when the initial error rate is [5% -4.1%), the target code rate R5=0.7;
When the initial error rate is 4.1% -3.5%), the target code rate R6=0.74;
when the initial error rate is 3.5% -2.8%), the target code rate R7 = 0.78;
when the initial error rate is 2.8% -2.4%), the target code rate R8=0.81;
when the initial error rate is 2.4% -2%), the target code rate R9=0.83;
at an initial bit error rate of 2% -1.86%), the target bit rate r10=0.84.
Further, the code rate is adjustable based on a puncturing algorithm to perform code rate lifting, and the puncturing in the step 4 refers to filling the corresponding position P of the key X or Y, where the position P is determined by the puncturing algorithm, and includes two steps of grouping and ordering:
Grouping: grouping all variable nodes by utilizing the concept of a recovery tree, and placing variable nodes requiring the same recovery step number into the same set;
Sequencing: and the variable nodes in the same set are ranked in front of the combination through a ranking algorithm, and when the punching position is selected, the variable nodes requiring fewer recovery steps are preferentially selected.
Further, the puncturing vector pre-stored in the ROM in step 6 is obtained based on a packet ordering puncturing algorithm, the algorithm is implemented by matlab, and puncturing positions P with the code rate R of 0.55, 0.6, 0.66, 0.6, 0.74, 0.78, 0.81 and 0.84 of 8 code rates are generated, and then the data is pre-stored in the ROM. The hardware system of the invention stores two mother code matrixes with code rate of 1/2 and 2/3A, realizes the segmentation punching of the code rate of 1/2 to 2/3 and 2/3 to 0.89, and realizes the code rate adjustment from 0.5 to 0.89 by calculating the variable node position of the target code rate needing punching in advance and then storing the generated punching vector in ROM.
Further, the hardware architecture of the LDPC decoder for performing LDPC decoding in the step 6 is generated based on HLS, the LDPC decoder uses Unroll and Pipeline instructions, unroll instructions are used in combination with the structural characteristics of the check matrix H in the hardware architecture generated through instruction constraint, and the parallelism of row updating is designed to be m, namely m check node updating units are updated simultaneously; the parallelism of column update is designed as n, namely n variable node update units update simultaneously, and all loop sentences inside the instruction are expanded by combining with the Pipeline instruction.
After the moving target code rate is obtained, reading out a punching vector from the ROM, carrying out 0 operation on the corresponding position of the initial likelihood ratio information, and entering into the LDPC decoding process after preprocessing is completed:
step 6-1) initializing prior probability:
where i, j represent the ith column and jth row of the check matrix H, Representing the probabilities of 0 and 1 of the ith bit respectively, wherein L (P i) represents the prior probability, q ij represents the transmission of the ith variable node to the jth check node, L (q ij) represents the log likelihood ratio information transmitted by the ith variable node, e represents the initial error rate obtained by error rate estimation, and k represents the iteration times;
Step 6-2) check node update:
Lk(rji)＝(1-2Sj)Πi′∈R(j)∣isgn(Lk-1(qi'j(.min|Lk-1(qi'j)|×α (2)
Wherein R ji denotes that the jth check node is transferred to the ith variable node, L (R ji) denotes that log likelihood ratio information is transferred, S j is syndrome information, i' e R (j)/i denotes variable nodes connected to the check node j except the ith variable node, and α is a normalization coefficient.
Step 6-3) variable node update:
Lk(qij)＝L(Pi)+∑j′∈C(i)\jLk(rj′i) (3)
Wherein j' e C (i)/j represents a check node connected to the i-th variable node except the check node j;
step 6-4) updating the posterior probability:
Wherein L (q i) represents variable node information, and j epsilon C (i) represents information transmitted to the variable node i by the check node j;
Step 6-5) decoding judgment:
c is the code word which is finally decoded, H is a check matrix, S is a syndrome, if the decoding result meets cH T =S, the decoding is successful, otherwise, the iterative decoding is continued, and when the maximum iterative decoding times are reached, the decoding is terminated, namely the decoding fails.
Examples
With reference to fig. 2, in this embodiment, check matrixes of two code rates, namely, QC-LDPC codes 1/2 and 2/3A of IEEE 802.16e standard are adopted, the code length n=1536, the target operating frequency is 250MHZ, the maximum iteration number is 20, the hardware system design is completed on Vivado HLS 2018.3, on-board verification is performed on a zynq ultrascale + zcu102 development board, the channel initial error rate epsilon [0.02,0.11] is selected, the negotiation efficiency of the code rate r= 0.5,0.55,0.6,0.66,0.7,0.74,0.78,0.81,0.83,0.84 is calculated, the negotiation efficiency of the code rate adjustable negotiation scheme seen in fig. 2 is between 1 and 1.32, and when the estimated initial error rate parameter is received, the system selects a suitable punching position according to the error rate range, so as to adjust to the target code rate for error correction. Therefore, the system can adapt to the change of the error rate in the negotiation process under the condition that the initial error rate is continuously changed along with time, and the high-quality information negotiation process is realized. The LDPC decoder is implemented by vivado HLS, the tool provides data types with arbitrary bit width, through data simulation, balance performance and resources, and finally 9bit quantization standard quantization information is selected, the hardware architecture of the LDPC decoder is shown in figure 3, under the hardware architecture, the throughput rate of the decoder is given by the following formula (1), wherein f clk represents the working frequency, θ represents the initialization interval, iter represents the iteration times, and the decoding throughput rate can reach 136Mbps.
The invention obtains the optimal punching position by using the grouping ordering algorithm, reduces the decoding performance loss caused by code rate improvement by randomly selecting the punching position, optimizes the realization architecture of the minimum and decoding algorithm based on the HLS tool, and provides the realization method which has the advantages of realizing complexity and high throughput rate. Compared with the traditional method for randomly selecting the punching position, the method improves error correction efficiency and decoding success rate, obtains a hardware implementation architecture with high throughput rate based on the HLS tool, and has the advantages of short development period and flexible function upgrading.
Claims (3)
1. A QKD negotiation method based on HLS and LDPC code construction, comprising the steps of:
step 1, obtaining a key X or Y to be corrected;
step2, estimating the error rate, and obtaining the initial error rate of the key to be corrected;
step 3, obtaining a mother code matrix H and a target code rate R according to the initial error rate;
Step 4, judging whether the target code rate needs to be punched or not, jumping to step 5 without punching, and jumping to step 6 without punching;
step 5, directly performing LDPC decoding on the data to be corrected, wherein the LDPC decoder is optimally generated based on an HLS tool, and jumping to step 7 after decoding is finished;
Step 6, reading the punching vector from a pre-stored ROM, carrying out 0-giving operation on the corresponding position P of the data to be decoded, and carrying out LDPC decoding after the code rate is increased to the target code rate R;
Step 7, completing error correction;
and step3, obtaining a mother code matrix H and a target code rate R according to the initial error rate, wherein the method comprises the following steps of:
The mother code matrix H is a check matrix with 1/2 code rate and 2/3 code rate specified by IEEE 802.16E standard, wherein the target code rate R is determined by the initial error rate obtained in the step 2, and the corresponding relation between the initial error rate and the target code rate is as follows:
when the initial error rate is 11% -9%), the target code rate R1=0.5;
When the initial error rate is [9% -8%), the target code rate R2=0.55;
When the initial error rate is 8% -6.61%), the target code rate R3=0.60;
When the initial error rate is 6.61% -5%), the target code rate R4=2/3;
when the initial error rate is [5% -4.1%), the target code rate R5=0.7;
When the initial error rate is 4.1% -3.5%), the target code rate R6=0.74;
when the initial error rate is 3.5% -2.8%), the target code rate R7 = 0.78;
when the initial error rate is 2.8% -2.4%), the target code rate R8=0.81;
when the initial error rate is 2.4% -2%), the target code rate R9=0.83;
When the initial error rate is 2% -1.86%), the target code rate R10=0.84;
The punching vector pre-stored in the ROM in the step 6 is obtained based on a grouping ordering punching algorithm, the algorithm is realized through matlab, the punching positions P with the code rate R of 0.55, 0.6, 0.66, 0.6, 0.74, 0.78, 0.81 and 0.84 of 8 code rates are generated, and then the data is pre-stored in the ROM;
The algorithm flow for LDPC decoding in step 6 is as follows:
step 6-1) initializing prior probability:
Wherein i and j represent the ith column and the jth row of the check matrix H, P i 0,Pi 1 respectively represent the probabilities of 0 and 1 of the ith bit, L (P i) represents the prior probability, q ij represents the transmission of the ith variable node to the jth check node, L (q ij) represents the log likelihood ratio information transmitted by the ith variable node, e represents the initial bit error rate obtained by bit error rate estimation, and k represents the iteration times;
Step 6-2) check node update:
Lk(rji)＝(1-2Sj)Πi′∈R(j)isgn(Lk-1(qi'j)).minLk-1(qi'j)×α (2)
Wherein R ji represents that the jth check node is transmitted to the ith variable node, L (R ji) represents log likelihood ratio information transmitted by the jth check node, S j is syndrome information, i' e R (j)/i represents variable nodes connected with the check node j except the ith variable node, and alpha is a normalization coefficient;
step 6-3) variable node update:
Lk(qij)＝L(Pi)+∑j′∈C(i)jLk(rj′i) (3)
Wherein j' e C (i)/j represents a check node connected to the i-th variable node except the check node j;
step 6-4) updating the posterior probability:
Wherein L (q i) represents variable node information, and j epsilon C (i) represents information transmitted to the variable node i by the check node j;
Step 6-5) decoding judgment:
c is the code word which is finally decoded, H is a check matrix, S is a syndrome, if the decoding result meets cH T =S, the decoding is successful, otherwise, the iterative decoding is continued, and when the maximum iterative decoding times are reached, the decoding is terminated, namely the decoding fails.
2. The QKD negotiation method based on HLS and LDPC code construction according to claim 1, wherein the puncturing in step 4 means filling the corresponding position P of the key X or Y, the position P being determined by a puncturing algorithm, comprising two steps of grouping and ordering:
Grouping: grouping all variable nodes by utilizing the concept of a recovery tree, and placing variable nodes requiring the same recovery step number into the same set;
Sequencing: and the variable nodes in the same set are ranked in front of the combination through a ranking algorithm, and when the punching position is selected, the variable nodes requiring fewer recovery steps are preferentially selected.
3. The QKD negotiation method according to claim 1, wherein the hardware architecture of the LDPC decoder performing LDPC decoding in step 6 is based on HLS generation, the LDPC decoder uses Unroll and Pipeline instructions, and in the hardware architecture generated through instruction constraint, unroll instructions are used in combination with the structural features of the check matrix H, and the parallelism of row update is designed to be m, that is, m check node update units update simultaneously; the parallelism of column update is designed as n, namely n variable node update units update simultaneously, and all loop sentences inside the instruction are expanded by combining with the Pipeline instruction.
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