CN101807928B - Recording controller and parity check code decoder - Google Patents
Recording controller and parity check code decoder Download PDFInfo
- Publication number
- CN101807928B CN101807928B CN 200910006705 CN200910006705A CN101807928B CN 101807928 B CN101807928 B CN 101807928B CN 200910006705 CN200910006705 CN 200910006705 CN 200910006705 A CN200910006705 A CN 200910006705A CN 101807928 B CN101807928 B CN 101807928B
- Authority
- CN
- China
- Prior art keywords
- signal
- group
- delegation
- reliability
- shift
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Abstract
The invention provides a parity check code decoder. The decoder comprises a verification device, a reliability generation device, a reliability updating device and a recording controller, wherein the verification device acquires a plurality of check nodes by multiplying a matrix with N rows by N-bit nodes; the reliability generation device generates a reliability index for each bit node according to a channel; the reliability updating device makes the bit nodes and the check nodes mutually iterated based on the reliability indexes so as to update N exchange results corresponding to the N rows respectively; and the recording controller comprises a separator, a quantization determination device and a quantizer; the separator separates the matrix into at least one row group and outputs N characteristic signals corresponding to the exchange results respectively according to row weight; the quantization determination device determines a displacement signal for each row group according to the characteristic signals; and the quantizer outputs the characteristic signals after the characteristic signals are quantized based on the displacement signals.
Description
Technical field
The invention relates to a kind of recording technique, refer to especially the recording mode of a kind of parity check code (parity-check code) decoder.
Background technology
Low density parity check code (low-density parity-check code, LDPC) is a kind of error correcting code.Because coding gain approaches shannon limit (Shannon limit), recently also be employed in gradually in some communication standards, for example: second generation satellite digital video broadcast (Digital Video Broadcast-Satellite version 2, DVB-S2), digital TV ground multimedia broadcasting (Digital Terrestrial Multimedia Broadcasting, DTMB) or IEEE 802.11.In receiving terminal, ldpc decoder is that each position to be decoded from passage is considered as a node (bit node), and wherein N position node must satisfy (N-K) individual condition, just can obtain correct decoding, and these conditions namely is called inspection node (check node).Check that nodes are that under zero prerequisite, ldpc decoder can make this equipotential node mutually exchange this equipotential node with these inspection nodes take iterative manner may be as 0 or 1 probability satisfying these.
And many ldpc decoders all adopt logarithm similarity ratio (Log-likelihood ratio, LLR) to simplify calculating, and are to make the node may be for 0 probability divided by may be for after 1 probability, get LLR and form the expression of a reliability.Along with the increase of iterations, a position node may be higher for the probability of a particular value (0 or 1), and the absolute value of reliability also thereby increase.But in side circuit, can only realize with limited location length, be an important topic so how to record huge reliability.Though the Chinese patent application case of China's application number 200610012000.9 proposes to record reliability according to iterations, but because the number of times of transformation range sets in advance, therefore, determine that according to iterations reliability may not be certain to meet running treatment situation at that time.
Summary of the invention
Therefore, purpose of the present invention namely can dynamically be adjusted the parity check code decoder that records the required bit length of reliability according to reliability size providing a kind of, helps to reduce the cost of realizing circuit.
So, parity check code decoder of the present invention, be applicable to receive N position to be decoded through the parity check code coding at least by a passage, comprise: a demo plant, be a node depending on each position to be decoded, and have the capable parity check matrix of N with one and be multiplied by this N node and obtain a plurality of inspection nodes; One reliability generation device produces a reliability index according to this passage for each node; One reliability updating device makes this equipotential node and these check the mutual iteration exchange message of nodes based on these reliability indexs, and exchanges to upgrade N respectively to should the capable exchange result of N with iteration each time; An and recording controller, comprise: a separator, the capable weight capable according to this N is divided into delegation's group at least with this matrix, more export N the characteristic signal of corresponding these exchange results respectively according to the capable weight of every delegation group, and the row that belongs to delegation's group has identical capable weight, and the characteristic signal that belongs to delegation's group is to represent with identical bits length; One quantizes the ruling device, according to these characteristic signals, for every delegation group determines a shift signal; And a quantizer, quantize just to export after these characteristic signals based on this shift signal.
And recording controller of the present invention, be applicable to receive N signal to be recorded at least, and have the capable matrix of N and control according to one, comprise: a separator, the capable weight capable according to this N is divided into delegation's group at least with this matrix, more export N the characteristic signal of distinguishing these signals to be recorded of correspondence according to the capable weight of every delegation group, and the row that belongs to delegation's group has identical capable weight, the characteristic signal that belongs to delegation's group is to represent with identical bits length; One quantizes the ruling device, according to these characteristic signals, for every delegation group determines a shift signal; And a quantizer, quantize just to write an internal memory after these characteristic signals based on this shift signal.
Description of drawings
Fig. 1 is a calcspar, and the preferred embodiment of parity check code decoder of the present invention is described;
Fig. 2 is a calcspar, and the recording controller of this preferred embodiment is described;
Fig. 3 is a calcspar, and the saturated counters of this preferred embodiment is described; And
Fig. 4 is a calcspar, and the displacement resolver of this preferred embodiment is described.
Embodiment
About aforementioned and other technology contents, characteristics and effect of the present invention, in the following detailed description that coordinates with reference to a graphic preferred embodiment, can clearly present.
Consult Fig. 1, the preferred embodiment of parity check code decoder 100 of the present invention is applicable to receive plural number through the position to be decoded of LDPC coding by a passage 200, comprises a reliability generation device 1, a reliability updating device 2, a demo plant 3, a recording controller 5 and an internal memory 4.And parity check code decoder 100 of the present invention is ldpc decoders.
It is a Node B that demo plant 3 is looked each position to be decoded
0, B
1, B
2..., and be that the low density parity check matrix of take a matrix size as (N-K) * N (namely have (N-K) be listed as and to have a N capable) is multiplied by N position Node B
0, B
1, B
2... B
N-1Obtain (N-K) individual inspection node C
0, C
1, C
2... C
N-K-1, (N-K)＞0 wherein.It is 1 that the m+1 of hypothesis matrix is listed as the n+1 row element, and definition checks node C
mWith the position Node B
nArq message, and same inspection node C mutually
mCan with at least two mutual arq messages of position node, m=0 wherein, 1,2... (N-K-1), n=0,1,2... (N-1).
And the exchange result of reliability updating device 2 (is reliable index Q
nWith different Index for examination Q
mn) capable to N that should matrix respectively, and be defined as follows.Reliability index Q
nDefinition be: the position Node B
nPossible probability ratio (namely may for 0 probability with may be the ratio of 1 probability) get the result after LLR.And different Index for examination Q
mnDefinition be: satisfying except checking node C
mOuter other can with the position Node B
nThe inspection node C of mutual arq message
m, be under zero prerequisite, a Node B of weighing out
nPossible probability ratio get result after LLR.Therefore, when the position Node B
nMay be higher for 0 probability, reliability index Q
nWith different Index for examination Q
mnCan be greater than 0.Otherwise, be not more than 0.And with the increase of iterations, the position Node B
nMay be for the probability of a particular value (0 or 1) be higher, reliability index Q
nWith different Index for examination Q
mnAbsolute value also larger.At this moment, if recording controller 5 directly records the exchange result without special processing, the confined space of internal memory 4 will not applied use.
Consult Fig. 2, recording controller 5 comprises that a separator 51, quantizes ruling device 50 and a quantizer 54.Reliability index Q after corresponding renewal of this N difference of separator 51 output
nCharacteristic signal.Whether this quantification ruling device 50 reaches the saturated plural shift signal that decides according to these characteristic signals.And this quantizer 54 makes these characteristic signals quantize rear (that is: divided by after shift signal) just write memory 4 based on these shift signals, shortens to reach by the quantification program purpose that records required bit length.
Matrix size according to demo plant 3 employings, but this matrix of inference has (N-K) * N element (entry) (element value is 0 or 1), usually claim the non-zero element of row wherein to add up to the row weight (row weight) of these row, claim the non-zero element of delegation wherein to add up to the capable weight (column weight) of this row.All row weights all equate and all row weights all equate if satisfy, and look matrix and are rule (regular) type; If do not satisfy, it is irregular (irregular) type.For convenience of description, this preferred embodiment will be done the example explanation with the irregular type matrix.
Separator 51 meetings be divided into G (G 〉=1) row according to the capable capable weight of this N with matrix to be organized, and more exports this N difference correspondence according to the capable weight of every delegation group and upgrades rear reliability index Q
nCharacteristic signal.And the row that belongs to delegation's group has identical capable weight, and the characteristic signal that belongs to delegation's group is to represent with identical bits length, and the increase of bit length retinue weight and become large.
This is because the capable weight of n+1 is larger, representative exist more a plurality of can with the position Node B
nThe inspection node C of mutual arq message
m, reliability index Q
nAbsolute value also can thereby increase fast.So separator 51 can give the larger bit length of characteristic signal of corresponding larger row weight, to avoid saturated too soon.For example: suppose that separator 51 is divided into G=3 row group (being the first row group, the second row group, the third line group) with matrix, the capable weight of each row group is sequentially 3,4,11.So, separator 51 can represent to belong to the characteristic signal of the first row group with the A=6 bit length, represent to belong to the characteristic signal of the second row group with the B=7 bit length, and represent to belong to the characteristic signal of the third line group with the C=9 bit length.
Because recording controller 5 is to record in the same manner reliability index Q after the renewal of every delegation group
nSo, only explain with the first row group herein.After separator 51 determines to represent to belong to the characteristic signal of the first row group with the A=6 bit length, each characteristic signal is divided into one show the symbol indication (1) of its symbol (sign) and the absolute value signal (5) of its absolute value of demonstration.That is to say, if the absolute value of characteristic signal is not less than (2
5-1), can export absolute value signal (value is 11111); If less than (2
5-1), can be take 5 bit lengths equivalence is used as absolute value signal (for example: characteristic signal is as 18, and absolute value signal is 10010).
Determine that for every delegation group one presents the shift signal of 2 power side according to these absolute value signal and quantize ruling device 50.And quantize ruling device 50 have respectively to should G=3 3 saturated counters 52 and 3 displacement resolvers 53 of capable group.The saturated counters 52 of corresponding the first row group can judge whether the absolute value signal that belongs to the first row group reaches saturated (namely value is 11111) and export a saturation count, and it represents the reliability index Q that reaches capacity in the rear the first row group of iteration exchange each time
nNumber.Then, the displacement resolver 53 of corresponding the first row group can further decide shift signal according to saturation count.And (that is: divided by after shift signal) ability write memory 4 after quantizer 54 can make the absolute value signal that belongs to the first row group quantize based on shift signal, so quantizer 54 can be the updating memory of iteration exchange each time 4 contents.In addition, recording controller 5 also comprises a symbol buffer 55, records each symbol indication, for the symbol of identification internal memory 4 contents.Certainly, in another embodiment, also can ellipsis buffer 55, directly symbol is indicated write memory 4.
Consult Fig. 3 and Fig. 4, in more detail, each saturated counters 52 has a judging unit 521, a multi-task unit 522, an adder unit 523 and a saturated buffer unit 524, and each displacement resolver 53 has a judging unit 531, a multi-task unit 532, displacement statistic unit 533 and a shift cache unit 534.Each shift cache unit 534 produces these reliability indexs Q with reliability generation device 1
nAnd the replacement shift signal is a default value, and each saturated buffer unit 524 is with each these reliability indexs Q that upgrades of reliability updating device 2
nAnd the replacement saturation count is zero.
For the first row group, be after zero in saturated buffer unit 524 replacement saturation count, judging unit 521 just can begin to compare the absolute value signal that belongs to the first row group and whether equal a saturation value (namely 11111), if equal, multi-task unit 522 can output 1 value; If be not equal to, multi-task unit 522 can output 0 value.Then, adder unit 523 can add this output the last saturation count of saturated buffer unit 524, for saturated buffer unit 524 with addition result as saturation count after upgrading.Then, judging unit 521 continues next absolute value signal that belongs to the first row group is compared again, until the absolute value signal that all belong to the first row group is completed in comparison.
Then, whether the saturation count that the judging unit 531 of displacement resolver 53 can the judgement comparison be completed gained greater than a critical value, and impels multi-task unit 532 output one progression signals.Greater than critical value, multi-task unit 532 is chosen a shift amount and is used as the progression signal when saturation count; When being not more than, choosing 1 and be used as the progression signal.After iteration exchange for the first time, displacement statistic unit 533 can be used as output with the default value of shift signal with the progression signal times.And in the exchange of subsequently iteration, the shift signal that displacement statistic unit 533 can get iteration clearing house before the progression signal times.And shift cache unit 534 can be with the output of displacement statistic unit 533 as the shift signal after upgrading.
Lift an example start of displacement resolver 53 is described, and suppose that the default value of shift signal is 2
-2After iteration exchange for the first time, if judging unit 531 judges saturation count greater than critical value, multi-task unit 532 will be chosen a shift amount 2
2Be used as the progression signal, for displacement statistic unit 533, it be multiplied by the default value 2 of shift signal
-2, be 1 and make shift cache unit 534 upgrade shift signal.This is representing that also quantizer 54 can be directly with absolute value signal write memory 4.
And after iteration exchange for the second time, if judging unit 531 judges again saturation count greater than critical value, multi-task unit 532 will be chosen a shift amount 2
2, before can being multiplied by it, the statistic unit 533 that then is shifted once reaches the shift signal (value is 1) for gained, be 2 and make shift cache unit 534 upgrade shift signal
2Then, quantizer 54 can (value be 2 divided by upgrading the backward shift signal with absolute value signal
2) after write memory 4.
Although it should be noted that this preferred embodiment is that to have the irregular type matrixes of 3 row groups be example, row group number is not limited to this.Certainly, also visual regular pattern composite matrix is a special case wherein, and organizing at once number is 1.And, be write memory 4 again after symbol indication and absolute value signal although separator 51 is distinguishing characteristic signals.But in another embodiment, also can omit separator 51, directly in sign (sign) mode, characteristic signal be write.For example: when characteristic signal is-1, write 11111; When characteristic signal is 1, write 00001.
Moreover in the present embodiment, these shift signals of determining of displacement resolvers 53 are (for example: 2 to present 2 power side
X), and quantizer 54 is ability write memories 4 after making absolute value signal divided by shift signal.But in other is used, also can change shift signal into and refer to that (for example: X), and quantizer 54 is divided by 2 to power side's index
X, wherein X equals the value of shift signal.
Even more noteworthy, for these displacement resolvers 53, it is identical that the selected critical value of each judging unit 531 does not need shift amount identical and that each multi-task unit 532 is selected not need yet, and can adjust with the capable weight of corresponding row group.Even need not limit the shift signal that each shift cache unit 534 has identical default value, can set different default values according to passage 200 quality, and passage 200 quality be better, default value is larger.This is because passage 200 quality are better, the position Node B
nNot disturbed by passage 200, it is that the probability of a particular value is also just higher.
In addition, this preferred embodiment is based on the reliability index Q that reliability updating device 2 each iteration clearing houses get
nCome record, but the reliability index Q that also can produce based on reliability generation device 1 again
nCome record.And also can make into based on the different Index for examination Q that produces in iterative process in another embodiment,
mnCome record.
Although and this preferred embodiment is built-in memory 4 records with parity check code decoder 100, can be also to write an external memory 4.And recording controller 5 is independently to go out parity check code decoder 100.
In sum, parity check code decoder 100 of the present invention decides shift signal according to the saturation count of iteration exchange each time, and with absolute value signal divided by shift signal after write memory 4, record required bit length so can effectively shorten, and help to reduce the cost of realizing circuit, therefore really can reach purpose of the present invention.
The above person of thought, it is only preferred embodiment of the present invention, when not limiting scope of the invention process with this, the simple equivalence of namely generally doing according to the present patent application the scope of the claims and invention description content changes and modifies, and all still remains within the scope of the patent.
Claims (14)
1. a parity check code decoder, be applicable to receive N position to be decoded through the parity check code coding at least by a passage, comprises:
One demo plant, be a node depending on each position to be decoded, and have the capable parity check matrix of N with one and be multiplied by this N position node and obtain a plurality of inspection nodes, and with this have the capable parity check matrix of N be multiplied by upgrade after a position node obtain upgrading rear inspection node;
One reliability generation device is that each node produces a reliability index according to the quality of this passage, and the definition of wherein said reliability index is: institute's rheme node may for 0 probability with may be take the logarithm result after the similarity ratio of the ratio of 1 probability;
one reliability updating device, make this equipotential node and the mutual iteration exchange message of these inspection nodes based on described reliability index, and exchange to upgrade N respectively to should the capable exchange result of N with iteration each time, wherein each exchange result has described reliability index or at least one different Index for examination, the definition of described different Index for examination is: check that other of node can be under zero prerequisite with the inspection node of the mutual arq message of institute's rheme node except one satisfying, the institute's rheme node of weighing out may for 0 probability with may be take the logarithm result after the similarity ratio of the ratio of 1 probability, and
One recording controller comprises:
One separator, the capable weight capable according to this N is divided into G (G 〉=1) row group with this matrix, more export N the characteristic signal of corresponding these exchange results respectively according to the capable weight of every delegation group, and the row that belongs to delegation's group has identical capable weight, and the characteristic signal that belongs to delegation's group is to represent with identical bits length;
One quantizes the ruling device, according to these characteristic signals, for every delegation group determines a shift signal; And
One quantizer quantizes just to export after these characteristic signals based on this shift signal,
Wherein, this quantification ruling device has:
G the saturated counters of distinguishing corresponding every delegation group, whether the characteristic signal that judgement belongs to delegation's group reaches saturated and exports a saturation count; And
G the displacement resolver of distinguishing corresponding every delegation group decides this shift signal according to this saturation count.
2. parity check code decoder as claimed in claim 1, wherein, each saturated counters has:
One saturated buffer unit upgrades these exchange results this saturation count of resetting with this reliability updating device at every turn;
One judging unit, whether the characteristic signal that comparison belongs to every delegation group reaches saturated;
One multi-task unit is according to comparison result output one particular value of this judging unit; And
One adder unit adds last saturation count with this particular value, exports the rear saturation count of this renewal for this saturated buffer unit.
3. parity check code decoder as claimed in claim 1, wherein, each displacement resolver has:
One shift cache unit, producing these reliability indexs this shift signal of resetting with this reliability generation device is a default value;
One judging unit judges that whether this saturation count is greater than a critical value;
One multi-task unit is based on the judged result output one progression signal of this judging unit; And
One displacement statistic unit with last shift signal, is exported this renewal backward shift signal for this shift cache unit with this progression signal times.
4. parity check code decoder as claimed in claim 1, wherein, this separator is that after each characteristic signal is divided into a symbol indication and that shows its symbol and shown the absolute value signal of its absolute value, this quantification ruling device ability determines this shift signal based on the absolute value signal that belongs to every delegation group for every delegation group.
5. parity check code decoder as claimed in claim 1, wherein, the shift signal that this G displacement resolver determines is to present 2 power side, and this quantizer is to belong to characteristic signal with delegation's group divided by the corresponding displaced signal.
6. parity check code decoder as claimed in claim 1, wherein, the shift signal that this G displacement resolver determines is to present power side's index, and this quantizer is to belong to characteristic signal with delegation's group divided by 2
x, and x equals the value of corresponding displaced signal.
7. parity check code decoder as claimed in claim 3, wherein, each shift cache unit is adjusted the default value of this shift signal based on this passage.
8. recording controller that is used for parity check code decoder, be applicable to receive N signal to be recorded at least, and have the capable parity check matrix of N and control according to one, wherein, described N signal to be recorded is that described parity check code decoder is processed N the position to be decoded through the parity check code coding that receives and N the capable exchange result of the corresponding N of difference after the renewal that generates, and described recording controller comprises:
One separator, the capable weight capable according to this N is divided into G (G 〉=1) row group with this matrix, more export the characteristic signal of N respectively corresponding these signals to be recorded according to the capable weight of every delegation group, and the row that belongs to delegation's group has identical capable weight, and the characteristic signal that belongs to delegation's group is to represent with identical bits length;
One quantizes the ruling device, according to these characteristic signals, for every delegation group determines a shift signal; And
One quantizer quantizes just to write an internal memory after these characteristic signals based on this shift signal,
Wherein, this quantification ruling device has:
G the saturated counters of distinguishing corresponding every delegation group, whether the characteristic signal that judgement belongs to delegation's group reaches saturated and exports a saturation count; And
G the displacement resolver of distinguishing corresponding every delegation group decides this shift signal according to this saturation count.
9. recording controller as claimed in claim 8, wherein, each saturated counters has:
One saturated buffer unit upgrades these exchange results this saturation count of resetting with this reliability updating device at every turn;
One judging unit, whether the characteristic signal that comparison belongs to every delegation group reaches saturated;
One multi-task unit is according to comparison result output one particular value of this judging unit; And
One adder unit adds last saturation count with this particular value, exports the rear saturation count of this renewal for this saturated buffer unit.
10. recording controller as claimed in claim 8, wherein, each displacement resolver has:
One shift cache unit, producing these reliability indexs this shift signal of resetting with this reliability generation device is a default value;
One judging unit judges that whether this saturation count is greater than a critical value;
One multi-task unit is based on the judged result output one progression signal of this judging unit; And
One displacement statistic unit with last shift signal, is exported this renewal backward shift signal for this shift cache unit with this progression signal times.
11. recording controller as claimed in claim 8, wherein, this separator is that after each characteristic signal is divided into a symbol indication and that shows its symbol and shown the absolute value signal of its absolute value, this quantification ruling device ability determines this shift signal based on the absolute value signal that belongs to every delegation group for every delegation group.
12. recording controller as claimed in claim 8, wherein, this G the shift signal that determine of displacement resolver is to present 2 power side, and this quantizer is to belong to characteristic signal with delegation's group divided by the corresponding displaced signal.
13. recording controller as claimed in claim 8, wherein, this G the shift signal that determine of displacement resolver is to present power side's index, and this quantizer is to belong to characteristic signal with delegation's group divided by 2
x, and x equals the value of corresponding displaced signal.
14. recording controller as claimed in claim 10, wherein, each shift cache unit is adjusted the default value of this shift signal based on this passage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910006705 CN101807928B (en) | 2009-02-13 | 2009-02-13 | Recording controller and parity check code decoder |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910006705 CN101807928B (en) | 2009-02-13 | 2009-02-13 | Recording controller and parity check code decoder |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101807928A CN101807928A (en) | 2010-08-18 |
| CN101807928B true CN101807928B (en) | 2013-06-05 |
Family
ID=42609560
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200910006705 Active CN101807928B (en) | 2009-02-13 | 2009-02-13 | Recording controller and parity check code decoder |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101807928B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| SG10201707007QA (en) | 2015-10-13 | 2017-09-28 | Huawei Tech Co Ltd | Decoding device and method and signal transmission system |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1852029A (en) * | 2006-05-26 | 2006-10-25 | 清华大学 | Low-density odd-parity check-code decoding method adopting uniform quantizing variable range |
| CN101034892A (en) * | 2006-03-06 | 2007-09-12 | 西门子（中国）有限公司 | LDPC code generation method and device using the LDPC code |
| CN101106383A (en) * | 2007-08-13 | 2008-01-16 | 清华大学 | A low density checksum decoding method |
| CN101273532A (en) * | 2005-09-26 | 2008-09-24 | 日本电气株式会社 | Decoding device, and receiving device |
| CN101355366A (en) * | 2008-06-13 | 2009-01-28 | 华为技术有限公司 | Method and apparatus for decoding low density parity check code |
-
2009
- 2009-02-13 CN CN 200910006705 patent/CN101807928B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101273532A (en) * | 2005-09-26 | 2008-09-24 | 日本电气株式会社 | Decoding device, and receiving device |
| CN101034892A (en) * | 2006-03-06 | 2007-09-12 | 西门子（中国）有限公司 | LDPC code generation method and device using the LDPC code |
| CN1852029A (en) * | 2006-05-26 | 2006-10-25 | 清华大学 | Low-density odd-parity check-code decoding method adopting uniform quantizing variable range |
| CN101106383A (en) * | 2007-08-13 | 2008-01-16 | 清华大学 | A low density checksum decoding method |
| CN101355366A (en) * | 2008-06-13 | 2009-01-28 | 华为技术有限公司 | Method and apparatus for decoding low density parity check code |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101807928A (en) | 2010-08-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103888148B (en) | A kind of LDPC code Hard decision decoding method of dynamic threshold bit reversal | |
| US7853854B2 (en) | Iterative decoding of a frame of data encoded using a block coding algorithm | |
| US8607118B2 (en) | Iterative decoding method and apparatus | |
| CA2457420C (en) | Bit labeling for amplitude phase shift constellation used with low density parity check (ldpc) codes | |
| CN101141133B (en) | Method of encoding structured low density check code | |
| US8046658B2 (en) | Method and device for decoding blocks encoded with an LDPC code | |
| JP5506878B2 (en) | Parity check matrix generation method for low density parity check code | |
| CN105247808B (en) | The system and method being decoded using later period reliability information | |
| US7949932B2 (en) | Strengthening parity check bit protection for array-like LDPC codes | |
| CN102412847A (en) | Method and apparatus for decoding low density parity check code using united node processing | |
| CN1612486A (en) | Method and system for providing short block length low density parity check (LDPC) codes | |
| CN100592639C (en) | Low density parity check coding method, device and parity check matrix generating method | |
| US10848182B2 (en) | Iterative decoding with early termination criterion that permits errors in redundancy part | |
| US9219501B2 (en) | LDPC encoding/decoding method and device using same | |
| US11184034B2 (en) | Method and device for decoding staircase code, and storage medium | |
| Fontaine et al. | How Reed-Solomon codes can improve steganographic schemes | |
| CN107615666A (en) | The interpretation method and decoding equipment of LDPC shortened codes | |
| CN108206722B (en) | High-bit-rate data sending method and device | |
| US7792135B2 (en) | Device and method of constructing generation matrix for linear block coding, coding device and decoding device using the generation matrix | |
| CN101807928B (en) | Recording controller and parity check code decoder | |
| CN111525931B (en) | LDPC decoder, LDPC decoding method, storage medium and electronic apparatus | |
| US8402340B2 (en) | Parity-check-code decoder and recording controller | |
| CN101777920A (en) | Coding method and coding and decoding device of low-density parity check code | |
| JP2009182421A (en) | Decoding method and decoding device | |
| CN113131947B (en) | Decoding method, decoder and decoding device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |