CN101807928A - Recording controller and parity check code decoder - Google Patents
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Abstract
The invention provides a parity check code decoder. The decoder comprises a verification device, a reliability generation device, a reliability updating device and a recording controller, wherein the verification device acquires a plurality of check nodes by multiplying a matrix with N rows by N-bit nodes; the reliability generation device generates a reliability index for each bit node according to a channel; the reliability updating device makes the bit nodes and the check nodes mutually iterated based on the reliability indexes so as to update N exchange results corresponding to the N rows respectively; and the recording controller comprises a separator, a quantization determination device and a quantizer; the separator separates the matrix into at least one row group and outputs N characteristic signals corresponding to the exchange results respectively according to row weight; the quantization determination device determines a displacement signal for each row group according to the characteristic signals; and the quantizer outputs the characteristic signals after the characteristic signals are quantized based on the displacement signals.
Description
Technical field
The invention relates to a kind of recording technique, be meant the recording mode of a kind of parity check code (parity-check code) decoder especially.
Background technology
(low-density parity-check code LDPC) is a kind of error correcting code to low density parity check code.Because coding gain approaches shannon limit (Shannon limit), recently also be employed in some communication standards gradually, for example: second generation satellite digital video broadcast (Digital Video Broadcast-Satellite version 2, DVB-S2), digital TV ground multimedia broadcasting (Digital Terrestrial Multimedia Broadcasting, DTMB) or IEEE 802.11.In receiving terminal, ldpc decoder is that each position to be decoded of self-channel in the future is considered as a node (bit node), and wherein N position node must satisfy (N-K) individual condition, just can obtain correct decoding, and these conditions promptly is called inspection node (check node).Check that nodes are that ldpc decoder can make this equipotential node exchange this equipotential node with these inspection nodes mutually with iterative manner may be 0 or 1 probability under zero the prerequisite satisfying these.
And many ldpc decoders all adopt logarithm similarity ratio (Log-likelihood ratio LLR) simplifies calculating, and be make a node may for 0 probability divided by may be for after 1 the probability, get LLR and form the expression of a reliability.Along with the increase of iterations, a position node may be high more for the probability of a particular value (0 or 1), and the absolute value of reliability also thereby increase.But in side circuit, can only realize with limited bit length, be an important topic so how to write down huge reliability.Though the Chinese patent application case of China's application number 200610012000.9 proposes to write down reliability according to iterations, but because the number of times of transformation range configures in advance, therefore, determine that according to iterations reliability may not be certain to meet running treatment situation at that time.
Summary of the invention
Therefore, purpose of the present invention promptly in that a kind of parity check code decoder that can dynamically adjust the required bit length of record reliability according to the reliability size is provided, helps to reduce the cost of realizing circuit.
So, parity check code decoder of the present invention, be applicable to by a passage and receive N position to be decoded at least through the parity check code coding, comprise: a demo plant, looking each position to be decoded is a node, and has the capable parity check matrix of N with one and be multiplied by this N node and obtain a plurality of inspection nodes; One reliability generation device produces a reliability index according to this channel for each node; One reliability updating device makes this equipotential node and these check the mutual iteration exchange message of nodes based on these reliable indicator, and exchanges with iteration each time and to upgrade N respectively to should the capable exchange result of N; An and recording controller, comprise: a separator, the capable weight capable according to this N is divided into delegation's group at least with this matrix, more export N corresponding respectively these exchanges result's characteristic signal according to the capable weight of each row group, and the row that belongs to delegation's group has identical capable weight, and the characteristic signal that belongs to delegation's group is to represent with identical bits length; One quantizes the ruling device, according to these characteristic signals, for each row group determines a shift signal; And a quantizer, quantize just to export behind these characteristic signals based on this shift signal.
And recording controller of the present invention, be applicable to and receive N signal to be recorded at least, and have the capable matrix of N and control according to one, comprise: a separator, the capable weight capable according to this N is divided into delegation's group at least with this matrix, more export N the characteristic signal of distinguishing corresponding these signals to be recorded according to capable weight of each row group, and the row that belongs to delegation's group has identical capable weight, the characteristic signal that belongs to delegation's group is to represent with identical bits length; One quantizes the ruling device, according to these characteristic signals, for each row group determines a shift signal; And a quantizer, quantize just to write an internal memory behind these characteristic signals based on this shift signal.
Description of drawings
Fig. 1 is a calcspar, and the preferred embodiment of parity check code decoder of the present invention is described;
Fig. 2 is a calcspar, and the recording controller of this preferred embodiment is described;
Fig. 3 is a calcspar, and the saturated counters of this preferred embodiment is described; And
Fig. 4 is a calcspar, and the displacement resolver of this preferred embodiment is described.
Embodiment
About aforementioned and other technology contents, characteristics and effect of the present invention, in the following detailed description that cooperates with reference to a graphic preferred embodiment, can clearly present.
Consult Fig. 1, the preferred embodiment of parity check code decoder 100 of the present invention is applicable to by a passage 200 and receives the to be decoded position of plural number through the LDPC coding, comprises a reliability generation device 1, a reliability updating device 2, a demo plant 3, a recording controller 5 and an internal memory 4.And parity check code decoder 100 of the present invention is ldpc decoders.
It is a Node B that demo plant 3 is looked each position to be decoded
0, B
1, B
2..., and be to be multiplied by N Node B with a matrix size for the low density parity check matrix of (N-K) * N (promptly have (N-K) be listed as and to have a N capable)
0, B
1, B
2... B
N-1Obtain (N-K) individual inspection node C
0, C
1, C
2... C
N-K-1, (N-K)＞0 wherein.It is 1 that the m+1 of hypothesis matrix is listed as the n+1 row element, and then node C is checked in definition
mWith the position Node B
nArq message, and same inspection node C mutually
mCan with at least two mutual arq messages of position node, m=0 wherein, 1,2... (N-K-1), n=0,1,2... (N-1).
And the exchange result of reliability updating device 2 (is reliable index Q
nWith different inspection index Q
Mn) capable to N that should matrix respectively, and be defined as follows.Reliability index Q
nDefinition be: the position Node B
nPossible probability ratio (promptly may for 0 probability with may be the ratio of 1 probability) get the result behind the LLR.And different inspection index Q
MnDefinition be: satisfying except checking node C
mOuter other can with the position Node B
nThe inspection node C of mutual arq message
M 'Be under zero the prerequisite, a Node B of weighing out
nPossible probability ratio get result behind the LLR.Therefore, when the position Node B
nMay be higher for 0 probability, reliability index Q
nWith different inspection index Q
MnCan be greater than 0.Otherwise, be not more than 0.And with the increase of iterations, the position Node B
nMay be for the probability of a particular value (0 or 1) be high more, reliability index Q
nWith different inspection index Q
MnAbsolute value also big more.At this moment, recording controller 5 is if directly write down the exchange result without special processing, and the confined space of internal memory 4 will not applied use.
Consult Fig. 2, recording controller 5 comprises that a separator 51, quantizes a ruling device 50 and a quantizer 54.N corresponding respectively back reliability index Q that upgrades of these separator 51 outputs
nCharacteristic signal.Whether this quantification ruling device 50 reaches the saturated plural shift signal that decides according to these characteristic signals.And this quantizer 54 makes these characteristic signals quantize just write memory 4 of back (that is: divided by behind the shift signal) based on these shift signals, to reach the purpose that shortens the required bit length of record by the quantification program.
Matrix size according to demo plant 3 employings, but this matrix of inference has (N-K) * N element (entry) (element value is 0 or 1), usually claim non-0 element of row wherein to add up to the row weight (row weight) of these row, claim non-0 element of delegation wherein to add up to the capable weight (column weight) of this row.All row weights all equate and all row weights all equate if satisfy, and then look matrix and are rule (regular) type; If do not satisfy, then be irregular (irregular) type.For convenience of description, this preferred embodiment will be done the example explanation with the irregular type matrix.
This is because the capable weight of n+1 is big more, representative exist a plurality of more can with the position Node B
nThe inspection node C of mutual arq message
m, reliability index Q
nAbsolute value also can thereby increase fast.So separator 51 can give the bigger bit length of characteristic signal of corresponding bigger capable weight, to avoid saturated too soon.For example: suppose that separator 51 is divided into G=3 row group (i.e. the first row group, the second row group, the third line group) with matrix, the capable weight of each row group is 3,4,11 in regular turn.So, separator 51 can represent to belong to the characteristic signal of the first row group with the A=6 bit length, represents to belong to the characteristic signal of the second row group with the B=7 bit length, and represents to belong to the characteristic signal of the third line group with the C=9 bit length.
Because recording controller 5 is to write down reliability index Q after renewal of each row group in the same manner
nSo, only do explanation herein with the first row group.Separator 51 decisions are represented to belong to the A=6 bit length after the characteristic signal of the first row group, each characteristic signal are divided into the symbol of its symbol of demonstration (sign) and are indicated (1) and one to show the absolute value signal (5) of its absolute value.That is to say, if the absolute value of characteristic signal is not less than (2
5-1), can export absolute value signal (value is 11111); If less than (2
5-1), can be with 5 bit lengths equivalence is used as absolute value signal (for example: characteristic signal is 18, and absolute value signal is 10010).
Come to determine one to present the shift signal of 2 power power according to these absolute value signal and quantize ruling device 50 for each row group.And quantize ruling device 50 have respectively to should G=3 3 saturated counters 52 and 3 displacement resolvers 53 of capable group.The saturated counters 52 of the corresponding first row group can judge whether the absolute value signal that belongs to the first row group reaches saturated (promptly value is 11111) and export a saturation count, and it represents the reliability index Q that reaches capacity in the first row group of the back of iteration exchange each time
nNumber.Then, the displacement resolver 53 of the corresponding first row group can further decide shift signal according to saturation count.And quantizer 54 can make the absolute value signal that belongs to the first row group quantize just write memory 4 of back (that is: divided by behind the shift signal) based on shift signal, so quantizer 54 can be the updating memory of iteration exchange each time 4 contents.In addition, recording controller 5 also comprises a symbol buffer 55, writes down each symbol indication, for the symbol of identification internal memory 4 contents.Certainly, in another embodiment, also can ellipsis buffer 55, directly symbol is indicated write memory 4.
Consult Fig. 3 and Fig. 4, in more detail, each saturated counters 52 has a judging unit 521, a multi-task unit 522, an adder unit 523 and a saturated buffer unit 524, and each displacement resolver 53 has a judging unit 531, a multi-task unit 532, a displacement statistic unit 533 and a shift cache unit 534.Each shift cache unit 534 produces these reliability indexs Q with reliability generation device 1
nAnd the replacement shift signal is a default value, and each saturated buffer unit 524 is with reliability updating device 2 each these reliability indexs Q that upgrade
nAnd the replacement saturation count is zero.
For the first row group, in saturated buffer unit 524 replacement saturation count is after zero, judging unit 521 just can begin to compare the absolute value signal that belongs to the first row group and whether equal a saturation value (promptly 11111), if equal, multi-task unit 522 can be worth in output 1; If be not equal to, multi-task unit 522 can output 0 value.Then, adder unit 523 can add this output the last saturation count of saturated buffer unit 524, for saturated buffer unit 524 with addition result as upgrading the back saturation count.Then, judging unit 521 continues next absolute value signal that belongs to the first row group is compared again, finishes the absolute value signal that all belong to the first row group up to comparison.
Then, whether the judging unit 531 of displacement resolver 53 can judge saturation count that comparison finishes gained greater than a critical value, and impels multi-task unit 532 outputs one progression signal.When saturation count greater than critical value, multi-task unit 532 is chosen a shift amount and is used as the progression signal; When being not more than, choosing 1 and be used as the progression signal.After the iteration exchange first time, displacement statistic unit 533 can be used as output with the default value of shift signal with the progression signal times.And in iteration exchange subsequently, displacement statistic unit 533 is understood the shift signal that the former iteration clearing house of progression signal times is got.And shift cache unit 534 can be with the output of displacement statistic unit 533 as the shift signal after upgrading.
Lift an example start of displacement resolver 53 is described, and suppose that the default value of shift signal is 2
-2After the iteration exchange first time, if judging unit 531 is judged saturation count greater than critical value, multi-task unit 532 will be chosen a shift amount 2
2Be used as the progression signal, it be multiplied by the default value 2 of shift signal for displacement statistic unit 533
-2, be 1 and make shift cache unit 534 upgrade shift signal.This is also representing quantizer 54 meetings directly with absolute value signal write memory 4.
And after the iteration exchange for the second time, if judging unit 531 is judged saturation count again greater than critical value, multi-task unit 532 will be chosen a shift amount 2
2, the statistic unit 533 that is shifted then can be multiplied by the shift signal (value is 1) of a preceding iteration gained with it, is 2 and make shift cache unit 534 upgrade shift signal
2Then, quantizer 54 can (value be 2 divided by upgrading the backward shift signal with absolute value signal
2) after write memory 4.
Though it should be noted that this preferred embodiment is is example with irregular type matrixes with 3 row groups, row group number is not limited thereto.Certainly, also visual regular pattern composite matrix is a special case wherein, and organizing number at once is 1.And, be write memory 4 again after symbol indication and the absolute value signal though separator 51 is distinguishing characteristic signals.But in another embodiment, also can omit separator 51, directly characteristic signal be write in sign (sign) mode.For example:, write 11111 when characteristic signal is-1; When characteristic signal is 1, write 00001.
Moreover in the present embodiment, these shift signals of being determined of displacement resolvers 53 are (for example: 2 to present 2 power power
X), and quantizer 54 is ability write memories 4 after making absolute value signal divided by shift signal.But in other is used, also can change shift signal into and be meant that (for example: X), and quantizer 54 is divided by 2 to power power index
X, wherein X equals the value of shift signal.
Even more noteworthy, for these displacement resolvers 53, each judging unit 531 selected critical values do not need identical and each multi-task unit 532 selected shift amounts do not need identically yet, can adjust with the capable weight of corresponding row group.Even need not limit the shift signal that each shift cache unit 534 has identical default value, can set different default values according to channel 200 quality, and channel 200 quality be good more, default value is big more.This is because channel 200 quality are good more, the position Node B
nNot disturbed by passage 200, it is that the probability of a particular value is also just high more.
In addition, this preferred embodiment is based on the reliability index Q that reliability updating device 2 each iteration clearing houses get
nCome record, but the reliability index Q that also can be produced based on reliability generation device 1 again
nCome record.And also can make in another embodiment, based on the different inspection index Q that is produced in the iterative process
MnCome record.
Though and this preferred embodiment is built-in internal memory 4 records with parity check code decoder 100, also can be to write an external memory 4.And recording controller 5 is independently to go out parity check code decoder 100.
In sum, parity check code decoder 100 of the present invention decides shift signal according to the saturation count of iteration exchange each time, and with absolute value signal divided by shift signal after write memory 4, so can effectively shorten the required bit length of record, and help to reduce the cost of realizing circuit, so can reach purpose of the present invention really.
The above person of thought, it only is preferred embodiment of the present invention, when not limiting scope of the invention process with this, promptly the simple equivalent of being done according to the present patent application claim and invention description content generally changes and modifies, and all still belongs in the scope that patent of the present invention contains.
Claims (18)
1. a parity check code decoder is applicable to by a passage to receive N position to be decoded through the parity check code coding at least, comprises:
One demo plant, looking each position to be decoded is a node, and has the capable parity check matrix of N with one and be multiplied by this N node and obtain a plurality of inspection nodes;
One reliability generation device produces a reliability index according to this channel for each node;
One reliability updating device makes this equipotential node and these check the mutual iteration exchange message of nodes based on these reliable indicator, and exchanges with iteration each time and to upgrade N respectively to should the capable exchange result of N; And
One recording controller comprises:
One separator, the capable weight capable according to this N is divided into G (G 〉=1) row group with this matrix, more export N corresponding respectively these exchanges result's characteristic signal according to the capable weight of each row group, and the row that belongs to delegation's group has identical capable weight, and the characteristic signal that belongs to delegation's group is to represent with identical bits length;
One quantizes the ruling device, according to these characteristic signals, for each row group determines a shift signal; And
One quantizer quantizes just to export behind these characteristic signals based on this shift signal.
2. parity check code decoder as claimed in claim 1, wherein, this quantification ruling device has:
The saturated counters of G respectively corresponding each row group judges whether the characteristic signal that belongs to delegation's group reaches saturated and export a saturation count; And
The displacement resolver of G corresponding respectively each row group decides this shift signal according to this saturation count.
3. parity check code decoder as claimed in claim 2, wherein, each saturated counters has:
One saturated buffer unit upgrades these exchanges result this saturation count of resetting with this reliability updating device at every turn;
Whether the characteristic signal that one judging unit, comparison belong to each row group reaches saturated;
One multi-task unit is exported a particular value according to the comparison result of this judging unit; And
One adder unit adds last saturation count with this particular value, exports this renewal back saturation count for this saturated buffer unit.
4. parity check code decoder as claimed in claim 2, wherein, each displacement resolver has:
One shift cache unit, producing these reliable indicator this shift signal of resetting with this reliability generation device is a default value;
One judging unit judges that whether this saturation count is greater than a critical value;
One multi-task unit is exported a progression signal based on the judged result of this judging unit; And
One displacement statistic unit with last shift signal, is exported this renewal backward shift signal for this shift cache unit with this progression signal times.
5. parity check code decoder as claimed in claim 1, wherein, this separator is after each characteristic signal is divided into a symbol indication and that shows its symbol and shown the absolute value signal of its absolute value, and it is that each row is organized and determined this shift signal that this quantifications ruling device just comes based on the absolute value signal that belongs to each row group.
6. parity check code decoder as claimed in claim 1, wherein, each exchange result that this reliability updating device upgrades with each iteration clearing house has a reliability index.
7. parity check code decoder as claimed in claim 1, wherein, each exchange result that this reliability updating device upgrades with each iteration clearing house has at least one different inspection index.
8. parity check code decoder as claimed in claim 2, wherein, this G displacement shift signal that resolver determined is to present 2 power power, and this quantizer is to belong to characteristic signal with delegation's group divided by the corresponding displaced signal.
9. parity check code decoder as claimed in claim 2, wherein, this G displacement shift signal that resolver determined is to present power power index, and this quantizer is to belong to characteristic signal with delegation's group divided by 2
x, and x equals the value of corresponding displaced signal.
10. parity check code decoder as claimed in claim 4, wherein, each shift cache unit is adjusted the default value of this shift signal based on this channel.
11. a recording controller is applicable to receive at least N signal to be recorded, and has the capable matrix of N according to one and control, and comprising:
One separator, the capable weight capable according to this N is divided into G (G 〉=1) row group with this matrix, more export the characteristic signal of N respectively corresponding these signals to be recorded according to the capable weight of each row group, and the row that belongs to delegation's group has identical capable weight, and the characteristic signal that belongs to delegation's group is to represent with identical bits length;
One quantizes the ruling device, according to these characteristic signals, for each row group determines a shift signal; And
One quantizer quantizes just to write an internal memory behind these characteristic signals based on this shift signal.
12. recording controller as claimed in claim 11, wherein, this quantification ruling device has:
The saturated counters of G respectively corresponding each row group judges whether the characteristic signal that belongs to delegation's group reaches saturated and export a saturation count; And
The displacement resolver of G corresponding respectively each row group decides this shift signal according to this saturation count.
13. recording controller as claimed in claim 12, wherein, each saturated counters has:
One saturated buffer unit upgrades these exchanges result this saturation count of resetting with this reliability updating device at every turn;
Whether the characteristic signal that one judging unit, comparison belong to each row group reaches saturated;
One multi-task unit is exported a particular value according to the comparison result of this judging unit; And
One adder unit adds last saturation count with this particular value, exports this renewal back saturation count for this saturated buffer unit.
14. recording controller as claimed in claim 12, wherein, each displacement resolver has:
One shift cache unit, producing these reliable indicator this shift signal of resetting with this reliability generation device is a default value;
One judging unit judges that whether this saturation count is greater than a critical value;
One multi-task unit is exported a progression signal based on the judged result of this judging unit; And
One displacement statistic unit with last shift signal, is exported this renewal backward shift signal for this shift cache unit with this progression signal times.
15. recording controller as claimed in claim 11, wherein, this separator is after each characteristic signal is divided into a symbol indication and that shows its symbol and shown the absolute value signal of its absolute value, and it is that each row is organized and determined this shift signal that this quantifications ruling device just comes based on the absolute value signal that belongs to each row group.
16. recording controller as claimed in claim 12, wherein, this G displacement shift signal that resolver determined is to present 2 power power, and this quantizer is to belong to characteristic signal with delegation's group divided by the corresponding displaced signal.
17. recording controller as claimed in claim 12, wherein, this G displacement shift signal that resolver determined is to present power power index, and this quantizer is to belong to characteristic signal with delegation's group divided by 2
x, and x equals the value of corresponding displaced signal.
18. recording controller as claimed in claim 14, wherein, each shift cache unit is adjusted the default value of this shift signal based on this channel.
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