CN107615666A

CN107615666A - The interpretation method and decoding equipment of LDPC shortened codes

Info

Publication number: CN107615666A
Application number: CN201580080721.0A
Authority: CN
Inventors: 司小书; 范嘉旗
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2015-09-16
Filing date: 2015-09-16
Publication date: 2018-01-19
Also published as: WO2017045142A1

Abstract

The embodiments of the invention provide a kind of interpretation method and decoding equipment of low density parity check code LDPC shortened codes, the interpretation method includes intercepting P rows N ' row from the P*N original checksums matrixes of full code corresponding to shortened code, as P*N ' object identifier matrixes, wherein, K ' row of the N ' row including at least the original checksums matrix of position correspondence of the individual information bits of K ' in full code, arranged with the last P of original checksums matrix, N is the length of complete code length corresponding to shortened code, N ' be code length corresponding to object identifier matrix length, K '+P≤N '<N；According to object identifier matrix, row decoding is entered to shortened code, obtains the individual decoding bits of K '.The embodiment of the present invention, without entering row decoding to full code, improves the handling capacity and decoding efficiency of decoding because the object identifier matrix smaller than original checksums matrix of use decodes to shortened code.

Description

Decoding method and decoding equipment of LDPC truncated code

Technical Field

The embodiment of the invention relates to the technical field of communication, in particular to a decoding method and decoding equipment of a low-density parity check code (LDPC) truncated code.

Background

The purpose of communication is to ensure the reliability, security and validity of the delivered messages. However, the validity and the reliability are contradictory, and generally, when information is transmitted, certain redundant information is added to achieve the reliability of communication, but the bandwidth of the system is wasted, that is, the validity is reduced. In order to realize reliable information transmission, researchers have proposed error-correcting coding schemes to resist the interference of channel noise on the transmitted information during transmission, and further ensure the reception of reliable transmitted information.

According to Shannon (Shannon) theory, the Shannon limit is the minimum bit snr at which error correction coding can perform effective error correction. The performance of error correction coding is determined by the degree of approaching the shannon limit. . In the 90 s of the 20 th century, Turbo codes were proposed, the performance of which is very close to the shannon limit. Following Turbo codes, Low Density Parity Check codes (LDPC) have attracted much attention from researchers, and have become a research hotspot in the field of communications in recent years.

Generally, the longer the LDPC code length, the better the decoding performance, but the long code length means that more resources are occupied for logic implementation, and the throughput of the decoding module is low because the LDPC decoding requires multiple iterations. In practical applications, it is necessary to reduce the amount of data involved in decoding as much as possible, thereby reducing resources occupied by logic implementation and improving decoding throughput.

Because of its ease of application, LDPC truncated codes are widely adopted by many standards. When the LDPC truncation code is coded, the information bit of the coding is less than the length of the complete information code, and zero value is filled behind the residual data, so that the length of the total data is equal to the length of the complete information code. Then, the information code is encoded to generate check bits. Finally, the padded zeros are removed and the data and check portions are sent into the channel. When decoding the LDPC truncated code, the traditional decoding method firstly fills a specific value to a truncated position, then decodes the complete code word, and finally only outputs the decoded information part (which is shorter than the length of the complete information code).

The decoding process of the traditional LDPC truncated code is the same as that of the complete code, the processed data volume is also the same, but the output effective data length is short, and in extreme cases, the output effective data length is 1, which causes the throughput of the LDPC truncated code to be very low.

Disclosure of Invention

The embodiment of the invention provides a decoding method and decoding equipment of an LDPC truncated code, and the decoding method can improve the decoding throughput.

In a first aspect, a method for decoding an LDPC truncated code of a low density parity check code, the truncated code including K' information bits and P check bits, the method comprising:

intercepting P rows and N 'columns from a P x N original check matrix of a complete code corresponding to the truncated code to be used as a P x N' target check matrix, wherein the N 'columns at least comprise K' columns of the original check matrix corresponding to the positions of the K 'information bits in the complete code and the last P column of the original check matrix, N is the length of the complete code length corresponding to the truncated code, N' is the length of the code length corresponding to the target check matrix, and K '+ P is less than or equal to N' < N;

and decoding the truncated code according to the target check matrix to obtain K' decoding bits.

With reference to the first aspect, in a first possible implementation manner, the decoding the truncated code according to the target check matrix to obtain K' decoded bits includes:

and decoding the truncated code by adopting a minimum sum Min-sum decoding algorithm according to the target check matrix to obtain K' decoding bits.

With reference to the first aspect or the first possible implementation manner, in a second possible implementation manner,

the method for intercepting the P rows and N 'columns from the P x N original check matrix of the complete code corresponding to the truncated code as the P x N' target check matrix includes:

and intercepting K ' columns of the original check matrix corresponding to the positions of the K ' information bits in the complete code and the last P columns of the original check matrix from the P x N original check matrix of the complete code corresponding to the truncated code to be used as a P x N ' target check matrix, wherein N ' is K ' + P.

With reference to the first possible implementation manner, in a third possible implementation manner, the truncated code is a quasi-cyclic low-density parity-check code QC-LDPC truncated code, a dimension of an original base matrix of a P × N original check matrix of a complete code corresponding to the QC-LDPC truncated code is P/L × N/L, L is an expansion factor,

and intercepting the original base matrix ceil (K '/L) columns corresponding to the positions of the K' information bits in the complete code from the original base matrix and the last P/L columns of the original base matrix to be used as a P N target check matrix, wherein ceil (K '/L) represents the minimum integer which is greater than or equal to K'/L, and N '═ ceil (K'/L) + P/L) L.

With reference to the third possible implementation manner, in a fourth possible implementation manner, when K' is not an integer multiple of L, before the decoding the truncated code by using a Min-sum decoding algorithm according to the target check matrix, the decoding method further includes:

filling Z preset log-likelihood ratio LLR values before and/or after K 'bits in the LDPC truncated code to obtain a target truncated code, wherein the code length of the target truncated code is N', Z is N '- (K' + P),

wherein, decoding the truncated code by using a Min-sum decoding algorithm according to the target check matrix to obtain K' bits includes:

and decoding the target truncated code by adopting a minimum sum Min-sum decoding algorithm according to the target check matrix to obtain K' decoding bits.

In a second aspect, there is provided a decoding apparatus of a low density parity check code LDPC truncated code, the truncated code including K' information bits and P check bits, the decoding apparatus comprising:

an intercepting unit, configured to intercept P rows and N 'columns from a P × N original check matrix of a complete code corresponding to the truncated code, as a P × N' target check matrix, where the N 'column at least includes a K' column of the original check matrix corresponding to a position of the K 'information bits in the complete code, and a last P column of the original check matrix, where N is a length of the complete code length corresponding to the truncated code, N' is a length of the code length corresponding to the target truncated code, and K '+ P is less than or equal to N' < N;

and the decoding unit is used for decoding the truncated code according to the target check matrix to obtain K' decoding bits.

With reference to the second aspect, in a first possible implementation manner, the decoding unit decodes the truncated code by using a Min-sum decoding algorithm according to the target check matrix, and obtains K' decoded bits.

With reference to the second aspect or the first possible implementation manner of the second aspect, in a second possible implementation manner,

the intercepting unit intercepts K 'columns of the original check matrix corresponding to the positions of the K' information bits in the complete code and the last P columns of the original check matrix from the P x N original check matrix of the complete code corresponding to the truncated code, and the K 'columns and the last P columns serve as P x N' target check matrices, wherein N 'is K' + P.

With reference to the first possible implementation manner of the second aspect, in a third possible implementation manner, the truncated code is a quasi-cyclic low-density parity-check code QC-LDPC truncated code, a dimension of an original base matrix of a P × N original check matrix of a complete code corresponding to the QC-LDPC truncated code is P/L × N/L, L is an expansion factor,

the truncation unit truncates, from the original base matrix, a ceil (K '/L) column of the original base matrix corresponding to the position of the K ' information bits in the complete code and a last P/L column of the original base matrix as a P × N ' target check matrix, where ceil (K '/L) represents a minimum integer greater than or equal to K '/L, and N ' ═ ceil (K '/L) + P/L) < L.

With reference to the third possible implementation manner of the second aspect, in a fourth possible implementation manner, when K' is not an integer multiple of L, the decoding apparatus further includes:

a filling unit, configured to fill Z preset log-likelihood ratio LLR values before and/or after K 'bits in the LDPC truncated code before the decoding unit decodes the truncated code by using a Min-sum decoding algorithm according to the target check matrix, so as to obtain a target truncated code, where the code length of the target truncated code is N', Z is N '- (K' + P),

the decoding unit is specifically configured to decode the target truncated code by using a Min-sum decoding algorithm according to the target check matrix to obtain K' decoding bits.

Based on the technical scheme, the target check matrix corresponding to the truncated code is intercepted from the original check matrix of the complete code corresponding to the truncated code, and the truncated code is decoded according to the target check matrix.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments of the present invention will be briefly described below, and it is obvious that the drawings described below are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic block diagram of padding bits in a decoding method of an LDPC truncated code.

Fig. 2 is a schematic flow chart of a decoding method of an LDPC truncated code.

FIG. 3 is a schematic block diagram of a decoding method of an LDPC truncated code.

Fig. 4 is a schematic flowchart of a decoding method of an LDPC truncated code according to an embodiment of the present invention.

Fig. 5 is a schematic flowchart of a decoding method of an LDPC truncated code according to another embodiment of the present invention.

FIG. 6 is a block diagram illustrating the structure of a QC-LDPC code-base matrix according to one embodiment of the present invention.

Fig. 7 is a block diagram schematically illustrating a structure of an element matrix of a QC-LDPC code basis matrix according to an embodiment of the present invention.

Fig. 8 is a schematic flowchart of a decoding method of an LDPC truncated code according to another embodiment of the present invention.

Fig. 9 is a schematic block diagram of a decoding apparatus of an LDPC truncated code according to an embodiment of the present invention.

Fig. 10 is a schematic block diagram of a decoding apparatus of an LDPC truncated code according to another embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, shall fall within the scope of protection of the present invention.

It should be understood that the technical solutions of the embodiments of the present invention may be applied to various communication systems, for example, a digital communication system and an optical communication system, or the technical solutions of the embodiments of the present invention may be applied to a wired communication system or a wireless communication system, and the embodiments of the present invention are not limited thereto.

It should also be understood that in the embodiment of the present invention, the decoding device may be integrated as a module in any receiver for decoding, and may also be directly a device including, but not limited to, a wireless or wired signal receiver, a computer or other device having a signal receiver function, and the like.

It should be noted that, as shown in fig. 1, an LDPC truncated code decoding method is as follows, before decoding, the truncated code needs to be filled with padding bits to form a complete code, and then decoding is performed.

Specifically, the LDPC parameter is (N, K, P), where N denotes a codeword code length, K denotes an information code length, and P denotes a check code length generated after encoding, and has the following relationship P — N-K. The check matrix H of a particular LDPC is unique with dimensions P × N; and H is a sparse matrix where most of the elements have values equal to 0 and only a few have values equal to 1.

Setting the information code length of the truncated code as K ', and satisfying K' < K; when a sending end carries out LDPC coding, firstly filling K-K 'zero bits behind K' information bits to form K information bits, and then coding the K information bits by using a check matrix H to obtain P check bits; the padded K-K 'zero bits need to be deleted before being sent to the channel, and only K' + P bits are sent.

LDPC decoding can be divided into two broad categories: hard decision decoding and soft decision decoding. The processing object of hard decision decoding is binary data, the calculated data amount is less, but the decoding performance is very limited; the processing object of soft-decision decoding is a Log Likelihood Ratio (LLR) value, the calculated data amount is much larger, but the decoding performance is very good, and in practical application, a soft-decision decoding mode is mainly used. Therefore, the embodiments of the present invention mainly discuss a method using soft-decision decoding.

After receiving K '+ P LLR values, the receiving end needs to fill K-K' specific LLR values to the position of the zero bit filling code of the transmitting end to form a code word with the total length of N; then decoding is carried out according to the check matrix H and the filled code words; the decoding algorithms are many, and here, a minimum-sum (Min-sum) decoding algorithm is taken as an example to describe a decoding process.

If the code length N is 7, the information code length K is 3, and the truncated information code length K' is 2, the check code length P is N-K4, and the dimension of the check matrix H is 4 × 7. The Min-sum based decoding algorithm flow is described in detail below in conjunction with fig. 2 and 3.

And 201, starting.

202, a maximum iteration number Iter is set, and the initialization I is 0.

Specifically, the maximum number of iterations may be, for example, 3, 5, 10, etc., and the initialization iteration number I is 0.

203, receiving a truncated code C ' comprising (K ' + P) LLR values '

The (K-K') LLR values are padded 204 such that the code length equals N, resulting in a new codeword C.

For example, as shown in fig. 3(a), soft information (i.e., codeword C) APP ═ C1C2C3C4C5C6C7 after being padded with a specific value]As shown in fig. 3(a), the codeword C includes 7 LLR values, wherein the 3 rd value C3 represents a padded LLR value, wherein the LLR value is defined as the current bit r_iThe probability equal to 0 is divided by the probability equal to 1 and the result is then logarithmized.

The variable node value is initialized with the C value 205.

The distribution of 1 in the check matrix H is shown in fig. 3(b), the dark background squares represent 1, and the non-background squares represent 0; initializing variable node value Lq by using APP value according to H matrix 1 distribution position_jiAs shown in formula (1), wherein i is a column index, j is a row index, and Lq_jiRepresents the value of the jth row and ith column in the check matrix, Lc_i＝ci,i∈[1,7]。

Lq_ji＝Lc_i (1)

For example, after initialization, the values of the position where the ith column is 1 are all ci. For example, column 1, row 1 has a value of c1 and column 5, row three has a value of c 5.

And 206, updating the check nodes according to the check matrix H.

Updating check node Lr row by row_jiAs shown in FIG. 3 (c); removing the current point to be updated, and multiplying the sign bits of other check nodes in the row to be used as the output sign bit of the current point; dividing the current point, and taking the minimum value of the absolute values of other check nodes as the output absolute value of the current point; and updating line by line until 4 lines are updated. The updating process is shown in formula (2), wherein R_j/iIndicating a set in row j with a column index not equal to i, Lr_jiRepresenting the value of ith row of jth row after updating the check matrix row, representing the point of ith row of jth row to be updated at present, and other check nodes of jth rowAnd the sign bit of the point of the ith column in the jth row obtained by multiplying the sign bits of the points represents the absolute value of the current point obtained by dividing the point of the ith column in the current jth row and taking the minimum value of the absolute values of other check nodes. It should be understood that the result of the above row update is represented by Sign Min (,) in fig. 3 (c).

β_jl＝||Lq_jl|| (3)

For example, after row update, the value of row 1, column 1 is Sign Min (c3, c 5); row 2, column 2 values are Sign Min (c4, c 6).

207, updating variable nodes according to the check matrix H.

Updating variable node Lq column by column_jiAs shown in FIG. 3 (d); removing the current point to be updated, and adding the values of other variable nodes in the column to obtain the updated value of the current point; the updating process is shown in formula (4), wherein C_j/iIndicating a set in column i with a row index not equal to j, Lq_jiAnd the value of the ith row and the ith column after the verification matrix column is updated is shown. And (4) indicating that the point of the ith row and the ith column is removed, and adding the values of other variable nodes of the ith column to obtain the updated value of the point of the ith row and the ith column. It should be understood that in fig. 3(d), the 1 st to 4 th rows are respectively represented by A, B, C, D, the column labels are represented by numbers, for example, a1 represents the value of the 1 st row and 1 st column point after column update, and C5 represents the value of the 5 rd column point in the 3 rd row.

For example, after the column update, the value a1 ═ Sign × Min (c5, c7) in row 1 and column 1.

208, calculating the total variable node value, and performing hard judgment on the total variable node value to obtain C₁

Hard decision, process is shown in fig. 3 (e); adding all the variable node values of each column, and adding LLR original values input at corresponding positions to obtain total variable node values LQ_iA decision to 1 or 0 according to its sign bit; specifically, the decision value is determined according to the following formula:

LLR(r_i)<0 r_i＝1

LLR(r_i)>0 r_i＝0

wherein r is_iRepresents the current bit, where r_i＝LQ_i。

LQ_iIs shown in formula (5), wherein C_iAnd the index set representing the ith column represents the sum of all variable node values of the ith column.

For example, column 1 corresponds to a total variable node value of a1+ C1+ C1.

209, I is equal to Iter.

Specifically, it is determined whether I is equal to the maximum number of iterations Iter. If yes, (Y), i.e., I < Iter, step 212 is performed, and if no, (N), I < Iter, step 210 is performed.

210，I＝I+1。

Specifically, when I is smaller than Iter, the value of I is increased by 1.

211，H*C₁Whether or not it is equal to 0.

According to the code word C after hard judgment₁Checking with H matrix, if checking is successful, H C₁If 0, the iteration is completed and step 212 is executed, otherwise H × C₁Not equal to 0, then add the original input LLR value Lc corresponding to the current column on the basis of the variable node of each column that has been column updated, as shown in FIG. 3(f)_jiAs the updated variable node value Lq_jiAs shown in equation (6).

Thereafter, the iterative execution step 206 is returned to.

For example, the value of row 1, column 1, is updated to A1+ c1 before the next iteration.

212, take C₁The first K' middle bits are output.

Specifically, after the maximum number of iterations is reached, or after the check is successful, the first K' (two) bits are output as the final output result.

213, end.

As can be seen, in the above decoding algorithm, for example, if the LDPC code length N is 16200, K is 14400, P is 1800, and the truncated information code length K' is 1, according to the above truncated code decoding method, the receiving end needs to fill 14399 LLR values first, then perform decoding, and after decoding is completed, output only the first bit as the final output. According to the description of fig. 2 and 3, although only one bit is output, the length of data participating in the iteration is 16200. Therefore, the LDPC truncation code decoding method in the prior art has the following defects: the row and column updating of each iteration needs to process the filled LLR value, so that the decoding processing time is increased, and the system throughput is reduced. The above operation requires additional logic resources to store the filled data, resulting in increased decoding resources.

The embodiment of the invention provides a method for simplifying LDPC truncated code decoding, which solves the problems of low LDPC truncated code decoding throughput and more occupied resources in the prior art. The following is a detailed description with reference to specific examples.

Fig. 4 is a schematic flowchart of a decoding method of an LDPC truncated code according to an embodiment of the present invention. The truncated code includes K' information bits and P check bits, and the decoding method shown in fig. 4 may be executed by a decoding device, and specifically, the decoding method includes:

410, intercepting P rows and N 'columns from a P x N original check matrix of a complete code corresponding to a truncated code to be used as a P x N' target check matrix, wherein the N 'columns at least comprise K' columns of the original check matrix corresponding to the positions of K 'information bits in the complete code and the last P columns of the original check matrix, N is the length of the complete code length corresponding to the truncated code, N' is the length of the code length corresponding to the target check matrix, and K '+ P is less than or equal to N' < N;

and 420, decoding the truncated code according to the target check matrix to obtain K' decoding bits.

Therefore, the target check matrix corresponding to the truncated code is intercepted from the original check matrix of the complete code corresponding to the truncated code, and the truncated code is decoded according to the target check matrix.

In other words, in the embodiment of the invention, the truncated code does not need to be decoded after being filled into the complete code, but the original check matrix is intercepted and then the truncated code is directly decoded, or only a small part of bits are filled and then the decoding is carried out, so that the decoding efficiency is improved.

In addition, the embodiment of the invention reduces the update calculation of the filling LLR value and improves the processing capacity of the decoding module; meanwhile, the embodiment of the invention reduces the storage of the filling LLR value and reduces the occupied resources during the logic realization.

It should be understood that, in 410, in the embodiment of the present invention, the complete check matrix may be truncated according to a truncated position of the truncated code, specifically, each bit of the complete code corresponds to one column of the P × N original check matrix, and in the embodiment of the present invention, the original check matrix may be truncated according to a position of the information bit in the truncated code corresponding to the complete code to obtain the target check matrix, where the target check matrix at least includes all columns corresponding to the information bit and columns corresponding to the check bits, and the number of columns of the target check matrix is smaller than the number of columns of the original check matrix.

For example, when K ' information bits of the truncated code are located in the first K ' bits of the complete code, the target check matrix includes at least the first K ' column (the foremost K ' column of the original check matrix) and the last P column (the last P column of the original check matrix) of the original check matrix, and for example, when K ' information bits are located in the middle K ' bits of the complete code, the target check matrix includes at least the middle K ' column and the last P column of the original check matrix, and for example, when K ' information bits are located in two segments of bits of the complete code, for example, the first segment includes a bits, the second segment includes b bits, and a + b is K ', the target check matrix includes at least the middle a column, b column, and last P column of the original check matrix.

It should be noted that, hereinafter, the detailed description will be given by taking an example that when only K ' information bits are located in the first K ' bits of the complete code, the target check matrix at least includes the first K ' column and the last P column of the original check matrix, but the embodiment of the present invention is not limited thereto.

In other words, the description is given by taking an example in which K 'information bits are located in the first K' bits of the complete code, and is only for helping those skilled in the art understand the embodiment of the present invention, and the embodiment of the present invention is not limited to the specific values or the specific scenarios illustrated. It will be apparent to those skilled in the art from this list that various equivalent modifications or variations, such as those when the K ' information bits are located in the middle K ' bits of the complete code or when the K ' information bits are located in several segments of the complete code, may be made, and such modifications or variations are within the scope of the embodiments of the present invention.

It should be understood that, in the embodiment of the present invention, the obtained K 'decoded bits are decoded bits corresponding to K' information bits of the truncated code. That is, even if there are padding bits, the final output is only the K 'decoded bits corresponding to the K' information bits of the truncated code, in other words, only the decoded information portion is finally output.

It should also be understood that, in the embodiment of the present invention, a plurality of existing methods may be adopted to decode the truncated code according to the target check matrix, so as to obtain K' decoded bits. For example, the truncated code may be decoded by a Min-sum decoding algorithm according to the target check matrix to obtain K' decoded bits. Embodiments of the invention are not limited in this respect.

Next, the minimum sum Min-sum decoding algorithm is used to decode the truncated code, which will be described in detail.

It should be noted that, the feasibility analysis of the embodiment of the present invention is as follows:

according to the definition of LLR, if the LLR value corresponding to the current bit is less than zero, the probability that the current bit is 1 is high, and the LLR value is suitable to be judged to be 1; conversely, if the LLR value is greater than zero, then it is appropriate to be judged to be 0; and the larger the absolute value of the LLR value is, the larger the probability of being judged to be 1 or 0 is; if the LLR value is exactly equal to zero, indicating that the probability that the current bit is equal to 0 or 1 is equal, then the current bit is judged to be 1 or 0 (indicating that an error occurs, resulting in an error). When the transmitting end codes the truncated code, K-K' zero values are filled behind the truncated information code and then the code is coded. Correspondingly, at the receiving end, it is known in advance that the filled true bit is 0, so a positive large LLR value needs to be filled, and the larger the filled LLR value is, the lower the possibility that the position bit is inverted is, and the better the decoding performance is.

From the above description, the value c3 filled in fig. 3(a) is a positive maximum, which means that the value c3 is much larger than other values, and the following analysis is made:

referring to the description of the first row update process of fig. 3(c), since c3 is a positive maximum, c3 does not contribute any to the update of other check nodes of the current row; (first, c3 is a positive value and does not change the symbolic attribute; second, in taking the minimum value, because c3 is a maximum, it is not selected as the minimum value;)

Referring to the column update process of FIG. 3(d), again, the third column c3 value does not contribute any to other column variable node updates;

referring to fig. 3(e), in the hard decision process, only the 3 rd column data among the 7 th column data is related to c 3; however, since the values of a3 and D3 are the minimum values of other rows, respectively, after they are added to c3, the result is still a positive maximum value, and the corresponding bit is hard judged to be 0, which coincides with the real value filled by the transmitting end;

referring to fig. 3(f) for preparing data for next row update, only two data in column 3 out of 7 are associated with c3, c3+ A3 and c3+ D3; since A3 and D3 are the minimum values of row 1 and row 5, respectively, c3+ A3 and c3+ D3 are also two positive maxima, and c3+ A3 can be considered approximately equal to c3, and c3+ D3 is also equal to c 3;

completing one iteration, and entering the next iteration to update the line (refer to fig. 3(c), and fig. 3(f) replaces the diagram (b)); similarly, since the value of column 3 is large, it can be considered as the maximum value, and they do not contribute to the row update process; then, the column update process (refer to fig. 3(d)) is performed, and similarly, only the 3 rd column includes the value of c 3; after hard judgment, the 3 rd bit is hard judged to be 0; the data is ready for the next row update, and similarly, only two data in column 3 are associated with c3, and the value of c3 is maximum.

From the above description process, it can be concluded that, when decoding the truncated codes by using the Min-Sum algorithm, the LLR values filled by the existing algorithm have limited influence on the updating of the algorithm; only when the filled c3 is small, and after iteration, the value of the position of c3 is updated to the minimum value, the update of other nodes can be affected, but in this case, the value of the position of c3 is already small, and the sign of the position of c3 may even be reversed, so that misjudgment is caused, and the decoding performance is reduced. It can therefore be seen that even though the padding LLR values have an effect on the iterative process, they have only a negative effect. The padded LLRs may not have to participate in the update process during the iterative process.

Therefore, in the embodiment of the invention, the target check matrix corresponding to the truncated code is obtained by intercepting the original check matrix of the complete code corresponding to the truncated code, and the scheme of decoding the truncated code by adopting the target check matrix is feasible and effective.

Optionally, as another embodiment, in 410, K ' columns of the original check matrix corresponding to positions of K ' information bits in the complete code and the last P columns of the original check matrix are truncated from P × N original check matrix of the complete code corresponding to the truncated code, as P × N ' target check matrix, where N ' ═ K ' + P.

For example, according to the length K ' of the truncated code information code and the check bit P, the first K ' column and the last P column of the original check matrix H are truncated to obtain a new check matrix H ', in the existing scheme, the decoding object C includes a part filled due to truncation, and the length is N; matrix H is the original check matrix with dimensions P × N. In the scheme of the invention, compared with the existing scheme, the decoding object C 'reduces the part filled in C, and the new matrix H' reduces the matrix blocks filled in H correspondingly. Therefore, the target check matrix smaller than the original check matrix is adopted to decode the truncated code, and the decoding of the complete code is not needed, so that the decoding throughput is improved, and the decoding efficiency is improved.

It should be understood that the intercepted target check matrix in the embodiment of the present invention may correspond to the truncated code exactly, that is, the number of columns of the code word of the truncated code is equal to that of the target check matrix; the number of columns of the target check matrix may also be greater than the number of codewords of the truncated code but smaller than the number of columns of the complete check matrix, in this case, certain padding bits need to be padded on the basis of the truncated code according to the existing method, so that the number of columns of the padded codewords is equal to the number of columns of the target check matrix, in this case, although padding bits are also needed, only a small number of bits need to be padded, and compared with the prior art, the decoding efficiency can also be improved.

This is described in detail below with reference to the specific example of fig. 5. The decoding method shown in fig. 5 includes:

501, begin.

502, the maximum iteration number Iter is set, and the initialization I is 0.

503, intercepting the check matrix H according to the value K 'to obtain a new matrix H'.

Specifically, according to the truncated code information code length K ', the P × N original check matrix H is truncated to obtain a new P × N ' check matrix H ', where N ' ═ K ' + P.

504, receiving a truncated code C ' comprising (K ' + P) LLR values '

And 505, initializing a variable node value by using the C' value.

Specifically, step 505 is similar to step 205, and the specific implementation in step 505 is similar to step 205, except that the LDPC code and the check matrix are different, but the specific processing procedure is the same, and is not described in detail here to avoid repetition, specifically, the difference is only that the truncated code in step 505, the complete code in step 205, the corresponding check matrix in step 505 is the P × N' target check matrix, and the P × N original check matrix in step 205.

The check nodes are row updated 506 based on the new check matrix H'.

Specifically, step 506 is similar to step 206, and the specific implementation in step 506 is similar to step 206, except that the LDPC code and the check matrix are different, but the specific processing procedure is the same, and is not described in detail here to avoid repetition.

507, updating variable nodes according to the new check matrix H' in a column mode.

Specifically, step 507 is similar to step 207, and the specific implementation in step 507 is similar to step 207, except that the LDPC code and the check matrix are different, but the specific processing procedure is the same, and in order to avoid repetition, detailed description is omitted here.

And 508, calculating a total variable node value, and performing hard judgment on the total variable node value to obtain a bit sequence C1'.

Specifically, step 508 is similar to step 208, and the specific implementation in step 508 is similar to step 208, except that the LDPC code and the check matrix are different, but the specific processing procedure is the same, and is not described in detail here to avoid repetition.

509, whether I equals Iter

Specifically, it is determined whether I is equal to the maximum number of iterations Iter. If I is equal to Iter, step 512 is executed, and if I < Iter, step 510 is executed.

510，I＝I+1

Specifically, when I is smaller than Iter, the value of I is increased by 1.

511, H '. C1' is equal to 0

Specifically, the hard judgment result is checked, whether the product of the matrix H 'and the matrix C1' is equal to zero or not is judged, if not, the next iteration is performed, step 506 is performed, and otherwise, 512 is performed;

wherein, step 511 is similar to step 211, and the specific implementation in step 511 is similar to step 211, except that the LDPC code and the check matrix are different, but the specific processing procedure is the same, and in order to avoid repetition, detailed description is omitted here.

And 512, taking the first K 'bits in C1' as output.

Specifically, after the maximum number of iterations is reached, or after the verification is successful, the first K' bits are output as the final output result.

513, the process is ended.

Therefore, in the embodiment of the invention, the target check matrix corresponding to the truncated code is intercepted from the original check matrix of the complete code corresponding to the truncated code, and the scheme of decoding the truncated code by adopting the target check matrix is feasible and effective.

Optionally, as another embodiment, the LDPC truncated Code is a Quasi-Cyclic Low Density Parity Check Code (QC-LDPC) truncated Code, a dimension of an original basis matrix of a P × N original Check matrix of a complete Code corresponding to the QC-LDPC truncated Code is P/L × N/L, L is an expansion factor,

at 410, the original base matrix ceil (K '/L) column corresponding to the position of K ' information bits in the complete code and the last P/L column of the original base matrix are truncated from the original base matrix as a P × N ' target check matrix, wherein ceil (K '/L) represents the minimum integer greater than or equal to K '/L, and N ' ═ ceil (K '/L) + P/L) × L.

Further, as another embodiment, when K' is not an integer multiple of L, the decoding method further includes:

in 420, the target truncated code is decoded by using a Min-sum decoding algorithm according to the target check matrix to obtain K' decoding bits.

It should be understood that, in the embodiment of the present invention, Z preset log-likelihood ratio LLR values are padded before and/or after K 'bits in the LDPC truncated code, as the case may be, to obtain the target truncated code, so that the code length of the target truncated code is N', Z ═ N '- (K' + P). For example, when K ' information bits of the truncated code are located at positions in the complete code, the padded bits may be located before K ' bits or after K ' bits.

In particular, in LDPC applications, QC-LDPC is a dominant type due to its smaller memory requirements. The check matrix of QC-LDPC is determined by two parameters, a base matrix H1 and a dilation factor L. Fig. 6 depicts the structure of the basis matrix H1, where the expansion factor L is 8. Each element of the base matrix represents a square matrix of L x L, the value of the square matrix being determined by the value of the element. According to the example of the dimension parameter 4 × 10(m is 4, n is 10) of the base matrix and the expansion factor L is 8, the dimension of the original check matrix H is 32 × 80(mL × nL), and then the basic parameters of the LDPC are obtained: n80, P32 and K48. The values of the elements in the base matrix can be divided into two types, -1 and non-1. -1 represents a zero matrix of L x L; a value other than-1, e.g., k, which represents the matrix obtained by right-shifting the unit matrix of L × L by k times in a unit cycle with the column vector as a unit, and 0 represents a unit matrix of L × L; and 1 represents a matrix obtained by circularly shifting the unit matrix to the right once by taking the column vector as a unit. k ranges from-1, 0, 1, …, L-1. Fig. 7 illustrates the case where k is equal to the matrix content represented by the values 0, 1 and 2, and the case where k takes other values, and so on, can be obtained, and will not be described again here.

According to the description of QC-LDPC, the check matrix H of this type can be represented by a base matrix H1 and a dilation factor L, and only H1 needs to be stored in logic implementation, so that compared with a general way of storing the original check matrix H, the storage amount is greatly reduced. Therefore, the QC-LDPC is widely applied in many scenes at present.

It should be understood that, when the number K ' of information bits of the QC-LDPC code is an integer multiple of the expansion factor L, the embodiment of the present invention does not need to perform padding, and the specific processing procedure is similar to that in fig. 5, except that the leading ceil (K '/L) column and the trailing P/L column of the original base matrix are truncated to obtain the P × N ' target check matrix. Other subsequent processes are similar to the method of fig. 5 and will not be described in detail here.

When K ' is not an integer multiple of L, the decoding method in the embodiment of the present invention needs to fill Z preset log-likelihood ratio LLR values after K ' bits in the LDPC truncated code to obtain the target truncated code, so that the code length of the target truncated code is N ', and Z ═ N ' - (K ' + P). The purpose of the filling bits is to make the code length of the target truncated code correspond to the target check matrix, so as to decode the target truncated code by adopting a minimum sum Min-sum decoding algorithm according to the target check matrix, and obtain the first K' decoding bits.

It should be understood that the truncated target check matrix in the embodiment of the present invention may correspond to the truncated code exactly, that is, the number of columns of the target check matrix including the smallest integer greater than or equal to K'/L corresponding to the position of the information bit of the truncated code in the complete code, and the later P/L columns. The number of columns of the target check matrix may also be greater than the number of columns, but is smaller than the number of columns of the complete check matrix, in this case, a certain number of padding bits need to be padded on the basis of the truncated code according to the existing method, so that the number of columns of the padded codeword is equal to the number of columns of the target check matrix, in this case, although padding bits are also needed, only a small number of bits need to be padded, and compared with the prior art, the decoding efficiency can also be improved.

Referring to fig. 8, a specific decoding method according to an embodiment of the present invention when K' is not an integer multiple of L will be described in detail.

Specifically, the decoding method shown in fig. 8 includes:

801, begin.

And 802, setting the maximum iteration number Iter, and initializing I to 0.

803, according to the value of K ', intercepting the check matrix H to obtain a new matrix H1'.

Specifically, the front ceil (K '/L) column and the back P/L column of the original base matrix are intercepted to obtain a P x N' target check matrix, wherein ceil (K '/L) represents the minimum integer which is greater than or equal to K'/L,

N’＝(ceil(K’/L)+P/L)*L。

804, a truncated code C ' comprising (K ' + P) LLR values is received '

805, N ' - (K ' + P) LLR values are padded to make the code length equal to N ', resulting in a new codeword C "

And filling Z preset log-likelihood ratio LLR values after K 'bits in the LDPC truncated code to obtain the target truncated code, wherein the code length of the target truncated code is N', and Z is N '- (K' + P).

The variable node value is initialized 806 with the C "value.

Specifically, step 806 is similar to step 205, and the specific implementation in step 806 is similar to step 205, except that the LDPC code and the check matrix are different, but the specific processing procedure is the same, and is not described in detail here to avoid repetition, and specifically, the difference is only that the truncated code in step 806, the complete code in step 205, the corresponding check matrix in step 806 is the P × N' target check matrix, and the P × N original check matrix in step 205.

807, the check nodes are row updated according to the new check matrix H1'.

Specifically, step 807 is similar to step 206, and the specific implementation in step 807 is similar to step 206, except that the LDPC code and the check matrix are different, but the specific processing procedure is the same, and in order to avoid repetition, detailed description is omitted here.

808, column updates variable nodes according to the new check matrix H1'.

Specifically, step 808 is similar to step 207, and the specific implementation in step 808 is similar to step 207, except that the LDPC code and the check matrix are different, but the specific processing procedure is the same, and is not described in detail here to avoid repetition.

And 809, calculating the total variable node value, and performing hard judgment on the total variable node value to obtain a bit sequence C1'.

Specifically, step 809 is similar to step 208, and the specific implementation in step 809 is similar to step 208, except that the LDPC code and the check matrix are different, but the specific processing procedure is the same, and is not detailed here to avoid repetition.

810, whether I equals Iter

Specifically, it is determined whether I is equal to the maximum number of iterations Iter. If I is equal to Iter, step 813 is performed, and if I < Iter, step 811 is performed.

811，I＝I+1

Specifically, when I is smaller than Iter, the value of I is increased by 1.

812, H1'. C1 "equal to 0

Specifically, the hard determination result is checked, whether the product of the matrix H1' and the matrix C ″ is equal to zero is determined, if not, the next iteration is performed, step 807 is performed, otherwise, 813 is performed.

Wherein, step 812 is similar to step 211, and the specific implementation in step 812 is similar to step 211, except that the LDPC code and the check matrix are different, but the specific processing procedure is the same, and is not detailed here to avoid repetition.

813, take the first K' bits of C1 "as output.

814, end.

Therefore, in the embodiment of the invention, the target check matrix corresponding to the truncated code is intercepted from the original check matrix of the complete code corresponding to the truncated code, and the truncated code is decoded according to the target check matrix.

It should be noted that the examples of fig. 1 to 8 are only for assisting those skilled in the art in understanding the embodiments of the present invention, and are not intended to limit the embodiments of the present invention to the specific values or specific scenarios illustrated. It will be apparent to those skilled in the art from the examples given in figures 1 to 8 that various equivalent modifications or variations are possible, and such modifications or variations are intended to be within the scope of the embodiments of the present invention.

The decoding method according to the embodiment of the present invention is described in detail above with reference to fig. 1 to 8, and the decoding apparatus according to the embodiment of the present invention will be described below with reference to fig. 9 and 10.

Fig. 9 is a schematic block diagram of a decoding apparatus of an LDPC truncated code according to an embodiment of the present invention. The decoding apparatus 900 shown in fig. 9 corresponds to the decoding method shown in fig. 4, the decoding apparatus 900 can implement the processes in the embodiment of the decoding method shown in fig. 4, the specific functions of the decoding apparatus 900 can be referred to the corresponding description in fig. 4, and the detailed description is appropriately omitted here to avoid repetition. The decoding apparatus 900 is for low density parity check code LDPC truncated code decoding, and may include: a truncation unit 910 and a decoding unit 920.

Specifically, the intercepting unit 910 is configured to intercept a P × N original check matrix of a complete code corresponding to a truncated code, to obtain a P × N ' target check matrix, where the target check matrix at least includes a K ' column and a P-column that correspond to positions of information bits of the truncated code in the complete code in the original check matrix, N is a length of the complete code length corresponding to the truncated code, N ' is a length of the code length corresponding to the target truncated code, and K ' + P is less than or equal to N ' < N; the decoding unit 920 decodes the truncated code according to the target check matrix to obtain K' decoded bits.

Optionally, as another embodiment, the decoding unit 920 decodes the truncated code by using a Min-sum decoding algorithm according to the target check matrix, and obtains K' decoded bits.

Optionally, as another embodiment, the truncating unit 910 truncates, from the P × N original check matrix of the complete code corresponding to the truncated code, a K ' column of the original check matrix corresponding to the position of the K ' information bits in the complete code, and a last P column of the original check matrix, as a P × N ' target check matrix, where N ' ═ K ' + P.

Alternatively, as another embodiment, the LDPC truncated code is a quasi-cyclic low density parity check code QC-LDPC truncated code, the dimension of the original base matrix of the P × N original check matrix of the complete code corresponding to the QC-LDPC truncated code is P/L × N/L, L is an expansion factor,

truncating unit 910 truncates, from the original base matrix, a ceil (K '/L) column of the original base matrix corresponding to the position of the K ' information bits in the complete code and a last P/L column of the original base matrix as a P × N ' target check matrix, where ceil (K '/L) represents a minimum integer greater than or equal to K '/L, and N ' ═ ceil (K '/L) + P/L) × L.

Further, as another embodiment, when K' is not an integer multiple of L, the decoding apparatus further includes: and filling the cells.

Specifically, the padding unit is configured to, before the decoding unit decodes the truncated code by using a Min-sum decoding algorithm according to the target check matrix, pad Z preset log-likelihood ratio LLR values before K 'bits in the LDPC truncated code to obtain the target truncated code, so that the code length of the target truncated code is N', Z ═ N '- (K' + P),

the decoding unit 920 is specifically configured to decode the target truncated code by using a Min-sum decoding algorithm according to the target check matrix to obtain K' decoding bits corresponding to the target truncated code.

Fig. 10 is a schematic block diagram of a decoding apparatus of an LDPC truncated code according to another embodiment of the present invention. . The decoding apparatus 1000 shown in fig. 10 corresponds to the decoding method shown in fig. 4, the decoding apparatus 1000 can implement the processes in the embodiment of the decoding method shown in fig. 4, the specific functions of the decoding apparatus 1000 can be referred to the corresponding description in fig. 4, and the detailed description is appropriately omitted here to avoid repetition. The decoding apparatus 1000 is for low density parity check code LDPC truncated code decoding, and may include: including a processor 1010, memory 1020, and bus system 1030.

Specifically, the processor 1010 calls the codes stored in the memory 1020 through the bus system 1030, and intercepts P rows and N 'columns from a P × N original check matrix of a complete code corresponding to a truncated code, as a P × N' target check matrix, where the N 'columns at least include K' columns of the original check matrix corresponding to positions of K 'information bits in the complete code, and a last P column of the original check matrix, N is a length of the complete code length corresponding to the truncated code, N' is a length of the code length corresponding to the target check matrix, and K '+ P is equal to or less than N' < N; and decoding the truncated code according to the target check matrix to obtain K' decoding bits.

The method disclosed in the above embodiments of the present invention may be applied to the processor 1010 or implemented by the processor 1010. The processor 1010 may be an integrated circuit chip having signal processing capabilities. In implementation, the steps of the above method may be performed by integrated logic circuits of hardware or instructions in the form of software in the processor 1010. The Processor 1010 may be a general-purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic device, or discrete hardware components. The various methods, steps and logic blocks disclosed in the embodiments of the present invention may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of the method disclosed in connection with the embodiments of the present invention may be directly implemented by a hardware decoding processor, or implemented by a combination of hardware and software modules in the decoding processor. The software module may be located in a Random Access Memory (RAM), a flash Memory, a Read-Only Memory (ROM), a programmable ROM, an electrically erasable programmable Memory, a register, or other storage media that are well known in the art. The storage medium is located in the memory 1020, the processor 1010 reads the information in the memory 1020, and the steps of the above method are completed by combining the hardware, and the bus system 1030 may include a power bus, a control bus, a status signal bus, and the like besides a data bus. For clarity of illustration, however, the various buses are designated in the figure as the bus system 1030.

Optionally, as another embodiment, the processor 1010 decodes the truncated code by using a Min-sum decoding algorithm according to the target check matrix to obtain K' decoded bits.

Optionally, as another embodiment, the processor 1010 truncates, from the P × N original check matrix of the complete code corresponding to the truncated code, a K ' column of the original check matrix corresponding to the position of the K ' information bits in the complete code, and a last P column of the original check matrix as a P × N ' target check matrix, where N ' ═ K ' + P.

processor 1010 truncates, from the original base matrix, a ceil (K '/L) column of the original base matrix corresponding to the position of the K ' information bits in the complete code and a last P/L column of the original base matrix as a P × N ' target check matrix, where ceil (K '/L) represents a minimum integer greater than or equal to K '/L, and N ' ═ ceil (K '/L) + P/L) _.

Further, as another embodiment, when K ' is not an integer multiple of L, the processor 1010 fills Z preset log-likelihood ratio LLR values before and/or after K ' bits in the LDPC truncated code before the decoding unit decodes the truncated code by the Min-sum decoding algorithm according to the target check matrix, so as to obtain the target truncated code, such that the code length of the target truncated code is N ', Z ═ N ' - (K ' + P); the processor 1010 is specifically configured to decode the target truncated code by using a Min-sum decoding algorithm according to the target check matrix to obtain K' decoding bits corresponding to the target truncated code.

It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in various embodiments of the present invention, the sequence numbers of the above-mentioned processes do not mean the execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

Additionally, the terms "system" and "network" are often used interchangeably herein. The term "and/or" herein is merely an association describing an associated object, meaning that three relationships may exist, e.g., a and/or B, may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.

It should be understood that in the present embodiment, "B corresponding to a" means that B is associated with a, from which B can be determined. It should also be understood that determining B from a does not mean determining B from a alone, but may be determined from a and/or other information.

Those of ordinary skill in the art will appreciate that the elements and algorithm steps of the examples described in connection with the embodiments disclosed herein may be embodied in electronic hardware, computer software, or combinations of both, and that the components and steps of the examples have been described in a functional general in the foregoing description for the purpose of illustrating clearly the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.

In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, a division of a unit is merely a logical division, and an actual implementation may have another division, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may also be an electric, mechanical or other form of connection.

Units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment of the present invention.

In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.

From the above description of the embodiments, it is clear to those skilled in the art that the present invention can be implemented by hardware, firmware, or a combination thereof. When implemented in software, the functions described above may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a computer. Taking this as an example but not limiting: computer-readable media can include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. Furthermore, the method is simple. Any connection is properly termed a computer-readable medium. For example, if software is transmitted from a website, a server, or other remote source using a coaxial cable, a fiber optic cable, a twisted pair, a Digital Subscriber Line (DSL), or a wireless technology such as infrared, radio, and microwave, the coaxial cable, the fiber optic cable, the twisted pair, the DSL, or the wireless technology such as infrared, radio, and microwave are included in the fixation of the medium. Disk and disc, as used herein, includes Compact Disc (CD), laser disc, optical disc, Digital Versatile Disc (DVD), floppy Disk and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

In short, the above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

A decoding method of a Low Density Parity Check (LDPC) truncated code, wherein the truncated code comprises K' information bits and P check bits, the decoding method comprising:

intercepting P rows and N 'columns from a P x N original check matrix of a complete code corresponding to the truncated code to be used as a P x N' target check matrix, wherein the N 'columns at least comprise K' columns of the original check matrix corresponding to the positions of the K 'information bits in the complete code and the last P columns of the original check matrix, N is the length of the complete code length corresponding to the truncated code, N' is the length of the code length corresponding to the target check matrix, and K '+ P is less than or equal to N' < N;

and decoding the truncated code according to the target check matrix to obtain K' decoding bits.
The decoding method according to claim 1,

the decoding the truncated code according to the target check matrix to obtain K' decoded bits includes:

and decoding the truncated code by adopting a minimum sum Min-sum decoding algorithm according to the target check matrix to obtain K' decoding bits.
The decoding method according to claim 1 or 2,

the intercepting P rows and N 'columns from the P × N original check matrix of the complete code corresponding to the truncated code as a P × N' target check matrix includes:

and intercepting K ' columns of the original check matrix corresponding to the positions of the K ' information bits in the complete code and the last P columns of the original check matrix from P × N original check matrix of the complete code corresponding to the truncated code to serve as P × N ' target check matrix, wherein N ' ═ K ' + P.
The decoding method according to claim 2,

the truncated code is quasi-cyclic low-density parity check code QC-LDPC truncated code, the dimension of an original base matrix of a P N original check matrix of a complete code corresponding to the QC-LDPC truncated code is P/L N/L, L is an expansion factor,

the intercepting P rows and N 'columns from the P × N original check matrix of the complete code corresponding to the truncated code as a P × N' target check matrix includes:

and intercepting the original base matrix ceil (K '/L) column corresponding to the position of the K ' information bits in the complete code from the original base matrix and the last P/L column of the original base matrix as a P N ' target check matrix, wherein ceil (K '/L) represents the minimum integer which is greater than or equal to K '/L, and N ' ═ ceil (K '/L) + P/L) L.
The decoding method according to claim 4,

when K' is not an integer multiple of L, before decoding the truncated code by using Min-sum decoding algorithm according to the target check matrix, the decoding method further includes:

filling Z preset log-likelihood ratio LLR values before and/or after K 'bits in the truncated code to obtain a target truncated code, wherein the code length of the target truncated code is N', Z is N '- (K' + P),

decoding the truncated code by adopting a Min-sum decoding algorithm according to the target check matrix to obtain K' bits, wherein the decoding comprises the following steps:

and decoding the target truncated code by adopting a minimum sum Min-sum decoding algorithm according to the target check matrix to obtain K' decoding bits.
A decoding apparatus of a low density parity check code LDPC truncated code, wherein the truncated code includes K' information bits and P check bits, the decoding apparatus comprising:

an intercepting unit, configured to intercept P rows and N 'columns from a P × N original check matrix of a complete code corresponding to the truncated code, as a P × N' target check matrix, where the N 'column at least includes a K' column of the original check matrix corresponding to a position of the K 'information bits in the complete code, and a last P column of the original check matrix, where N is a length of the complete code length corresponding to the truncated code, N' is a length of the code length corresponding to the target truncated code, and K '+ P is less than or equal to N' < N;

and the decoding unit is used for decoding the truncated code according to the target check matrix to obtain K' decoding bits.
The decoding apparatus according to claim 6,

and the decoding unit is used for decoding the truncated code by adopting a minimum sum Min-sum decoding algorithm according to the target check matrix to obtain K' decoding bits.
The decoding apparatus according to claim 6 or 7,

the intercepting unit intercepts K 'columns of the original check matrix corresponding to the positions of the K' information bits in the complete code and the last P columns of the original check matrix from the P x N original check matrix of the complete code corresponding to the truncated code, and the K 'columns and the last P columns serve as P x N' target check matrices, wherein N 'is K' + P.
The decoding apparatus according to claim 7,

the truncated code is quasi-cyclic low-density parity check code QC-LDPC truncated code, the dimension of an original base matrix of a P N original check matrix of a complete code corresponding to the QC-LDPC truncated code is P/L N/L, L is an expansion factor,

the truncation unit truncates, from the original base matrix, a ceil (K '/L) column of the original base matrix corresponding to the position of the K ' information bits in the complete code and a last P/L column of the original base matrix as a P × N ' target check matrix, where ceil (K '/L) represents a minimum integer greater than or equal to K '/L, and N ' ═ is (ceil (K '/L) + P/L) < L.
The decoding apparatus according to claim 9,

when the K' is not an integer multiple of L, the coding apparatus further comprises:

a filling unit, configured to fill Z preset log-likelihood ratio LLR values before and/or after K 'bits in the LDPC truncated code before the decoding unit decodes the truncated code by using a Min-sum decoding algorithm according to the target check matrix, so as to obtain a target truncated code, where the code length of the target truncated code is N', Z is N '- (K' + P),

the decoding unit is specifically configured to decode the target truncated code by using a Min-sum decoding algorithm according to the target check matrix to obtain K' decoding bits.