CN106601305A - Solid-state disk error correction method combining error detection code with error correction code - Google Patents
Solid-state disk error correction method combining error detection code with error correction code Download PDFInfo
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- CN106601305A CN106601305A CN201611025081.6A CN201611025081A CN106601305A CN 106601305 A CN106601305 A CN 106601305A CN 201611025081 A CN201611025081 A CN 201611025081A CN 106601305 A CN106601305 A CN 106601305A
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Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
- G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
- H03M13/1111—Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms
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- Probability & Statistics with Applications (AREA)
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Detection And Correction Of Errors (AREA)
Abstract
The invention discloses a solid-state disk error correction method combining an error detection code with an error correction code. The method comprises the following steps of (1) before data is written in a solid-state disk, encoding original data of flash pages, and storing the data in a storage unit of the solid-state disk; and (2) detecting error states of the flash pages in the storage unit by using error detection code decoding operation, directly reading the flash pages without errors, and performing error correction on the flash pages with errors by using low-density parity-check code (LDPC) decoding operation. According to the method, the flash pages can be subjected to error detection by using error detection code cyclic redundancy check (CRC) firstly when the error rates of the flash pages are very low in an early use stage of the solid-state disk; the detected pages without the errors are directly read without being subjected to the LDPC decoding process; and the detected pages with the errors are subjected to LDPC decoding-based error correction.
Description
Technical field
The invention belongs to solid-state disk error correcting technique field, in particular it relates to one kind is combined using error-detecging code and error correcting code
Solid-state disk error correction method.
Background technology
Solid-state disk has been applied to every field in people's life, it is ensured that the safety of solid-state disk data storage is most important,
Wherein error correcting code is one of the most frequently used technology of data safety of current solid-state disk.With solid-state disk manufacturing process progress, flash memory
Unit size is less and less, and corresponding noise is consequently increased.Solid-state disk internal noise is determined by many factors, such as wiped
Number of times, data retention over time etc., the oxide layer that erasable operation can be destroyed around flash cell are write, and adjacent flash memory list can be caused
Unit produces Charged Couple effect, causes flash cell internal charge amount to change, so as to cause flash cell threshold voltage value
Change, so as to cause corrupt data.Erasable number of times is bigger, and the noise jamming amplitude for causing is bigger, the error of solid-state disk internal data
Rate is higher.In the early application stage of solid-state disk, seldom, data retention over time is also very short, internal data error rate for erasable number of times
Very low, most of Hash memory pages are error-free.In stage middle and later periods of solid-state disk, the increase and data retention over time because of erasable number of times
Prolongation, the error rate of internal data steps up.
Low density parity check code (Low-Density Parity-Check code, LDPC) is because of its excellent error correction energy
Power is applied to every field.LDPC is mainly made up of encoder and decoder.Initial data needs to be given birth to through LDPC encoder
Into check bit, initial data and LDPC check bit collectively form code word.When reading solid-state disk data, code word needs ldpc decoder
Decoding.If initial data malfunctions, can be corrected through LDPC decodings process.If initial data is error-free, under normal circumstances
Also LDPC decoding processes are had to pass through, can thus increases unnecessary decoding time, affect the reading performance of solid-state disk data.
Patent document CN 104464822A disclose a kind of LDPC error correction/encoding method interval based on flash memory mistake, its
According to the current error rate of solid state hard disc channel, accurately mistake interval is calculated, using the possible dislocation of wrong deciding field
Position, has orientated the position in errors present as according to the upset of Bit-Flipping methods coding guideline.This method eliminates Bit-
The propagation of wrong code word, improves error correcting capability and algorithm performs efficiency during the decoding firmly of Flipping methods.But the party
Method has the following disadvantages and defect：
(1) the method does not account for the process of error-free page, and error-free page need not be decoded, and can be directly read；
(2) the method needs the mistake for judging data interval, and for the solid-state disk early application stage, error rate is very low
Even close zero, the time overhead for judging to process can be increased.
If initial data malfunctions, can be corrected through LDPC decodings process.If initial data is error-free, normal condition
Under also have to pass through LDPC decoding processes, can thus increase unnecessary decoding time, affect the reading performance of solid-state disk data.
If detecting the error condition of Hash memory pages using error-detecging code CRC in advance, for error-free page need not then experience LDPC decoding processes.
For wrong page, then error correction is carried out through LDPC decodings process.
The content of the invention
For the disadvantages described above or Improvement requirement of prior art, the present invention is provided one kind and is tied using error-detecging code and error correction code-phase
The solid-state disk error correction method of conjunction, its object is to according to solid-state disk the characteristics of early stage corrupt data rate is extremely low, using inspection
The mode that error code and error correcting code combine, reaches the purpose for improving solid-state disk reading performance, reduces error-free in solid-state disk early stage
The unnecessary LDPC decoding processes of page, reduce the LDPC decoding processes of a large amount of error-free pages of solid-state disk early stage, while reducing
The error correction energy consumption of LDPC code, and improve the reading performance of solid-state disk.
To achieve these goals, the present invention provides the solid-state disk error correction side that a kind of use error-detecging code and error correcting code combine
Method, it is characterised in that：The method comprises the steps：
(1) before solid-state disk write data, the initial data of Hash memory pages is encoded, and is saved in depositing for the solid-state disk
In storage unit；
(2) error condition of Hash memory pages in the memory cell is checked using error-detecging code decoded operation, to there is no mistake
Hash memory pages directly read, to exist mistake the Hash memory pages then entangled using low density parity check code decoded operation
It is wrong.
Further, the error-detecging code decoded operation process includes sentencing each Hash memory pages of the memory cell firmly
Certainly voltage is perceived, and obtains the binary message of data storage, and carries out error-detecging code decoded operation to the Hash memory pages.
Further, the low density parity check code decoded operation process includes：The memory cell is carried out soft to sentence
Certainly voltage is perceived, and is obtained logarithm and is felt relieved than information, and carries out low density parity check code decoded operation to Hash memory pages.
Preferably, it is additionally included in before execution step (2) and judges whether the memory cell writes full step, and it is full to not writing
Memory cell be immediately performed step (2).
Further, for full memory cell is write, also including judging whether solid-state disk inside parallel property can use
The step of, and for the disabled solid-state disk of parallel property shifts to an earlier date execution step (2), for the available solid-state disk of parallel property is carried
Front parallel execution of steps (2).
Preferably, it is additionally included in and judges whether the memory cell is write and completely front judge the solid-state disk whether idle step
Suddenly, and when busy it is immediately performed step (2).
Preferably, it is additionally included in and judges whether judge the solid-state disk before whether solid-state disk inside parallel property is available
The step being detected, and step (2) is immediately performed when judging and being detected, perform the judgement solid-state disk when not being detected
The step of whether internal parallel property can be used.
Preferably, it is additionally included in mistake in the Hash memory pages for judging that the memory cell is judged before whether the solid-state disk is idle
Whether page probability the step of more than the threshold value of setting, and performs when less than threshold value and judge the solid-state disk whether step of free time
Suddenly.
Further, when more than threshold value the solid-state disk is entangled using low density parity check code decoded operation
It is wrong.
Further, the coding detailed process is：
(11) error-detecging code and encoding low density parity check are used respectively to the initial data of the Hash memory pages, respectively
Produce error-detecging code check bit sum low density parity check code check bit；
(12) initial data, error-detecging code check bit and low density parity check code check bit collectively constitute code word；
(13) code word is saved in the memory cell of the solid-state disk.
In general, by the contemplated above technical scheme of the present invention compared with prior art, can obtain down and show
Beneficial effect：
(1) in technical scheme, it is proposed that the CDF- that a kind of solid-state disk is combined using error-detecging code and error correcting code
LDPC methods, the early stage that the method can be used in solid-state disk, in the case where Hash memory pages error rate is very low, first using inspection
Error code CRC carries out error detection to Hash memory pages, directly reads for the error-free page of detection need not carry out LDPC decodings process, and for inspection
The wrong page for going out then carries out LDPC decoding error correction.
(2) because error-free page eliminates LDPC decoding processes, the reading performance of solid-state disk can get a promotion.Simultaneously in solid-state
In disk free time, to completely writing flash block CDF-LDPC decoding processes can be in advance performed.If solid-state disk parallel property can use,
Executed in parallel CDF-LDPC decoding process can be shifted to an earlier date.
(3) the above-mentioned CDF-LDPC decoding processes and executed in parallel CDF-LDPC decoded operation in advance of performing in advance can enter one
Step lifts the reading performance of solid-state disk.On the other hand, because eliminating the LDPC decoded operations to error-free page, the LDPC needed for solid-state disk
Decoding energy consumption is also reduced, and the reliability of solid-state disk is not exposed to any impact.
Description of the drawings
A kind of process of the solid-state disk error correction method that Fig. 1 combines for use error-detecging code and error correcting code of the embodiment of the present invention
Flow chart；
Fig. 2 is related to for the solid-state disk error correction method that a kind of use error-detecging code and error correcting code of the embodiment of the present invention combine
CDF-LDPC cataloged procedure schematic diagrames；
Fig. 3 is related to for the solid-state disk error correction method that a kind of use error-detecging code and error correcting code of the embodiment of the present invention combine
CDF-LDPC decodes process schematic.
Specific embodiment
In order that the objects, technical solutions and advantages of the present invention become more apparent, it is right below in conjunction with drawings and Examples
The present invention is further elaborated.It should be appreciated that specific embodiment described herein is only to explain the present invention, not
For limiting the present invention.As long as additionally, technical characteristic involved in invention described below each embodiment that
Conflict is not constituted between this just can be mutually combined.
A kind of process of the solid-state disk error correction method that Fig. 1 combines for use error-detecging code and error correcting code of the embodiment of the present invention
Flow chart.As shown in figure 1, the method comprises the steps：
(1) cataloged procedure detailed process is：
Before solid-state disk input data, in order to using error correcting code error correction, to carry out error correcting coding process.One Hash memory pages
Initial data be designated as D；
(1.1) as shown in Fig. 2 initial data D of a Hash memory pages performs CRC codings generates CRC check position CRC-P, hold
Row LDPC codings generate LDPC check bit LDPC-P；
Initial data D of (1.2) Hash memory pages, CRC check position CRC-P, LDPC check bit LDPC-P collectively form one
Individual code word is stored in solid-state disk.Each code word increases the Error-free-Judgment identifiers of 1, for judging the page
Whether data malfunction, and initial value is 0, represent that the page data is error-free.If the page data error, Error-free-Judgment
Identifier is set to 1.
(2) process control section detailed process is：
(2.1) as shown in figure 1, when solid-state disk storage unit is accessed, judging the faulty page probability P of Hash memory pages place block is
It is no more than threshold value T, if P ＞ T, the Hash memory pages using LDPC decode error correction, otherwise go to step (2.2)；
(2.2) judge whether solid-state disk is idle, if solid-state disk does not have free time, go to step (3) and be immediately performed, it is no
Then go to step (2.3)；
(2.3) judge whether Hash memory pages place block is completely to write block, if the block is not completely to write block, go to step (3) immediately
Perform, otherwise go to step (2.4)；
(2.4) judge whether flash block is tested, if the block is tested, go to step (3), otherwise go to
Step (2.5)；
(2.5) whether the parallel property for judging solid-state disk can use, if it is not then performing in advance to Hash memory pages place block
Step (3), otherwise shifts to an earlier date parallel execution of steps (3) to Hash memory pages place block；
(3) decoding process is specially：
(3.1) as shown in figure 3, initial data D and CRC check position CRC-P that access Hash memory pages are collectively constituted into CRC code
Word, hard decision voltage is carried out to code word and perceives the specific binary message of acquisition；
(3.2) CRC decoded operations are carried out to CRC code word；
(3.3) judge whether Hash memory pages malfunction, that is, judge whether Error-free-Judgment is 1, if Error-
Free-Judgment is 0, represents that Hash memory pages are error-free, then directly read, and otherwise Error-free-Judgment is set to into 1,
And go to step (3.4)；
(3.4) initial data D and LDPC check bit LDPC-P to accessing Hash memory pages collectively constitutes LDPC code word, to code word
Carry out soft-decision voltage and perceive acquisition log-likelihood ratio information；
(3.5) LDPC decoded operations are carried out to LDPC code word, the mistake in data is corrected；
(3.6) if flash block is wiped free of, all pages in flash block of Error-free-Judgment is set to into 0, table
Show that Hash memory pages are error-free.
The faulty page probability of Hash memory pages place block refer to during faulty page number and flash memory are fast in flash block total page number it
Than.
The present invention proposes a kind of CDF-LDPC methods that solid-state disk is combined using error-detecging code and error correcting code, the method energy
Hash memory pages, in the case where Hash memory pages error rate is very low, are first entered by enough early stages used in solid-state disk using error-detecging code CRC
Row error detection, directly reads for the error-free page of detection need not carry out LDPC decodings process, and for the wrong page of detection is then carried out
LDPC decodes error correction.
Because error-free page eliminates LDPC decoding processes, the reading performance of solid-state disk can get a promotion.Simultaneously in solid-state disk
In free time, to completely writing flash block CDF-LDPC decoding processes can be in advance performed.If solid-state disk parallel property can use, can
To shift to an earlier date executed in parallel CDF-LDPC decoding process.
The above-mentioned CDF-LDPC of execution in advance decoding processes and executed in parallel CDF-LDPC decoded operation in advance can be further
Lift the reading performance of solid-state disk.On the other hand, because eliminating the LDPC decoded operations to error-free page, the LDPC needed for solid-state disk is translated
Code energy consumption is also reduced, and the reliability of solid-state disk is not exposed to any impact.
As it will be easily appreciated by one skilled in the art that the foregoing is only presently preferred embodiments of the present invention, not to
The present invention, all any modification, equivalent and improvement made within the spirit and principles in the present invention etc. are limited, all should be included
Within protection scope of the present invention.
Claims (10)
1. the solid-state disk error correction method that a kind of use error-detecging code and error correcting code combine, it is characterised in that the method includes as follows
Step：
(1) before solid-state disk write data, the initial data of Hash memory pages is encoded, and is saved in the storage list of the solid-state disk
In unit；
(2) error condition of Hash memory pages in the memory cell, the sudden strain of a muscle to there is no mistake are checked using error-detecging code decoded operation
Deposit page to directly read, the Hash memory pages to there is mistake then carry out error correction using low density parity check code decoded operation.
2. the solid-state disk error correction method that a kind of use error-detecging code according to claim 1 and error correcting code combine, wherein, institute
Stating error-detecging code decoded operation process includes carrying out each Hash memory pages of the memory cell hard decision voltage perception, obtains storage
The binary message of data, and error-detecging code decoded operation is carried out to the Hash memory pages.
3. the solid-state disk error correction method that a kind of use error-detecging code according to claim 1 and 2 and error correcting code combine, its
In, the low density parity check code decoded operation process includes：Soft-decision voltage perception is carried out to the memory cell, is obtained
Logarithm is felt relieved than information, and carries out low density parity check code decoded operation to Hash memory pages.
4. the solid-state disk error correction side that a kind of use error-detecging code and error correcting code according to any one of claim 1-3 combines
Method, wherein, it is additionally included in before execution step (2) and judges whether the memory cell writes full step, and to not writing full storage
Unit is immediately performed step (2).
5. the solid-state disk error correction method that a kind of use error-detecging code according to claim 4 and error correcting code combine, wherein, it is right
In full memory cell is write, also including judge solid-state disk inside parallel property whether can with the step of, and for parallel category
The disabled solid-state disk of property shifts to an earlier date execution step (2), for the available solid-state disk of parallel property shifts to an earlier date parallel execution of steps (2).
6. the solid-state disk error correction method that a kind of use error-detecging code and error correcting code according to claim 4 or 5 combines, its
In, be additionally included in judge the memory cell whether write it is completely front judge the solid-state disk whether idle step, and busy
When be immediately performed step (2).
7. the solid-state disk error correction method that a kind of use error-detecging code according to claim 5 and error correcting code combine, wherein, also
It is included in and judges to judge before whether solid-state disk inside parallel property is available the solid-state disk whether step being detected, and
Step (2) is immediately performed when judging and being detected, is performed when not being detected and described is judged inside solid-state disk whether is parallel property
The step of can using.
8. the solid-state disk error correction method that a kind of use error-detecging code according to claim 6 and error correcting code combine, wherein, also
It is included in faulty page probability in the Hash memory pages for judging that the memory cell is judged before the solid-state disk is whether idle and whether is more than and sets
The step of fixed threshold value, and perform when less than threshold value and judge the solid-state disk whether step of free time.
9. the solid-state disk error correction method that a kind of use error-detecging code according to claim 8 and error correcting code combine, wherein,
Error correction is carried out to the solid-state disk using low density parity check code decoded operation more than during threshold value.
10. the solid-state disk error correction that a kind of use error-detecging code and error correcting code according to any one of claim 1-9 combines
Method, wherein, the coding detailed process is：
(11) error-detecging code and encoding low density parity check are used respectively to the initial data of the Hash memory pages, produces respectively
Error-detecging code check bit sum low density parity check code check bit；
(12) initial data, error-detecging code check bit and low density parity check code check bit collectively constitute code word；
(13) code word is saved in the memory cell of the solid-state disk.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107861834A (en) * | 2017-11-06 | 2018-03-30 | 华中科技大学 | A kind of method based on wrong pre-detection skill upgrading solid state hard disc reading performance |
| CN108804025A (en) * | 2018-03-07 | 2018-11-13 | 深圳忆联信息系统有限公司 | A kind of method and solid state disk for reducing flash memory and being detained mistake |
| CN108958963A (en) * | 2018-06-01 | 2018-12-07 | 杭州电子科技大学 | A kind of NAND FLASH error control method based on LDPC and cyclic redundancy check code |
| CN111162794A (en) * | 2018-11-08 | 2020-05-15 | 北京忆芯科技有限公司 | Decoding data caching method and decoder |
| WO2020199490A1 (en) * | 2019-04-01 | 2020-10-08 | 江苏华存电子科技有限公司 | Dual-mode error detection memory and dual-mode error detection method |
| CN114879916A (en) * | 2022-07-12 | 2022-08-09 | 合肥康芯威存储技术有限公司 | Method and device for managing storage unit |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101040445A (en) * | 2005-01-22 | 2007-09-19 | 思科技术公司 | Error protecting groups of data words |
| CN101258471A (en) * | 2005-07-15 | 2008-09-03 | Gsip有限责任公司 | Flash error correction |
| US20090070637A1 (en) * | 2006-03-07 | 2009-03-12 | Nxp B.V. | Electronic circuit with a memory matrix that stores pages including extra data |
| CN102436406A (en) * | 2010-09-15 | 2012-05-02 | 株式会社东芝 | Semiconductor device and data access method thereof |
| CN103186352A (en) * | 2011-12-30 | 2013-07-03 | 三星电子株式会社 | Method of reading data from storage device, error correction device and storage system |
| US20140136926A1 (en) * | 2005-04-28 | 2014-05-15 | Micron Technology, Inc. | Non-systematic coded error correction |
| CN103973272A (en) * | 2013-01-30 | 2014-08-06 | 德克萨斯仪器股份有限公司 | Error detection in nonvolatile logic arrays using parity |
-
2016
- 2016-11-18 CN CN201611025081.6A patent/CN106601305A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101040445A (en) * | 2005-01-22 | 2007-09-19 | 思科技术公司 | Error protecting groups of data words |
| US20140136926A1 (en) * | 2005-04-28 | 2014-05-15 | Micron Technology, Inc. | Non-systematic coded error correction |
| CN101258471A (en) * | 2005-07-15 | 2008-09-03 | Gsip有限责任公司 | Flash error correction |
| US20090070637A1 (en) * | 2006-03-07 | 2009-03-12 | Nxp B.V. | Electronic circuit with a memory matrix that stores pages including extra data |
| CN102436406A (en) * | 2010-09-15 | 2012-05-02 | 株式会社东芝 | Semiconductor device and data access method thereof |
| CN103186352A (en) * | 2011-12-30 | 2013-07-03 | 三星电子株式会社 | Method of reading data from storage device, error correction device and storage system |
| CN103973272A (en) * | 2013-01-30 | 2014-08-06 | 德克萨斯仪器股份有限公司 | Error detection in nonvolatile logic arrays using parity |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107861834A (en) * | 2017-11-06 | 2018-03-30 | 华中科技大学 | A kind of method based on wrong pre-detection skill upgrading solid state hard disc reading performance |
| CN108804025A (en) * | 2018-03-07 | 2018-11-13 | 深圳忆联信息系统有限公司 | A kind of method and solid state disk for reducing flash memory and being detained mistake |
| CN108958963A (en) * | 2018-06-01 | 2018-12-07 | 杭州电子科技大学 | A kind of NAND FLASH error control method based on LDPC and cyclic redundancy check code |
| CN111162794A (en) * | 2018-11-08 | 2020-05-15 | 北京忆芯科技有限公司 | Decoding data caching method and decoder |
| CN111162794B (en) * | 2018-11-08 | 2023-10-20 | 北京忆芯科技有限公司 | Decoding data caching method and decoder |
| WO2020199490A1 (en) * | 2019-04-01 | 2020-10-08 | 江苏华存电子科技有限公司 | Dual-mode error detection memory and dual-mode error detection method |
| CN114879916A (en) * | 2022-07-12 | 2022-08-09 | 合肥康芯威存储技术有限公司 | Method and device for managing storage unit |
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