CN108766501B - Design and verification method for fault injection of storage with EDAC fault tolerance - Google Patents
Design and verification method for fault injection of storage with EDAC fault tolerance Download PDFInfo
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Abstract
The invention discloses a memory fault injection design and verification method with EDAC fault tolerance, which respectively controls the read-write access of a data/instruction domain and a check domain in different working modes, and only enables a control signal of the read operation of the data/instruction domain to be effective when the data/instruction domain is read in a test mode, thereby realizing the test read access of the data/instruction domain; when the check domain is read, only the control signal of the read operation of the check domain is enabled to realize the test read access of the check domain, when the data/instruction domain is fault injected, only the control signal of the write operation of the data/instruction domain is enabled, when the check domain is fault injected, only the control signal of the write operation of the check domain is enabled to realize the random fault injection of the data/instruction domain and the check domain. The invention realizes independent read-write access of the data/instruction domain and the check domain, and ensures the testability of the memory after fault-tolerant design.
Description
Technical Field
The invention belongs to the technical field of integrated circuit design, and particularly relates to a design and verification method for fault injection of a storage with EDAC fault tolerance.
Background
The SEU (Single-Event-Upset) effect in the space environment is very likely to affect the digital integrated circuit components, especially the memory device, causing program execution errors, thereby causing system failure. The memory may be located on the SoC (system on chip) or external to the SoC as external memory space, but the memory controller is typically located within the SoC. Aiming at the practical application of a space environment, in order to improve the radiation resistance of an SoC main memory system, a fault-tolerant reinforcement design is required to be adopted for an on-chip memory and an off-chip memory, and because the main memory system is not reproducible and is usually coded by EDAC, the purpose of correct reproduction can be achieved by correcting most errors. By adopting the EDAC coding technology, a redundant check element memory needs to be added on the basis of the original memory to serve as a check domain. In a normal function mode, when the memory is written, the check elements do not need to be sent, the write data firstly passes through an EDAC encoder to generate corresponding check elements, and then the write data and the check elements are respectively and simultaneously written into a data/instruction domain and a check domain; when the memory is read, the read data and the corresponding check elements are read from the data/instruction domain and the check domain respectively at the same time, and enter the EDAC decoder for error detection, if the read data is error-free, the read data is only returned to the processor, and the processor does not need to concern the condition of the corresponding check elements. Thus, in normal functional mode, the check elements are transparent to the processor.
However, the fault tolerant design of memory requires verification to ensure the reliability of the design. The method mainly comprises an analysis model method, a field error data analysis method, a fault injection method and the like, wherein the fault injection is an effective method for verifying the reliability of fault-tolerant design and mainly comprises software error injection, physical error injection, simulation error injection and the like. In order to realize the purpose of arbitrarily injecting errors and observing the error-tolerant memory in real time, an error injection structure needs to be specially designed when fault tolerance design is carried out, and the requirements of subsequently verifying the correctness of the fault-tolerant structure and carrying out fault injection and verification are met.
For example, "a fault simulation system and an analysis method for single event upset" provides a fault simulation system and an analysis method for single event upset in a large-scale integrated circuit SRAM-type FPGA, which use a software and hardware combination mode to interactively complete fault injection and fault detection through an upper computer and a control board, thereby realizing the verification of the fault tolerance of the SRAM-type FPGA. However, there is not much information on how to perform the fault-tolerant design based on the error-tolerant structure, and there are documents on the error-tolerant design of the TMR structure, such as "TMR fault injection and verification method research and implementation" (computer measurement and control). In particular, how to implement the error injection design and verification of the error-tolerant memory has not been found to solve the problem through searching related patents and documents.
Disclosure of Invention
The technical problem to be solved by the present invention is to provide a design and verification method for fault injection of a storage with EDAC fault tolerance, in which, in a test mode, a data/instruction field and a check field can implement independent read-write operations, and read-write data/instructions and check elements are all completed by reading and writing corresponding registers, so that errors can be arbitrarily noted, and simultaneously, the purpose of real-time observation of the data/instructions and the check elements is achieved, thereby ensuring the testability of the storage after fault-tolerant design.
The invention adopts the following technical scheme:
a memory fault injection design and verification method with EDAC fault tolerance, which carries out different control on read-write access of a data/instruction domain and a check domain respectively in different working modes, and only enables a control signal of the read operation of the data/instruction domain to be effective when the read operation is carried out on the data/instruction domain in a test mode, thereby realizing the test read access of the data/instruction domain; when the check domain is read, only the control signal of the read operation of the check domain is enabled to realize the test read access of the check domain, when the data/instruction domain is fault injected, only the control signal of the write operation of the data/instruction domain is enabled, when the check domain is fault injected, only the control signal of the write operation of the check domain is enabled to realize the random fault injection of the data/instruction domain and the check domain.
Specifically, according to the working mode, the read-write access of the data/instruction domain and the check domain is as follows:
under a normal working mode, the control signals and the control time sequence of the read-write access of the data/instruction domain and the check domain are consistent, and the data/instruction domain and the check domain are in one-to-one correspondence; in the test mode, the data/command field and the check field need to have independent read-write access control.
Further, in a normal working mode, the control signal controls the reading and writing of the data/instruction domain and the check domain at the same time; in the test mode, if the test data/instruction domain is detected, the read-write control signal is effective to access the data/instruction domain, and the read-write access controller of the verification domain is set to be ineffective; if the test check domain is present, the read-write control signal is valid for accessing the check domain, and the read-write access controller for the data/command domain is set to be invalid.
Specifically, the reading operation on the data/instruction domain specifically includes:
under the test mode, the test mode is firstly configured to test the data/instruction, so that the control signal of the read operation of the data/instruction domain is effective, the control signal of the read operation of the check domain is shielded, the read access operation of a certain address is sent, the data/instruction of the corresponding address returns to the test read data register test _ rdata, and then the read operation is carried out on the test read data register, so that the test read access of the data/instruction domain is realized.
Specifically, the reading operation performed on the check field specifically includes:
under the test mode, a check domain test mode is firstly configured, so that a control signal of read operation of a check domain is enabled, a control signal of read operation of a data/instruction domain is shielded, read access operation of a certain address is sent, a check element corresponding to the address returns to a test read check element register test _ readac, and then the test read access of the check domain is realized by reading the test read check element register.
Specifically, the writing operation on the data/instruction domain specifically includes:
under the test mode, a mode for testing data/instructions is firstly configured, a control signal of the write operation of a data/instruction field is enabled to be valid, the control signal of the write operation of a check field is shielded, the data to be written is firstly written into a test write data register test _ wdata, then an access operation of a certain address is issued, the data in the test _ wdata register is written into a data/instruction field of a corresponding address, a check element in the corresponding check field maintains an original value, the test _ wdata register is read, the consistency of the written data is confirmed, and any error injection of the data/instruction field is realized.
Specifically, the writing operation performed on the check field specifically includes:
under a test mode, a check domain test mode is configured, so that a control signal of write operation of a check domain is enabled, a control signal of write operation of a data/instruction domain is shielded, a check element to be written is written into a test write check element register test _ legal first, then access operation of writing a certain address is sent, data in the test _ legal register is written into the check domain of a corresponding address, a value in the corresponding data/instruction domain is kept unchanged, read operation is carried out on the test _ legal register, consistency of the written check element is confirmed, and any error injection of the check domain is achieved.
Specifically, selecting the data/instruction domain to perform fault injection on the memory with the EDAC fault tolerance specifically includes:
when the data/instruction domain is subjected to error injection, a data/instruction domain test mode needs to be configured, when the value of the corresponding address in the current data/instruction domain is known, data to be subjected to error correction is written into a test _ wdata register, write operation on the corresponding address is initiated, if the value of the corresponding address in the data/instruction domain is unknown, read operation on the same address is initiated once, the read data is recorded in the test _ rdata register, then the value in the test _ rdata register is taken out, is subjected to error correction, is written into the test _ wdata register, and write operation is initiated to inject an error into the corresponding address.
Further, selecting a check domain to perform fault injection on the memory with the EDAC fault tolerance specifically includes:
when the error is noted for the check domain, the operated registers are test _ weather and test _ readac, no extra address space needs to be allocated for the check domain, the address access to the check domain is the same as the access address of the data/instruction domain, and only under different test modes, the accessed storage areas are different.
Specifically, in the design and verification method, a corresponding password register is designed for write access of the test control register, and a corresponding password is written into the corresponding password register first, so that only one operation is performed on the test control register if the password is correct.
Compared with the prior art, the invention has at least the following beneficial effects:
the invention relates to a memory fault injection design and verification method with EDAC fault tolerance, which respectively controls the read-write access of a data/instruction domain and a check domain in different working modes, and only enables a control signal of the read operation of the data/instruction domain to be effective when the read operation is carried out on the data/instruction domain in a test mode, thereby realizing the test read access of the data/instruction domain; when the check domain is read, only the control signal of the read operation of the check domain is enabled to realize the test read access of the check domain, when the data/instruction domain is fault injected, only the control signal of the write operation of the data/instruction domain is enabled, when the check domain is fault injected, only the control signal of the write operation of the check domain is enabled to realize the random fault injection of the data/instruction domain and the check domain. The independent read-write access of the data/instruction domain and the check domain is realized, the read-write data/instruction and the check element are completed by reading and writing the corresponding register, the purpose of real-time observation of the data/instruction and the check element is realized while errors can be arbitrarily noted, the testability of the memory after fault-tolerant design is ensured, and the obtained effects are as follows:
by setting a mode configuration register programmable by a user and carrying out corresponding structural design, the read-write access control of a data/instruction domain and a check domain is ensured to be simultaneous under a normal working mode, the consistency of the data/instruction and the check element is ensured, the read-write access control of the data/instruction domain and the check domain is independent under a test mode, and a read-write access control signal is only effective to a currently configured storage domain according to whether the currently configured test data/instruction domain or the test check domain is adopted, so that the error injection of the data/instruction domain and the check domain can be respectively realized.
By designing the test write data register test _ wdata and the test check element register test _ wedac, the tester can optionally inject errors into the data/instruction domain and the check domain respectively by operating the registers in the test mode, and the fault injection mode is simple and clear.
By designing the test read data register test _ rdata and the test read check element register test _ readac, the error injection condition of the data/instruction field and the check field can be observed in real time by a tester through read access to the corresponding registers in the test mode.
By adopting the password register, when the correct password is written into the password register, the write enable of the test control register can be started, and the reliability of the test design structure is improved.
The technical solution of the present invention is further described in detail by the accompanying drawings and embodiments.
Drawings
FIG. 1 is a schematic diagram of the read/write access control structure of the memory with EDAC fault tolerance according to the present invention.
Detailed Description
The invention provides a fault injection design and verification method of a storage with EDAC fault tolerance, which is used for independently realizing the fault injection and verification of a data/instruction domain and a verification domain of a fault-tolerant storage.
The invention relates to a method for designing and verifying fault injection of a storage with EDAC fault tolerance, which comprises the following steps:
s1, performing different control on the read-write access of the data/instruction domain and the check domain in different working modes;
in a normal working mode, the control signals and the control time sequence of the read-write access of the data/instruction domain and the check domain are consistent, independent access control signals do not need to be set for the check domain, extra access addresses do not need to be distributed for the check domain, the data/instruction domain and the check domain are in one-to-one correspondence, and the same addresses as those of the data/instruction domain are used.
In test mode, the data/command field and the check field need to have independent read and write access control.
In fact, the control signals for the read-write access of the data/instruction domain and the check domain can be a set, and in a normal working mode, the control signals simultaneously control the read-write of the data/instruction domain and the check domain; in the test mode, if the test data/instruction domain is detected, the read-write control signal is effective to access the data/instruction domain, and the read-write access controller of the verification domain is set to be ineffective; if the test check domain is present, the read-write control signal is valid for accessing the check domain, and the read-write access controller for the data/command domain is set to be invalid.
S2, in the test mode, when reading the data/instruction domain, firstly configuring the mode for testing the data/instruction, aiming to make the control signal of the reading operation of the data/instruction domain effective, and shielding the control signal of the reading operation of the check domain, then sending the reading access operation of a certain address, returning the data/instruction of the corresponding address to the test reading data register test _ rdata, and then reading the test reading register test _ rdata to realize the test reading access of the data/instruction domain;
when reading operation is carried out on a check domain, a check domain test mode is configured firstly, aiming at enabling a control signal of the reading operation of the check domain to be effective, shielding a control signal of the reading operation of a data/instruction domain, sending a reading access operation of reading a certain address, returning a check element of the corresponding address to a test reading check element register test _ readac, and then carrying out the reading operation on the test _ readac register to realize the test reading access of the check domain;
s3, in the test mode, when writing operation is carried out on the data/instruction domain, firstly configuring a mode for testing the data/instruction, aiming at enabling a control signal of the writing operation of the data/instruction domain to be valid and shielding a control signal of the writing operation of the check domain, then writing the data to be written into a test write data register test _ wdata, and sending an access operation of a certain address, wherein the data in the test _ wdata register is written into the data/instruction domain of the corresponding address, the check element in the corresponding check domain maintains the original value, the test _ wdata register can be read, the consistency of the written data is confirmed, and any misinjection of the data/instruction domain is realized for the test writing operation of the data/instruction domain;
when the check domain is written, a check domain test mode is configured firstly, aiming at enabling a control signal of the write operation of the check domain to be effective, a control signal of the write operation of the data/instruction domain is shielded, a check element to be written is written into a test write check element register test _ legal first, then an access operation of writing a certain address is sent, data in the test _ legal register is written into the check domain of a corresponding address, the value in the corresponding data/instruction domain is kept unchanged, the test _ legal register can be read, the consistency of the written check element is confirmed, and any error injection of the check domain is realized for the test write operation of the check domain;
s4, when fault injection is carried out on the memory with the EDAC fault tolerance, errors can be injected into the data/instruction domain and/or the check domain;
when the data/instruction field is subjected to error injection, a data/instruction field test mode needs to be configured, if the value of the corresponding address in the current data/instruction field is known, the data to be subjected to error correction is written into a test _ wdata register, and the write operation of the corresponding address is initiated, if the value of the corresponding address in the data/instruction field is unknown, the read operation of the same address can be initiated once, the read data can be recorded in the test _ rdata register, then the value in the test _ rdata register is taken out, the error is corrected, the data is written into the test _ wdata register, and the write operation is initiated to inject the error into the corresponding address.
When an error is injected into the check field, the flow is consistent, except that the registers of the operation are test _ weather and test _ restore. It should be noted that no extra address space needs to be allocated to the check domain, the address access to the check domain is the same as the access address of the data/instruction domain, and only in different test modes, the accessed storage areas are different;
s5, based on the consideration of reliability, in order to prevent system faults caused by human misoperation and space radiation environment, a corresponding password register is specially designed for the write access of the test control register, namely, a corresponding password must be written into the corresponding password register firstly, and the password is correct, so that the test control register can be operated once, and the reliability of the test design structure is improved.
The invention is based on the design structure of fault injection, so that the data/instruction domain and the check domain have independent access paths, the data/instruction domain and the check domain can be injected with errors respectively at will, and the purpose that the data/instruction domain and the check domain have testability is achieved. Meanwhile, the data in the data/instruction domain and the check domain can be checked for error injection conditions of the data/instruction domain and the check domain through reading the test _ rdata register and the test _ readac register respectively, so that the purpose of real-time observation is achieved.
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of the embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to FIG. 1, a read/write access control architecture for EDAC tolerant memory is shown. In a normal function mode, when a system sends a write operation to a memory, write data sys _ data is encoded by Edac to generate a corresponding check element wedac, a write enable signal Wen sent by the system enables a write enable Wen _ data of a data/instruction domain and a write enable Wen _ Edac signal of a check domain to be valid at the same time, and the sys _ data and the wedac are written into the data/instruction domain and the check domain respectively at the same time; when the system issues a read operation to the memory, the system issues a read enable signal Oen to assert the read enable Oen _ data of the data/command field and the read enable Oen _ Edac signal of the check field simultaneously, read out the data rdata and the check element readac from the data/command field and the check field respectively, and perform Edac decoding, and the decoded result and the corrected data are returned to the system.
In the test mode, if the test data/instruction field is configured, when the test write operation is carried out, the written data comes from the test write data register test _ wdata, because only the test data/instruction field is tested, the check field is kept unchanged, the Edac coding is not required, only the write enable signal of the data/instruction field is valid, and the write enable of the check field is shielded; in a test read operation, the system read enable signal Oen asserts the read enable signal Oen _ data of the data/command field, the read enable signal of the check field is masked, and the read data is written into the test read data register test _ rdata.
In the test mode, if the test check domain is configured, when write operation is carried out, the written data comes from the test write check element register test _ weather, the Edac coding module is not enabled, only the write enable signal Wen _ Edac of the check domain is valid, and the write enable of the data/instruction domain is shielded; in a test read operation, the system read enable signal Oen asserts the verify field read enable signal Oen _ edac, the data/command field read enable signal is masked, and the read data is written into the test read verify meta register test _ readac.
The invention has been applied to an SoC compatible with the SPARC V8 structure fault-tolerant processor, and the memory controller of the SoC main memory system uses the fault injection design structure and the verification method in the invention. When the memory is in a test mode, the data/instruction field and the check field can realize independent read-write operation, and the read-write data/instruction and the check element are completed by reading and writing the corresponding register, so that the purpose of real-time observation of the data/instruction and the check element can be realized while errors can be arbitrarily noted, and the testability of the memory after fault-tolerant design is ensured.
The above-mentioned contents are only for illustrating the technical idea of the present invention, and the protection scope of the present invention is not limited thereby, and any modification made on the basis of the technical idea of the present invention falls within the protection scope of the claims of the present invention.
Claims (7)
1. A design and verification method for fault injection of a storage with EDAC fault tolerance is characterized in that different control is respectively carried out on read-write access of a data/instruction domain and a check domain in different working modes, and in a test mode, when read operation is carried out on the data/instruction domain, only a control signal of the read operation of the data/instruction domain is enabled to be effective, so that test read access of the data/instruction domain is realized; when reading operation is carried out on the check field, only the control signal of the reading operation of the check field is enabled to be effective, test reading access of the check field is realized, when fault injection is carried out on the data/instruction field, only the control signal of the writing operation of the data/instruction field is enabled, and the specific steps of writing operation on the data/instruction field are as follows: under a test mode, a mode for testing data/instructions is configured firstly, a control signal of write operation of a data/instruction field is enabled to be valid, the control signal of write operation of a check field is shielded, data to be written is written into a test write data register test _ wdata firstly, then access operation of a certain address is issued, the data in the test _ wdata register is written into a data/instruction field of a corresponding address, a check element in the corresponding check field maintains an original value, read operation is performed on the test _ wdata register, consistency of the written data is confirmed, any error injection of the data/instruction field is realized, and the write operation on the check field is specifically that:
under a test mode, a check domain test mode is configured first, so that a control signal of a write operation of a check domain is enabled to shield a control signal of a write operation of a data/instruction domain, a check element to be written is written into a test write check element register test _ legal first, then an access operation of writing a certain address is issued, data in the test _ legal register is written into the check domain of a corresponding address, a value in the corresponding data/instruction domain is maintained unchanged, the test _ legal register is read, consistency of the written check element is confirmed, any fault injection of the check domain is realized, when fault injection is performed on the check domain, only the control signal of the write operation of the check domain is enabled, any fault injection of the data/instruction domain and the check domain is realized, and selecting the data/instruction domain to perform fault injection on a memory with EDAC fault tolerance specifically comprises the following steps: when the data/instruction domain is subjected to error injection, a data/instruction domain test mode needs to be configured, when the value of the corresponding address in the current data/instruction domain is known, data to be subjected to error correction is written into a test _ wdata register, write operation on the corresponding address is initiated, if the value of the corresponding address in the data/instruction domain is unknown, read operation on the same address is initiated once, the read data is recorded in the test _ rdata register, then the value in the test _ rdata register is taken out, is subjected to error correction, is written into the test _ wdata register, and write operation is initiated to inject an error into the corresponding address.
2. The method for design and verification of memory fault injection with EDAC fault tolerance according to claim 1, wherein the read and write accesses of the data/command field and the check field are specifically as follows according to the operation mode:
under a normal working mode, the control signals and the control time sequence of the read-write access of the data/instruction domain and the check domain are consistent, and the data/instruction domain and the check domain are in one-to-one correspondence; in the test mode, the data/command field and the check field need to have independent read-write access control.
3. The method for designing and verifying fault injection of storage with EDAC fault tolerance according to claim 1 or 2, wherein in normal operation mode, the control signal controls the reading and writing of the data/command field and the check field simultaneously; in the test mode, if the test data/instruction domain is detected, the read-write control signal is effective to access the data/instruction domain, and the read-write access controller of the verification domain is set to be ineffective; if the test check domain is present, the read-write control signal is valid for accessing the check domain, and the read-write access controller for the data/command domain is set to be invalid.
4. The method for design and verification of memory fault injection with EDAC fault tolerance according to claim 1, wherein the read operation on the data/command field specifically comprises:
under the test mode, the test mode is firstly configured to test the data/instruction, so that the control signal of the read operation of the data/instruction domain is effective, the control signal of the read operation of the check domain is shielded, the read access operation of a certain address is sent, the data/instruction of the corresponding address returns to the test read data register test _ rdata, and then the read operation is carried out on the test read data register, so that the test read access of the data/instruction domain is realized.
5. The method for design and verification of memory fault injection with EDAC fault tolerance according to claim 1, wherein the read operation on the check field specifically comprises:
under the test mode, a check domain test mode is firstly configured, so that a control signal of read operation of a check domain is enabled, a control signal of read operation of a data/instruction domain is shielded, read access operation of a certain address is sent, a check element corresponding to the address returns to a test read check element register test _ readac, and then the test read access of the check domain is realized by reading the test read check element register.
6. The method for design and verification of fault injection of a storage with EDAC fault tolerance according to claim 1, wherein the selecting the check domain to inject the fault into the storage with EDAC fault tolerance specifically comprises:
when the error is noted for the check domain, the operated registers are test _ weather and test _ readac, no extra address space needs to be allocated for the check domain, the address access to the check domain is the same as the access address of the data/instruction domain, and only under different test modes, the accessed storage areas are different.
7. The method as claimed in claim 1, wherein the design and verification method comprises designing a corresponding password register for write access of the test control register, writing a corresponding password into the corresponding password register, and performing one operation on the test control register only if the password is correct.
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| CN111243657A (en) * | 2020-03-03 | 2020-06-05 | 南京邮电大学 | Effective random fault injection method for memory circuit |
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