WO2021175099A1 - Procédé d'injection de défaut aléatoire efficace pour circuit de mémoire - Google Patents

Procédé d'injection de défaut aléatoire efficace pour circuit de mémoire Download PDF

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Publication number
WO2021175099A1
WO2021175099A1 PCT/CN2021/075704 CN2021075704W WO2021175099A1 WO 2021175099 A1 WO2021175099 A1 WO 2021175099A1 CN 2021075704 W CN2021075704 W CN 2021075704W WO 2021175099 A1 WO2021175099 A1 WO 2021175099A1
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Prior art keywords
nodes
random
fault injection
file
faulty
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PCT/CN2021/075704
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English (en)
Chinese (zh)
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蔡志匡
余昊杰
周正
王荧
王子轩
谢祖帅
刘璐
郭宇锋
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南京邮电大学
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Publication of WO2021175099A1 publication Critical patent/WO2021175099A1/fr

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor

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  • the invention relates to the field of ultra-large-scale digital integrated circuit testing, in particular to an effective random fault injection method of a memory circuit.
  • Static Random Access Memory is one of the key modules of mobile processors. SRAM is fast, has a small capacity, and has good compatibility. It is generally used as embedded memory, that is, cache or temporary storage. Device. To meet the ever-increasing demand for performance and power consumption, low-voltage SRAM design is gradually becoming a research hotspot in the industry. In order to improve the overall performance of the system-on-chip, reducing the power supply voltage is an effective means to improve the energy efficiency of the circuit. However, when the power supply voltage is lower than the threshold voltage, the influence of process parameter changes on the stability of the memory cell and the change of the critical path delay also increases sharply. Under advanced technology, SRAM will have more and more complicated failure models.
  • the SRAM circuit is different from the general digital circuit. SRAM is composed of a high-density storage array. According to different needs, the circuit structure is also different. Its failure rate is higher and the type of failure is more complicated. Therefore, the test of SRAM becomes more and more complicated. It has become more difficult, and due to the limitations of various technologies, whether the traditional test algorithm can really detect the failure of the memory circuit and the coverage of the failure has not been effectively verified. In the field of memory testing, there has always been a lack of a feasible method of memory fault injection to verify the test algorithm; the current fault injection methods used in engineering are software injection faults, Verilog-based fault injections and chip faults in the FPGA machine. The above methods Each has its own advantages and disadvantages, and the limitations are too high.
  • the purpose of the present invention is to provide an effective random fault injection method for a memory circuit, which can achieve random fault injection node positions, random number of injection nodes, and random injection resistance values by performing at the circuit simulation level and when injecting faults.
  • the existing methods have strong randomness, which reduces the complexity of fault injection while verifying the effectiveness of the algorithm.
  • the present invention provides an effective random fault injection method for a memory circuit, and the method steps are as follows:
  • Step 1 Use Perl language to extract all the nodes that may fail, modify the names of all failed nodes, and generate a new file;
  • Step 2 Randomly select one or more faulty nodes in the node file, and insert random resistors with resistance values at the nodes;
  • Step 3 After inserting the resistor, a new memory netlist file with random fault injection is generated.
  • a further improvement is that when extracting faulty nodes in the first step, the storage netlist is first analyzed, and all the circuit nodes that may be faulty in the storage unit are extracted through Perl language, and the names of all faulty nodes are modified according to the predetermined naming rules, which is convenient During fault injection, the randomly selected faulty node is located in the original netlist, and a new faulty node file is generated. Each line in the file is a faulty node.
  • a further improvement is that the method for selecting faulty nodes in the second step is as follows: randomly select p faulty nodes from the faulty node file, and determine the position of the randomly selected node in the original netlist through naming rules, and inject a resistor with random resistance ; If p nodes are selected, the resistance values of the injection resistors are r 1 ... r p , and the size of each resistance is random.
  • a further improvement is that the resistors injected in the second step are named R fau1 ...R faup , which correspond to two port nodes and random resistance values r 1 ...r p, and the above information is added to the memory cell module to generate a new The storage netlist file.
  • the beneficial effects of the present invention the randomness and comprehensiveness of the fault injection are taken into account while the fault is injected, resistors are added to the memory circuit structure, and the circuit defects that may occur in the manufacturing engineering of the circuit are simulated, and the validity of the algorithm is verified at the same time , Verified the fault coverage of the algorithm.
  • the fault injection of the present invention is performed on the memory spice netlist, which improves the executable of the fault injection, enhances the relevance of the fault injection in practice, and reduces the complexity of subsequent simulation verification.
  • Fig. 1 is a flow chart of the random fault injection method of the present invention.
  • FIG. 2 is a structural diagram of the SRAM of the present invention.
  • Fig. 3 is a diagram of node insertion resistance based on the 6T SRAM circuit of the present invention.
  • Fig. 4 is a block diagram of the verification structure after fault injection is completed based on the SRAM example of the present invention.
  • Fig. 5 is a waveform diagram of the random fault injection verification based on the 6T SRAM cell of the present invention.
  • this embodiment provides an effective random fault injection method for a memory circuit, and the method steps are as follows:
  • Step 1 Use Perl language to extract all the nodes that may fail, modify the names of all failed nodes, and generate a new file;
  • Step 2 Randomly select one or more faulty nodes in the node file, and insert random resistors with resistance values at the nodes;
  • Step 3 After inserting the resistor, a new memory netlist file with random fault injection is generated.
  • the method for selecting the faulty node in the second step is as follows: randomly select p faulty nodes from the faulty node file, and determine the position of the randomly selected node in the original netlist by naming rules, and inject a resistor with random resistance; if the node is selected If the number is p, the resistance values of the injection resistors are r 1 ... r p , and each resistance value is random.
  • the resistors injected in the second step are named R fau1 ...R faup , which correspond to two port nodes and random resistance values r 1 ...r p, add the above information to the memory cell module to generate a new memory netlist document.
  • This embodiment improves on the technical problem of memory fault injection, and innovatively implements an effective random fault injection method for memory. While fault injection, the randomness and comprehensiveness of fault injection are considered.
  • the fault injection in this embodiment is performed on the memory spice netlist, which improves the executable of fault injection, enhances the relevance of fault injection in practice, and reduces the complexity of subsequent simulation verification.
  • Figure 1 shows a flow chart of the random fault injection method of this embodiment. As shown in the figure, three steps are required to complete the random fault injection, including fault node extraction, random fault injection, and random fault injection verification.
  • the extraction of faulty nodes includes the location of possible faulty circuit nodes in the memory, extracting all circuit nodes and modifying the names of circuit nodes, generating a circuit node list file, and each line in the file corresponds to a circuit node to complete the extraction of faulty nodes; random fault injection is the implementation
  • the core module of the example includes the selected fault nodes randomly, the number of selected nodes is random, and the injection resistance value is random; different fault nodes at p (p>0) are randomly selected in the node file, and the resistance value of each node is injected Random; as shown in Figure 1, when randomly selecting different nodes at p, each time the selection is completed, it is necessary to determine whether the failure node is the same as the previous selection.
  • FIG. 2 is a structure diagram of the static random access memory.
  • a complete memory system includes an address decoder, a timing control unit, a column selector, a sensitive amplifier, and a data buffer unit. And a storage array, where the storage array is a plurality of neatly arranged storage units. As shown in the figure, the circuit structure diagram of the storage unit can be seen.
  • Figure 3 is based on the 6T SRAM circuit node insertion resistance diagram. As shown in the figure, according to the description of the memory netlist file, each MOS device name and port node name are marked. When the circuit node is extracted, the circuit node name is modified. The node is the three ports of each MOS device, so the device name is added before the node name.
  • the corresponding node location can be located by the device name, as shown in the figure, when the node name is randomly selected as MNPg-b
  • the fault injection location can be located at the bb node of the MNPg-b device according to the naming rule, and the resistance at the fault node is injected with a resistance value of r 1 and a resistor named R fau1.
  • FIG. 4 is a block diagram of the verification structure after fault injection is completed based on the SRAM example of this embodiment.
  • the BIST circuit includes modules such as state machine, address generator, data generator, and algorithm controller, and uses March2 algorithm to generate test vector tests.
  • Memory circuit The test output is compared with the expected data through a comparator. After the comparison, the tst-done signal jumps to 1. If the comparison data is consistent, the fail-h signal is 0, otherwise it jumps to 1. This experiment is based on a mixed simulation environment to verify the feasibility of the fault injection method.
  • the BIST test circuit is written in Verilog sentences and simulated by VCS.
  • the SRAM to be tested is a cdl netlist and simulated by HSIM.
  • Figure 5 is based on the random fault injection verification waveform of the 6T SRAM cell. The experimental results are compared through the hybrid simulation test waveform. Among them, (a) is the waveform of the original netlist test result of the memory. Observe the tst-done and fail-h in the figure.
  • Figure 6 (b) is the same simulation environment, after the random fault is injected Generate the netlist file test result waveform diagram, observe the tst-done and fail-h waveform transitions, and find that when the tst-done signal is still 0, the fail-h signal has jumped to 1, indicating that the circuit is faulty. Further analysis found that the corresponding test step when the waveform jumps is w1r1, and the injected fault node is R fau1 . The fault manifestation is a conversion failure, which cannot be converted from 0 to 1, which is consistent with the waveform check result of the algorithm, effectively verifying this embodiment The feasibility of the method.

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Abstract

La présente invention concerne un procédé d'injection de défaut efficace pour un circuit de mémoire. Le procédé comprend les étapes suivantes : étape 1, extraction de tous les nœuds défectueux possibles avec un langage Perl, modification des noms de tous les nœuds défectueux, et génération d'un nouveau fichier ; étape 2, sélection de manière aléatoire d'un ou de plusieurs nœuds défectueux dans le fichier de noeud, et insertion de résistances aléatoires de résistance dans les nœuds ; et l'étape 3, la génération d'un nouveau fichier de liste d'interconnexions de mémoire avec une injection de défaut aléatoire achevée après l'insertion de la résistance. Selon le procédé, la liste d'interconnexions après l'injection de défaut peut être générée, et une injection de défaut aléatoire est réalisée. Le procédé d'injection de défaut aléatoire est caractérisé en ce que la position de noeud du circuit d'injection de défaut est aléatoire, la quantité d'injection de défaut est aléatoire, et la valeur de résistance de la résistance d'injection est aléatoire, et le procédé est un procédé réalisable, et peut vérifier efficacement la couverture de défaut d'un algorithme de test.
PCT/CN2021/075704 2020-03-03 2021-02-07 Procédé d'injection de défaut aléatoire efficace pour circuit de mémoire WO2021175099A1 (fr)

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CN111243657A (zh) * 2020-03-03 2020-06-05 南京邮电大学 一种有效的存储器电路随机故障注入方法
CN112071355A (zh) * 2020-11-12 2020-12-11 南京邮电大学 一种提高故障覆盖率的自适应bist测试方法

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