CN112329374B - Single event effect rapid simulation method for large-scale circuit - Google Patents
Single event effect rapid simulation method for large-scale circuit Download PDFInfo
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Abstract
The invention provides a single event effect rapid simulation method for a large-scale circuit, which can obviously reduce the time overhead of large-scale simulation on the premise of ensuring the single event effect representation precision. The simulation method comprises the following steps: step 1) selecting an analyzed circuit and carrying out simulation related setting; step 2) extracting and editing files required by simulation based on the circuit netlist file, wherein the files comprise a transistor-level netlist containing fault injection, a gate-level/RTL-level/behavioral-level netlist without fault injection, an a2d file describing a digital-to-analog conversion interface, a result measurement file and a testbench file; step 3) carrying out simulation and digital mixed simulation, analyzing a simulation result obtained by a result measurement file in the simulation, and obtaining the response condition of the circuit to the single event effect under the condition of a specified fault injection range; step 4), traversing and judging; and 5) carrying out area equivalent analysis.
Description
Technical Field
The invention belongs to the field of radiation effect simulation, and relates to a single event effect rapid simulation method for a large-scale circuit.
Background
The Single Event Effect (SEE) is a radiation effect in which a Single high-energy particle in the universe is incident on a sensitive region of a semiconductor device, causing abnormal change of the state of the device. When the spacecraft works in the space, electronic components of the spacecraft are often influenced by a single event effect to break down, and even cause permanent damage to the system in serious cases. With the further development of the integrated circuit industry and the aerospace industry, the single event effect becomes an important factor for restricting the reliability of aerospace electronic components.
The single event effect resistance of aerospace electronic components is usually verified by adopting a ground experiment mode, and the mode has the problems of resource shortage, high cost, limited particle energy and the like, so that the development of a circuit-level single event effect simulation method research has important significance for the development and evaluation of an aerospace electronic system.
The existing circuit-level single event effect simulation technology generally adopts a single transistor-level netlist, and simulates the action process of high-energy particles and a chip through a simulator. The method has high simulation precision, and is suitable for researching the action mechanism of the single event effect in the circuit and evaluating the single event effect resistance of the circuit, such as:
chinese patent document CN108363894A discloses a circuit-level single event effect simulation platform, which can support large-scale circuits above ten thousand gate level to perform single event effect simulation analysis. However, in terms of simulation speed, the single event effect simulation technology is difficult to meet the simulation requirements of large-scale digital integrated circuits.
Disclosure of Invention
The invention aims to overcome the defects of the existing circuit-level single event effect simulation technology, provides a single event effect rapid simulation method for a large-scale circuit, and aims to remarkably reduce the time overhead of large-scale simulation on the premise of ensuring the single event effect representation precision.
The concept and principle of the invention are as follows:
for circuit level single event effect simulation, because the traditional analog simulation adopts a transistor level netlist, the used circuit models are the most basic elements and single tubes, and the I/V relation of each node is calculated according to the time relation during simulation, the simulation precision of the method is highest, but the simulation speed is difficult to meet the simulation requirement of a large-scale digital integrated circuit, and the digital simulation is performed at gate level/RTL level/action level, although the simulation precision is not as high as that of the analog simulation, the method has the advantages of high speed, support of large-scale circuit simulation and the like. In order to seek a good compromise between the accuracy and the speed of the simulation, the invention provides a single event effect hybrid simulation idea.
To achieve the above object, the present invention provides the following solutions:
step 1) simulation setup
Selecting an analyzed circuit, and carrying out simulation related setting, including fault injection setting, simulation time setting, measurement node setting and simulation times setting;
step 2) netlist extraction and editing
Extracting and editing files required by simulation based on the circuit netlist file according to the setting of the step 1), wherein the files comprise a transistor-level netlist containing fault injection, a gate-level/RTL-level/behavioral-level netlist without fault injection, an a2d file describing a digital-to-analog conversion interface, a result measurement file and a testbench file;
step 3) hybrid simulation and analysis
According to the simulation file extracted in the step 2), carrying out analog and digital mixed simulation under the simulation time set in the step 1), analyzing a simulation result obtained by a result measurement file in the simulation, and obtaining the response condition of the circuit to the single event effect under the condition of a specified fault injection range;
step 4) ergodic judgment
Judging whether the fault injection range is completely traversed or not; if not, replacing the fault injection setting, and skipping to the step 2); if yes, jumping to the step 5);
step 5) area equivalent analysis
And (4) according to the relation among the area of the fault injection range, the area of the sensitive part in the fault injection range and the area of the whole circuit, and according to the response condition of the circuit to the single event effect under different fault injection ranges obtained in the step 3) for multiple times, completing the high-speed and high-precision single event effect simulation analysis of the whole circuit through area equivalent analysis.
Based on the above scheme, the invention further optimizes as follows:
the fault injection is realized by adding the fault injection to a circuit netlist in a form of a piecewise linear current source (PWL) in SPICE syntax; the specific numerical values are based on the correlation results obtained from the device-level simulation.
The fault injection adopts a random injection mode of simulating one fault at a time, namely, one circuit node in a fault injection range is randomly selected and one time node in an injection time range is randomly selected for injection in each simulation.
The parameters related to the fault injection setting comprise a fault injection range, an injection time range, an LET value and the like, wherein the parameters are limited by the instantiation of the netlist by taking a module as a unit, and the fault injection range is at a minimum module level.
The circuit netlist file includes a transistor-level netlist of the full circuit, a gate-level/RTL-level/behavioral-level netlist of the full circuit, and node information of the full circuit.
In the step 2), all the files are generated through scripts written by Perl and Shell languages. In the step 3), a script written by Perl and Shell languages is used for completing a simulation task and result statistics; and meanwhile, result analysis is realized, and the fault injection position, time and circuit error condition when the circuit has an error are recorded.
The hybrid simulation described above specifies a pattern for the digital top level, verilog-top, so the stimulus in the testbench file is a digital stimulus.
The sensitivity response of the single event effect refers to the statistics of the single event soft error rate, and the related parameters comprise a fault injection range, fault generation times, simulation times and the like.
The hybrid simulation may employ an analog and digital simulator supporting a hybrid simulation mode, for example, simulation using the analog simulator FineSim in conjunction with the digital simulator VCS.
The steps 1) to 3) are also applicable to the single event sensitivity of different modules/paths in a qualitative analysis circuit, for example, the single event sensitivity analysis aiming at the maximum path of the combinational logic delay;
the area size of all the circuits is obtained by analysis of tools such as Layout L, Design Compiler, etc.
The number of injected particles traversed by the hybrid simulation each time is set according to the proportional relation between the areas of all sensitive parts in the fault injection range and the full circuit area, and the relation is as follows:
N i ＝S i /S·N
the total number of injected simulation particles is:
wherein N is i Injecting the number of the currently traversed simulation particles, S i The area of the sensitive part in the currently traversed fault injection range, S is the total circuit area, N is the actual total particle injection number, N s And n is the number of the total simulation particle injection and the traversal times.
The area equivalent analysis obtains the soft error rate of the whole circuit and the relation between each parameter as follows:
e is the soft error rate of the full circuit, n is the number of traversals, M i For the current traversalAnd (4) the error times, wherein N is the actual total particle injection number.
The invention has the following technical effects:
the single event effect simulation analysis method can perform single event effect simulation analysis of circuits with the size not smaller than a million gates, can qualitatively analyze the single event effect sensitivity of a certain module/path in the circuit, integrally analyzes the response condition of the whole circuit to the single event effect, and can be used as a powerful mode for testing the reliability of electronic components.
Compared with a single event effect ground experiment, the method has the advantages of short period and low cost, and can accurately position the fault injection position and time causing circuit errors; compared with the traditional circuit-level single event effect simulation technology, the method has the advantages of large scale, high speed and wider application prospect.
Drawings
FIG. 1 is a schematic diagram of a simulation process according to the present invention.
FIG. 2 is a flow diagram of netlist extraction and editing and hybrid simulation and analysis.
FIG. 3 is a schematic diagram of an original circuit of a SiP system with a Leon processor as a core according to an embodiment of the present invention.
Fig. 4 is a schematic diagram of a hybrid circuit of a SiP system with a Leon processor as a core according to an embodiment of the present invention.
Detailed Description
The single event effect rapid simulation method for large-scale circuits according to the present invention is further described in detail below with reference to the accompanying drawings and embodiments.
As shown in fig. 1, an overall process of a single event effect rapid simulation method for a large-scale circuit includes:
step 1) selecting an analyzed circuit, and carrying out simulation related setting, including fault injection setting, simulation time setting, measurement node setting, simulation frequency setting and the like;
after the relevant setting in step 1) is completed, performing step 2) netlist extraction and editing shown in fig. 2 to step 3) hybrid simulation and analysis flow: firstly, distinguishing an injection module from other modules according to the fault injection range set in the step 1); secondly, generating measurement statements (the injection module is a MEAS statement, and the other modules are $ DISPLAY statements) corresponding to the nodes to be measured of the injection module and the other modules according to the nodes to be measured set in the step 1) through a Perl script, and respectively adding the measurement statements into a transistor-level netlist and a gate-level/RTL-level/behavioral-level netlist; then, carrying out primary hybrid simulation according to the simulation time set in the step 1) to obtain a voltage value or a logic value of each measurement node of the system during fault-free injection, wherein the voltage value or the logic value is used as a standard value during normal operation of the system; then writing a fault injection file in a transistor-level netlist of the injection module through a Perl script in a mode of randomly selecting injection nodes and randomly selecting injection time, and performing secondary hybrid simulation to obtain a voltage value or a logic value of each measurement node of the system during fault injection; and finally, according to the simulation times set in the step 1), carrying out the processes of random injection and secondary simulation for multiple times, comparing the simulation times with the standard value obtained by primary simulation, and recording the simulation times and the error times of each part of the system, so that the response condition of the circuit to the single event effect under the condition of specifying the fault injection range can be realized.
The hybrid simulation can specify that the top-level module is digital or analog, namely verilog-top and spice-top, the difference between them is mainly that the testbench file and a2d file are different in relative settings, and because the top-level module also participates in the simulation process, the simulation speed of the mode adopting the top-level being verilog-top is slightly higher than that of the mode adopting the top-level being spice-top. Fig. 3 and 4 are schematic diagrams of an original circuit and a hybrid circuit of an SiP system with a Leon processor as a core according to an embodiment of the present invention, and the original circuit and the hybrid circuit are composed of the Leon processor, an instruction SRAM, a data SRAM, an initialization SRAM, and a part of peripheral circuits, wherein the fault injection range set in fig. 4 is an instruction SRAM module, and the top layer of the instantiation is a verilog-top mode.
The embodiment of fig. 4 proceeds to step 3) as described above, i.e., the sensitivity of single event effect of the command SRAM in the circuit is qualitatively analyzed. In order to verify the single event effect characterization accuracy of the hybrid simulation and the speed advantage of the hybrid simulation, 1000 times of simulation of 1 random fault injection is performed on the hybrid simulation, and the probability of system errors caused by the single event effect and the probability of transmission of errors of the command SRAM output end to other positions of the system are counted, as shown in table 1.
TABLE 1
The results of single transistor level simulations under the same conditions were also compared, as shown in table 2.
TABLE 2
It can be seen that in the circuit of the embodiment, the response of the circuit to the single event effect in the hybrid simulation is almost the same as that of the single transistor-level simulation. Meanwhile, in terms of time overhead, the time required by 10 times of simulation of the hybrid simulation and the single-transistor-level simulation is respectively obtained, the average time required by the hybrid simulation for a single time is calculated to be about 131.5s, and the average time required by the single-transistor-level simulation is 761.1s, namely in the embodiment, compared with the single-transistor-level simulation, the simulation speed of the hybrid simulation is improved by nearly 6 times, and a good acceleration effect is achieved.
And then, step 4) traversing judgment, dividing the circuit according to simulation needs, and specifying the traversing times, wherein the principle is that the simulation speed is improved as much as possible, so that the transistor-level part of the circuit needs to be reduced as much as possible, and the circuit is limited by the instantiation of the netlist by taking a module as a unit, and the module is taken as the minimum unit.
The simulation times of each traversal are set according to the proportional relation between the areas of all sensitive parts in the fault injection range and the full circuit area, and the relation is as follows:
N i ＝S i /S·N
according to the device-level simulation result in the existing literature, the sensitive part is defined as the drain terminal of all NMOS devices.
The total number of injected simulation particles is:
wherein N is i Injecting the number of the currently traversed simulation particles, S i The area of the sensitive part in the currently traversed fault injection range, S is the total circuit area, N is the actual total particle injection number, N s And n is the number of the injected total simulation particles and the traversal times.
Through the area equivalent analysis in the step 5), the soft error rate of the whole circuit is obtained, and the relation between each parameter is as follows:
where E is the soft error rate of the full circuit, n is the number of traversals, M i And N is the actual total particle injection number, which is the error frequency of the current traversal.
This relationship is obtained by combining the following relationships:
namely, the soft error rate of the full circuit is the sum of the generic terms of the product of the soft error rate of each traversal and the proportion of the sensitive part occupying the full circuit area in the fault injection range.
A very small number of combinational logic circuits among the modules are ignored, and the occupied area proportion is as follows:
where E is the soft error rate of the full circuit, S i The area of the sensitive part in the fault injection range traversed currently, S is the full circuit area, E i For the soft error rate of the current traversal, n is the traversal number, M i For the number of errors currently traversed, N i Number of injected particles, N, for the currently traversed simulation k For the current traversal of the actual number of particles, S k Fault injection range area for previous traversal, N is actual total particle injectionNumber of entries, S l To implant the area occupied by the uncovered circuitry.
Claims (10)
1. A single event effect rapid simulation method for a large-scale circuit is characterized by comprising the following steps:
step 1) simulation setup
Selecting an analyzed circuit, and carrying out simulation related setting, including fault injection setting, simulation time setting, measurement node setting and simulation times setting;
step 2) netlist extraction and editing
Extracting and editing files required by simulation based on the circuit netlist file and according to the setting of the step 1), wherein the files comprise a transistor-level netlist containing fault injection, a gate-level/RTL-level/behavioral-level netlist without fault injection, an a2d file describing a digital-to-analog conversion interface, a result measurement file and a testbench file;
step 3) hybrid simulation and analysis
According to the simulation file extracted in the step 2), carrying out analog and digital mixed simulation under the simulation time set in the step 1), analyzing a simulation result obtained by a result measurement file in the simulation, and obtaining the response condition of the circuit to the single event effect under the condition of a specified fault injection range;
step 4) ergodic judgment
Judging whether the fault injection range is completely traversed or not; if not, replacing the fault injection setting, and skipping to the step 2); if yes, jumping to the step 5);
step 5) area equivalent analysis
And (3) according to the relation among the area of the fault injection range, the area of the sensitive part in the fault injection range and the area of the whole circuit, and according to the response condition of the circuit to the single event effect under different fault injection ranges obtained in the step 3) for multiple times, completing the high-speed and high-precision single event effect simulation analysis of the whole circuit through area equivalent analysis.
2. The single event effect rapid simulation method for large-scale circuits according to claim 1, wherein during the hybrid simulation process of step 3), the fault injection is implemented by adding a piecewise linear current source (PWL) form in SPICE syntax to the circuit netlist.
3. The single event effect rapid simulation method for large-scale circuits according to claim 1, wherein in the hybrid simulation process of step 3), the fault injection adopts a random injection mode for simulating one fault at a time, that is, one circuit node in a fault injection range is randomly selected for each simulation, and one time node in an injection time range is randomly selected for injection.
4. The single event effect rapid simulation method for the large-scale circuit according to claim 1, wherein the relevant parameters of the fault injection setting in the step 1) comprise a fault injection range, an injection time range and an LET value.
5. The single event effect rapid simulation method for the large-scale circuit according to claim 1, wherein in the step 2), all files are generated through scripts written by Perl and Shell languages; and 3) completing a simulation task and result statistics by using a script written by Perl and Shell languages, realizing result analysis, and recording fault injection positions, time and circuit error conditions when the circuit has errors.
6. The method for single event effect rapid simulation for large-scale circuits according to claim 1, wherein the hybrid simulation in step 3) is specified as a digital top-level (verilog-top) mode, and accordingly, the stimulus in the testbench file is a digital stimulus.
7. The single event effect rapid simulation method for large-scale circuits according to claim 1, wherein the response condition of the circuit to the single event effect in step 3) refers to statistics of single event soft error rate, and the related parameters include fault injection range, fault generation times and simulation times.
8. The single event effect rapid simulation method for large-scale circuits according to claim 1, wherein the hybrid simulation in step 3) is a simulation performed by using an analog simulator FineSim in combination with a digital simulator VCS.
9. The method for single event effect simulation of large scale circuit according to claim 1, wherein the area size of the analyzed circuit is analyzed by a Layout L or Design Compiler software tool.
10. The single event effect rapid simulation method for large-scale circuits according to claim 4, wherein the number of injected particles in each traversal of the hybrid simulation is set according to a proportional relationship between the areas of all sensitive parts in the fault injection range and the full circuit area, and the relationship is as follows:
N i ＝S i /S·N
the total number of the simulated particle injections is:
wherein N is i Injecting the number of the currently traversed simulation particles, S i The area of the sensitive part in the currently traversed fault injection range, S is the total circuit area, N is the actual total particle injection number, N s The number of injected total simulation particles is n, and the traversal times is n;
the area equivalent analysis obtains the soft error rate of the whole circuit and the relation of each parameter as follows:
wherein E is the soft error rate of the full circuit, n is the traversal number, M i And N is the actual total particle injection number, which is the error frequency of the current traversal.
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| CN108363894B (en) * | 2018-05-04 | 2021-05-11 | 西安电子科技大学 | Circuit-level single event effect simulation platform |
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