CN212364515U - Automatic QC device of SOC chip - Google Patents

Abstract

The utility model provides an automatic QC device of SOC chip, wherein, the device includes the QC mother board, the QC mother board includes PMU power, MCU main control unit, SOCKET seat, QC daughter board, combination switch, TEST button, DEBUG button, functional module, result display module. The PMU power supply is used for supplying power to the QC motherboard; the QC daughter board is connected with the functional module, the MCU main controller and the SOC chip to be tested, which is arranged on the SOCKET seat; the MCU main controller is connected with the SOC chip to be tested through an SWD bus; the TEST key and the DEBUG key are used to initiate different QC modes. The utility model provides an automatic QC device of SOC chip only needs a function test that begins the test button just can accomplish the SOC chip, has portable, efficient characteristics.

Description

Automatic QC device of SOC chip

Technical Field

The utility model relates to a SOC chip test field, concretely relates to automatic QC device of SOC chip.

Background

Before shipment, the SOC chip usually needs to perform a function test according to an application scenario, and can be delivered to a customer after ensuring that there is no function problem. If 100% is to guarantee that there are no quality problems for the customer's chip, it is necessary to cover as much as possible all circuit functions during testing. However, the SOC chip has numerous internal functional modules, and differences in various circuit functions inevitably cause different test methods and test conditions, and if a condition environment test is established one by one according to the characteristics of each functional circuit in a large number of SOCs (quality control), the QC efficiency is low, and manual operation errors are easy to occur.

SUMMERY OF THE UTILITY MODEL

In order to solve the problem, the utility model provides an automatic QC device of SOC chip only needs a function test that begins the test button just can accomplish the SOC chip, has improved the efficiency of software testing of chip greatly. The utility model discloses a concrete technical scheme as follows:

an SOC chip automatic QC device comprises a QC mother board, wherein the QC mother board comprises a PMU power supply, an MCU main controller, a SOCKET seat, a QC daughter board, a combination switch, a TEST key, a DEBUG key, a functional module and a result display module, wherein the PMU power supply is connected with the MCU main controller and a current TEST unit and used for supplying power to the whole QC mother board; the MCU main controller is connected with the PMU power supply, the combination switch, the current testing unit and the QC daughter board and is used for controlling the whole QC process; the SOCKET seat is connected with the QC daughter board and the SOC chip to be tested and used for installing the SOC chip to be tested; the QC daughter board is connected with the MCU main controller, the SOCKET seat and the functional module and used for installing the SOCKET seat; the combination switch is connected with the MCU main controller and is used for manually inputting the type of the SOC chip to be tested; the TEST key is connected with the MCU main controller and used for starting a TEST mode; the DEBUG key is connected with the MCU main controller and used for starting a DEBUG mode; the function module is connected with the QC daughter board and used for testing various functions of the SOC chip to be tested; and the result display module is connected with the MCU main controller and used for displaying the test result. The SOC chip automatic QC device of the utility model relies on the MCU main controller, can automatically test the SOC chip without connecting the PC end and other traditional instruments, and has higher portability; the MCU main controller can randomly call the QC codes stored in advance according to the CHIPID of the SOC chip, and does not need to spend time to compile required codes before testing, thereby effectively shortening the testing time and improving the working efficiency of testers.

Further, the MCU main controller stores QC codes with the format of h, which are compiled and converted by the IDE. The QC codes are converted into h-header files with byte as a unit, so that the h-header files are convenient to call, and can be aligned with byte, half-word or word, and are flexible.

Furthermore, the SOCKET seat is arranged on a QC daughter board, the QC daughter board is arranged on a QC mother board, and both the SOCKET seat and the QC daughter board can be detached. The SOC chips of different types are compatible by replacing different SOCKET seats and the QC daughter boards, so that the QC device is prevented from being independently developed for the chips of different types, and the utilization rate of the QC device is improved.

Furthermore, the combination switch is an 8-bit dial switch, is connected with 8 IO ports of the MCU main controller, sets high and low levels through the dial switch, and encodes to form 8-bit data to represent a predefined SOC chip. The CHIPID of the SOC chip is allowed to be manually set by a user so as to deal with the situation that the MCU main controller cannot read the CHIPID, and the method is flexible.

Further, the functional module includes: the current testing unit is used for testing the power supply open short circuit of the SOC chip to be tested; the USART butt joint self-test module is used for testing a serial communication interface of the SOC chip to be tested; the GPIO docking self-test module is used for testing a general input/output interface of the SOC chip to be tested; the GPTM docking self-testing module is used for testing a universal timer module of the SOC chip to be tested; the MCTM butt joint self-test module is used for testing the PWM wave output function of the control motor of the SOC chip to be tested; the PID butt joint self-testing module is used for testing the PWM wave output function of the PID motion control of the SOC chip to be tested; the DAC testing module is used for testing the ADC analog-to-digital conversion function of the SOC chip to be tested; the ADC test module is used for testing the DAC analog-to-digital conversion function of the SOC chip to be tested; the externally hung NORFLASH device is used for testing an SPI controller module of the SOC chip to be tested; the plug-in EEPROM device is used for testing an I2C communication module of the SOC chip to be tested; the external DDR2/3 memory chip is used for testing the DDR controller circuit function of the SOC chip to be tested; and the plug-in TF card is used for testing the SDIO module circuit function of the SOC chip to be tested. According to the CHIPID of the SOC chip to be tested, whether the functional module is connected or not can be freely selected so as to meet the test requirements of different types of SOC chips.

Furthermore, the MCU main controller is provided with a communication serial port connected with an upper computer, and the upper computer can print a test result of the SOC chip. The host computer can provide detailed test report for the tester, makes things convenient for the tester to know specific test process.

The beneficial effects of the utility model reside in that: the utility model provides an automatic QC device of SOC chip has integrateed a plurality of functional test modules, can realize quick automatic test of SOC chip, shortens test time effectively, improves efficiency of software testing; the device is provided with a DEBUG mode, so that rapid fault positioning can be realized; the device still takes the treater certainly, need not connect the PC end and can test, does not also not rely on traditional instruments such as digital power supply, universal meter, oscilloscope simultaneously, has higher portability, and through the combination of different SOCKET seats and QC daughter board, can compatible SOC chips of different grade type, has higher commonality.

Drawings

Fig. 1 is a schematic view of an embodiment of the automatic QC apparatus for SOC chips of the present invention.

Fig. 2 is a flow chart of the automatic QC method of the SOC chip according to an embodiment of the present invention.

Detailed Description

The technical solution in the embodiments of the present invention will be described in detail below with reference to the accompanying drawings in the embodiments of the present invention. It should be understood that the following description of specific embodiments is illustrative only and is not intended to limit the invention.

In the following description, specific details are given to provide a thorough understanding of the embodiments. However, it will be understood by those of ordinary skill in the art that the embodiments may be practiced without these specific details. For example, circuits may be shown in block diagrams in order not to obscure the embodiments in unnecessary detail. In other instances, well-known circuits, structures and techniques may not be shown in detail in order not to obscure the embodiments.

As shown in fig. 1, an SOC chip automatic QC apparatus includes a QC motherboard, which includes a PMU power supply, an MCU main controller, a SOCKET seat, a QC daughter board, a combination switch, a TEST key, a DEBUG key, a function module, and a result display module, wherein the PMU power supply is connected to the MCU main controller and the current TEST unit, and is used for supplying power to the whole QC motherboard; the MCU main controller is connected with the PMU power supply, the combination switch, the current testing unit and the QC daughter board and is used for controlling the whole QC process; the SOCKET seat is connected with the QC daughter board and the SOC chip to be tested and used for installing the SOC chip to be tested; the QC daughter board is connected with the MCU main controller, the SOCKET seat and the functional module and used for installing the SOCKET seat; the combination switch is connected with the MCU main controller and used for manually inputting the type of the SOC chip to be tested; the TEST key is connected with the MCU main controller and used for starting a TEST mode; the DEBUG key is connected with the MCU main controller and used for starting a DEBUG mode; the function module is connected with the QC daughter board and used for testing various functions of the SOC chip to be tested; and the result display module is connected with the MCU main controller and used for displaying the test result. The SOC chip automatic QC device in the embodiment can be used for automatically testing the SOC chip without connecting a PC end and other traditional instruments by depending on the MCU main controller, and has high portability; the MCU main controller can randomly call the QC codes stored in advance according to the CHIPID of the SOC chip, and does not need to spend time to compile required codes before testing, thereby effectively shortening the testing time and improving the working efficiency of testers.

As one embodiment, the MCU main controller stores QC codes with the format of h after being compiled and converted by the IDE. The method of the embodiment converts the QC code into the h-header file with byte as a unit, is convenient to call, can also achieve byte alignment, half-word alignment or word alignment, and is flexible.

As one embodiment, the SOCKET seat is arranged on a QC daughter board, the QC daughter board is arranged on a QC mother board, and both the SOCKET seat and the QC daughter board can be detached. The method can be compatible with different types of SOC chips by replacing different SOCKET seats and QC daughter boards, avoids developing QC devices for different types of chips independently, and improves the utilization rate of the QC devices.

As one implementation mode, the combination switch is an 8-bit dial switch, is connected with 8 IO ports of the MCU main controller, sets high and low levels through the dial switch, and encodes to form 8-bit data to represent a predefined SOC chip. The method described in this embodiment allows a user to manually set the CHIPID of the SOC chip to cope with the situation that the MCU host controller cannot read the CHIPID, which is relatively flexible.

As one embodiment, the functional module includes: the current testing unit is used for testing the power supply open short circuit of the SOC chip to be tested; the USART butt joint self-test module is used for testing a serial communication interface of the SOC chip to be tested; the GPIO docking self-test module is used for testing a general input/output interface of the SOC chip to be tested; the GPTM docking self-testing module is used for testing a universal timer module of the SOC chip to be tested; the MCTM butt joint self-test module is used for testing the PWM wave output function of the control motor of the SOC chip to be tested; the PID butt joint self-testing module is used for testing the PWM wave output function of the PID motion control of the SOC chip to be tested; the DAC testing module is used for testing the ADC analog-to-digital conversion function of the SOC chip to be tested; the ADC test module is used for testing the DAC analog-to-digital conversion function of the SOC chip to be tested; the externally hung NORFLASH device is used for testing an SPI controller module of the SOC chip to be tested; the plug-in EEPROM device is used for testing an I2C communication module of the SOC chip to be tested; the external DDR2/3 memory chip is used for testing the DDR controller circuit function of the SOC chip to be tested; and the plug-in TF card is used for testing the SDIO module circuit function of the SOC chip to be tested. The functional module described in this embodiment can freely select whether to be connected or not according to the CHIPID of the SOC chip to be tested, so as to meet the test requirements of different types of SOC chips.

As one of the implementation modes, the MCU main controller is provided with a communication serial port connected with an upper computer, and the upper computer can print test information of the SOC chip test result. The method provided by the embodiment can provide a detailed test report for a tester, and the tester can conveniently know a specific test process.

The following describes the testing process of an SOC chip of a certain model in detail, and the testing process is shown in fig. 2, assuming that all functional modules on the QC motherboard are required for testing the chip.

Firstly, the SOC chip of the model is installed in a proper SOCKET seat, the seat is installed in a proper QC daughter board, the QC daughter board is installed on a QC mother board, the power supply is switched on, and preparation before testing is finished.

And when the user presses down the TEST key, the MCU main controller is connected with the SWD bus of the SOC chip to be tested through the GPIO port. If the connection fails, the user can manually set the model (CHIPID) of the SOC chip to be tested through a combination switch connected with the MCU main controller under the condition of ensuring the correct installation of the chip. The combination switch is an 8-bit dial switch, and can be pulled up to VCC when being pulled up, and pulled down to GND when being pulled down. The MCU master controller reads the level of the IO port to acquire the code value of the dial switch so as to know the CHIPID of the SOC chip to be tested, such as 0000_0001 for AM380S, 0000_0002 for AM380E, 0000_00003 for AM330, and the like; if the connection fails all the time without manual setting, the result display module gives an alarm, for example, an LED lamp is arranged to display red and continuously twinkle, and a user can perform power failure retest; and if the connection is successful, directly reading the CHIPID which is burnt to the SOC chip to be tested in advance.

After knowing the CHIPID of the SOC chip to be tested, loading the QC code required by the chip into a flash or sram memory inside the chip according to a preset priority sequence, then modifying the content of a stack pointer, pointing a PC pointer to a program start address, and starting the SOC chip to be tested to execute the code from a flash 0x0 address or an sram 0x20000000 address, wherein the specific steps are as follows:

(1) testing power supply open and short circuit, configuring a gear of a current testing unit by an MCU main controller through an I2C interface, accurately testing the current of a power supply pin of the SOC chip to be tested, obtaining the power consumption current of the SOC chip to be tested by the current testing unit through calculation, transmitting the power consumption current to the MCU main controller in real time for judgment, testing PASS if the measured current value is smaller than the maximum current specified by a specification, and then directly jumping to the next step for execution; otherwise, testing FAIL and waiting for user operation;

(2) firstly, a bootloader serial port sending terminal TX pin of an SOC chip to be tested is connected with a receiving terminal RX pin of a serial port of an MCU main controller, a bootloader program which is stored in a flash in advance is executed after the SOC chip to be tested is electrified, a character string with bootloader version information is sent through the serial port TX, the MCU main controller receives the character string through the serial port RX, if the bootloader version information is consistent with an expected version, PASS is tested, and then the next step is directly skipped to execute; if the received version information is inconsistent or the character string is not received within time, testing the FAIL and waiting for user operation;

(3) firstly, a GPTM module of an MCU main controller serving as a clock measurement unit is configured to capture an input mode and is connected with a CKOUT pin of an SOC chip to be tested, a low-frequency clock LSI, a frequency multiplication clock PLL, a USB clock and a DDRPLL clock in the SOC chip to be tested are sequentially emitted to the CKOUT pin, a GPTM module of the MCU main controller captures a count value and a GPTM working clock to calculate to obtain a specific frequency value of the clock to be tested, the specific frequency value is compared with a test index, if the specific frequency value is within the index range, PASS is tested, and then the next step is directly skipped to be executed; if the test frequency value is out of the index range, testing FAIL and waiting for user operation;

(4) the flash/sram storage test sequentially writes all A, reads out and compares, writes all 5, reads out and compares, writes in all F, reads out and compares, writes in all 0, reads out and compares, the above-mentioned test read data is identical with write data, test PASS, jump to the next step and carry out directly afterwards; if the test read data is inconsistent with the write data, testing FAIL and waiting for user operation;

(5) testing a DDR2/DDR3 control module, connecting an address line, a command line, a clock line and a data line of a to-be-tested SOC DDR2/DDR3 controller with the address line, the command line, the clock line and the data line of DDR2/DDR3 memory particles on a QC motherboard respectively, performing access and read-write operation on the memory particles at a set frequency speed, testing PASS if no error occurs in the access and the read-write operation, and then directly jumping to the next step for execution; if the access to the memory address is unsuccessful or the reading and writing are wrong, testing the FAIL and waiting for the user operation;

(6) firstly, generating a plurality of specific voltage values by utilizing an analog voltage output channel of a high-precision DAC chip on a QC motherboard; then, the SOC chip to be tested collects the voltage values through an ADC channel of the SOC chip, and the voltage value obtained after calculation is compared with the voltage value generated by the high-precision DAC chip; if several voltage values acquired by the ADC channel are within the input voltage index range, testing PASS, and then directly jumping to the next step for execution; if several voltage values acquired by the ADC channel are outside the input voltage index range, testing FAIL and waiting for user operation;

(7) testing by the MCTM control module, and connecting the two groups of MCTM interfaces by a QC code control signal switch IC; MT0_ CH0/0N/1/1N/2/2N/3 of a Motor timer0 is respectively connected with MT1_ CH0/0N/1/1N/2/2N/3 of a Motor timer 1; firstly, MT0_ CH0/0N/1/1N/2/2N/3 outputs PWM wave form, MT1_ CH0/0N/1/1N/2/2N/3 receives and detects the frequency of the PWM wave, then MT1_ CH0/0N/1/1N/2/2N/3 outputs the PWM wave form, MT0_ CH0/0N/1/1N/2/2N/3 receives and detects the frequency of the PWM wave; if the two groups of MCTM interfaces can detect the PWM waveform with the correct frequency, testing PASS, and then directly jumping to the next step for execution; if any group of MCTM interfaces cannot detect the PWM waves with the correct frequency, testing FAIL and waiting for user operation;

(8) testing by a universal timer module, and connecting the two groups of GPTM interfaces by a QC code control signal switch IC; t0_ CH0/1/2/3 of the GPTM timer0 is respectively connected with T1_ CH0/1/2/3 of the GPTM timer 1; firstly, T0_ CH0/1/2/3 outputs PWM wave forms, T1_ CH0/1/2/3 receives and detects the frequency of the PWM wave, then T1_ CH0/1/2/3 outputs the PWM wave forms, and T0_ CH0/1/2/3 receives and detects the frequency of the PWM wave; if the two groups of GPTM interfaces can detect the PWM waveform with the correct frequency, testing PASS, and then directly jumping to the next step for execution; otherwise, if any group of GPTM interfaces cannot detect the PWM wave with the correct frequency, testing FAIL and waiting for user operation;

(9) the PID control module tests, and the QC code control signal switch IC connects the two sets of PID module circuits; PID0_ OUT is connected with PID1_ IN, PID1_ OUT is connected with PID0_ IN; PID0_ OUT and PID1_ OUT output specific groups of frequency PWM waveforms, PID1_ IN and PID0_ IN receive and detect corresponding PWM waveforms respectively, if the frequencies of the groups are detected correctly, PASS is tested, and then the next step is directly skipped to execute; otherwise, if any group of PID input interfaces can not detect the PWM wave with the correct frequency, testing the FAIL and waiting for the user operation;

(10) testing the SPI controller module, wherein a QC code control signal switch IC connects n groups of SPI interfaces with n norflash devices on a QC motherboard, an SOC chip to be tested sends erasing and reading-writing commands (n is n SPI modules owned by the SOC to be tested) to the n norflash devices respectively, if the commands are executed correctly, PASS is tested, and then the next step is directly skipped to for execution; otherwise, if any group of commands are unsuccessfully executed, testing the FAIL and waiting for user operation;

(11) the serial communication interface test, QC code control signal switch IC connects TX interfaces of n groups of USART modules with RX interfaces respectively (n is n USART modules owned by SOC to be tested), if n groups of RX interfaces can correctly receive data sent by the TX interfaces, PASS is tested, and then the next step is directly skipped to execute; otherwise, if any group of commands are unsuccessfully executed, testing the FAIL and waiting for user operation;

(12) the method comprises the steps that an I2C communication module is tested, a QC code control signal switch IC connects n groups of I2C communication interfaces with n EEPROM devices on a QC motherboard, a SOC chip to be tested sends read-write commands (n is n I2C module circuits owned by the SOC to be tested) to the n EEPROM devices respectively, if the read data is equal to the written data, PASS is tested, and then the next step is directly skipped to for execution; if the read data is not equal to the written EEPROM data, testing the FAIL and waiting for user operation;

(13) testing a general input/output interface, wherein a QC code control signal switch IC connects the group A with the group B GPIO interfaces; firstly, taking the group A as output, respectively outputting 1/0 high and low levels, taking the group B as input, reading the level output by the group A, then changing the group B as output, and taking the group A as input to execute the same operation; if the two groups of GPIO interfaces can correctly read the level output by the other party, the test is passed, PASS is tested, and then the next step is directly skipped to be executed; if any group of GPIO interfaces can not read the correct level output by the other party, testing the FAIL and waiting for the operation of a user;

(14) the method comprises the following steps that a circuit function test of the SDIO module is carried out, a tf-sd card is inserted into a QC motherboard, a command line, a data line and a clock line of the SDIO module of an SOC chip to be tested are respectively connected with the tf-sd card, the tf-sd card is mounted, a file system is created and read-write test is carried out, if the test has no error, PASS is tested, and then the next step is directly skipped to be executed; if the file is wrongly read and written or the tf-sd card FAILs to be mounted, testing the FAIL and waiting for the user operation;

(15) firstly, generating a plurality of specific voltage values by using a DAC analog voltage output channel of the SOC chip to be tested; then, an ADC channel on the QC motherboard collects the voltage values and compares the voltage values with the voltage value generated by a DAC analog voltage output channel of the SOC chip to be tested; when the voltage acquired by the ADC channel is within the index range of the DAC analog output voltage, testing PASS, and then directly jumping to the next step for execution; if the voltage acquired by the ADC channel is out of the index range of the DAC analog output voltage, testing FAIL and waiting for user operation;

(16) testing an encryption and decryption module, configuring an encryption mode, carrying out encryption operation on input data, then carrying out decryption reverse operation on the encrypted data, testing PASS if the encrypted output data is equal to the decrypted data, and then directly jumping to the next step for execution; if the encrypted data and the decrypted data are not equal, testing the FAIL and waiting for user operation;

(17) testing a redundancy detection module, performing CRC on input data, comparing a calculated CRC value with an expected value, testing PASS if the CRC value is equal to the expected value, lighting an LED green lamp when all functional modules PASS the test, and then enabling the MCU master controller to enter a standby state; if the calculated CRC value is not equal to the expected value, testing FAIL and waiting for user operation;

in any of the above tests, FIAL, the user may press the DEBUG button to enter the DEBUG mode. And (4) after entering the DEBUG mode, pressing the DEBUG key once again, turning off the LED lamp, and then restarting the test from the step (1). If PASS is tested in the step (1), directly lighting an LED green lamp; and (3) if the FAIL is tested in the step (1), directly lighting the LED red lamp. In both cases, the user is required to wait for the next operation: if the user presses a TEST key, the LED lamp is turned off again, then the QC code of the step (1) is executed again, and a TEST result is displayed; and (3) if the user presses the DEBUG button, the LED lamp is also turned off, and then the QC code of the step (2) is executed, and the test result is displayed. Steps (1) to (16) all follow the same mode of operation. In step (17), since there is no next test module, the DEBUG mode exits after the DEBUG key is pressed, and the MCU main controller enters a standby state. In the DEBUG mode, the DEBUG key is double-clicked within 500ms, and the DEBUG mode can also be quitted.

And the MCU main controller is provided with a serial port for communicating with the PC. If the MCU main controller is connected with the PC through the serial port, after the TEST mode or the DEBUG mode is finished, the MCU main controller can firstly print PASS/FAIL information to the PC end and then enters a standby state.

In the embodiments provided in the present disclosure, it should be understood that the disclosed system, apparatus, and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form. The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present invention.

Claims (6)

1. An SOC chip automatic QC device comprises a QC motherboard, and is characterized in that the QC motherboard comprises a PMU power supply, an MCU main controller, a SOCKET seat, a QC daughter board, a combination switch, a TEST key, a DEBUG key, a functional module and a result display module, wherein,

the PMU power supply is connected with the MCU main controller and the current testing unit and is used for supplying power to the whole QC motherboard;

the MCU main controller is connected with the PMU power supply, the combination switch, the current testing unit and the QC daughter board and is used for controlling the QC process;

the SOCKET seat is connected with the QC daughter board and the SOC chip to be tested and used for installing the SOC chip to be tested;

the QC daughter board is connected with the MCU main controller, the SOCKET seat and the functional module and used for installing the SOCKET seat;

the combination switch is connected with the MCU main controller and is used for manually inputting the type of the SOC chip to be tested;

the TEST key is connected with the MCU main controller and used for starting a TEST mode;

the DEBUG key is connected with the MCU main controller and used for starting a DEBUG mode;

the function module is connected with the QC daughter board and used for testing various functions of the SOC chip to be tested;

and the result display module is connected with the MCU main controller and used for displaying the test result.

2. The automatic QC device of SOC chips according to claim 1, wherein the MCU master controller stores QC codes in the format of.h, compiled and converted by IDE.

3. The automatic QC device of SOC chips according to claim 1, wherein said SOCKET SOCKET is mounted on a QC daughter board, said QC daughter board is mounted on a QC mother board, and both the SOCKET SOCKET and the QC daughter board are detachable.

4. The automatic QC device for SOC chips according to claim 1, wherein the combination switch is an 8-bit dial switch, connected to 8 IO ports of MCU master controller, and set high and low levels by toggle switch to encode 8-bit data representing a predefined SOC chip.

5. The automatic QC device of SOC chips according to claim 1, wherein said functional modules comprise:

the current testing unit is used for testing the power supply open short circuit of the SOC chip to be tested;

the USART butt joint self-test module is used for testing a serial communication interface of the SOC chip to be tested;

the GPIO docking self-test module is used for testing a general input/output interface of the SOC chip to be tested;

the GPTM docking self-testing module is used for testing a universal timer module of the SOC chip to be tested;

the MCTM butt joint self-test module is used for testing the PWM wave output function of the control motor of the SOC chip to be tested;

the PID butt joint self-testing module is used for testing the PWM wave output function of the PID motion control of the SOC chip to be tested;

the DAC testing module is used for testing the ADC analog-to-digital conversion function of the SOC chip to be tested;

the ADC test module is used for testing the DAC analog-to-digital conversion function of the SOC chip to be tested;

the externally hung NORFLASH device is used for testing an SPI controller module of the SOC chip to be tested;

the plug-in EEPROM device is used for testing an I2C communication module of the SOC chip to be tested;

the external DDR2/3 memory chip is used for testing the DDR controller circuit function of the SOC chip to be tested;

and the plug-in TF card is used for testing the SDIO module circuit function of the SOC chip to be tested.

6. The automatic QC device of the SOC chips of claim 1, wherein the MCU master controller is provided with a communication serial port connected to an upper computer, and the upper computer can print test information of the test results of the SOC chips.

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