CN102157205A - Method for testing fault of multiposition memorizer inlaid in FPGA - Google Patents
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Abstract
The invention relates to a method for testing the fault of a multiposition memorizer inlaid in FPGA. The method comprises the following six steps of: firstly, increasing the quantity of test patterns through the formula: two multiplied by (one plus log2n) by the March C-algorithm; secondly, introducing the test patterns, the quantity of which is expressed by the formula: two multiplied by (one plus log2n) into six March units of the March C-algorithm so as to obtain the March C-algorithm for testing the memorizer based on memory cells and has the bit wide of n bit; thirdly, establishing a BIST structure in FPGA by utilizing the Verilog hardware description language; fourthly, using a control unit to control the test patterns of the tested memorizer, the state of a state controller as well as the start and stop of an internal response analyzer which are input under different states at the BIST platform, and generating the sequence of March element test patterns needed for different fault models of the memorizer by a test pattern generator; fifthly, testing the memorizer according to the generated test patterns; and sixthly, observing test wave forms, and determining the fault type of the memorizer. The method achieves simplicity and easiness for implementation, and has considerably broad application prospect in the field of testing the multiposition memorizer inlaid in FPGA.
Description
Technical field
The present invention relates to a kind of method for testing memory, relate in particular to a kind of method of testing to the embedded multi-bit memory fault in FPGA inside, belonging to FPGA is the field programmable gate array test technical field.
Background technology
Field programmable gate array (hereinafter to be referred as FPGA) is the novel programmable logic device (PLD) that occurs in the eighties mid-term, and its principal feature is exactly to be configured by software by the user fully and to programme, thereby finishes certain specific function, and can be erasable repeatedly.When revising and upgrade, do not need to change extraly the PCB circuit board, just revise on computers and refresh routine, make hardware design work become software development work, shortened the cycle of system design, improve the dirigibility that realizes and reduced R﹠D costs, therefore obtained numerous Hardware Engineers' favor.
Along with FPGA application and more and more cheaper price more and more widely, the user has proposed more and more higher requirement to its reliability.Simultaneously, fast development along with China's Aeronautics and Astronautics and weaponry cause, increasing weaponry, airborne electronic equipment system, missile-borne and aerospace electronic system adopt the FPGA device to replace the general-purpose device of traditional ASIC or middle and small scale to realize design, and this just has higher requirement to the q﹠r of FPGA device.So, the various fault detection and diagnosis methods of FPGA device are carried out deep comprehensively research, reduce the failure rate of FPGA device as far as possible, have important practical significance.And in-line memory is as current main-stream FPGA important function piece, and how it being carried out effective evaluation is the necessary link that FPGA is evaluated and tested comprehensively.
When embedded memory module is tested, be logical fault models with the physical fault model conversation usually.Embedded storage system is modeled as the functional module collection of interconnection, its actual physical fault depends on technology and transistor circuit to a great extent, fault model is turned to logic fault, make measuring technology and circuit engineering and manufacturing process irrelevant, therefore it has more versatility, and the embedded memory module functional mode as shown in Figure 1.
For the embedded memory module of FPGA inside, its fault model comprises persistent fault, translation exception, coupling fault and address decoder fault.
1) persistent fault: the in-line memory persistent fault is meant that the storage unit logical value is fixed as 0 or be fixed as 1 fault, and storage unit always is in malfunction, and the fault logic value does not change.
2) translation exception: storer translation exception is a kind of special circumstances of persistent fault.When storage unit was carried out data writing operation, storage-unit-failure made 0 → 1 (rising) change or 1 → 0 (decline) changes the fault generation.Rising translation exception is expressed as＜and ↑/0 〉, and decline translation exception is expressed as＜↓/1.
3) coupling fault: the form of expression of storer coupling fault be the transformation of storage unit a cause storage unit b do not expect change.When memory under test is set up the coupling fault model, adopt the coupling fault model of two unit usually, promptly being used to produce storage unit a takes place ↑ and ↓ write operation that changes can change the content of storage unit b.The storer coupling fault is broadly divided into three kinds according to the difference of coupling scheme, promptly is inverted coupling fault, idempotent coupling fault and Dynamic Coupling fault.
● be inverted coupling fault: the form of expression of being inverted coupling fault for storage unit a take place ↑ or ↓ change can stored inverted unit b storing value.General symbolization when describing the inversion coupling fault＜↑;
, wherein
The content of expression storage unit b is reversed, therefore the form of expression of two kinds of coupling faults can be described as＜↑;
And＜↓;
.
● the idempotent coupling fault: the idempotent coupling fault form of expression for storage unit a take place ↑ and ↓ when changing, the storing value of storage unit b is changed to 0 value or 1 value.When describing the idempotent coupling fault, general symbolization＜↑; 0 〉,＜↑; 1 〉,＜↓; 0〉or＜↓; 1〉expression.
● the Dynamic Coupling fault: the form of expression of storer Dynamic Coupling fault is for when carrying out read or write operation to a storage unit, and can to force the content that is coupled storage unit be 0 value or be 1 value.The Dynamic Coupling fault is a more generally situation of idempotent coupling fault, but because by all sensitization Dynamic Coupling of any read or write operation fault, carries out sensitization and the idempotent coupling fault only can change the coupled storage cell value by write operation.The Dynamic Coupling fault can be expressed as＜r0|w0; 0 〉, wherein | the expression read or write operation, must operate coupling unit.Four kinds of forms of expression of Dynamic Coupling fault can be used symbol:＜r0|w0; 0 〉,＜r0|w0; 1 〉,＜r1|w1; 0〉and＜r1|w1; 1〉expression.
4) address decoder fault: the decoded memory address fault shows as the address decoder mistake, and general hypothesis decoding logic is a non-sequential, and hypothesis is identical with decoding failure in the write operation process at read operation.Generally the address decoder fault is divided into four kinds: the addressable same storage unit of the addressable a plurality of storage unit in storage unit zero-address, special address and a plurality of address that can not visit, visit a certain address.
In the current Test Algorithms for Memory, the March algorithm is one of the most effective testing algorithm, and its testing complex degree is low, and fault coverage height, especially March C-algorithm are more effective to solving the in-line memory failure ratio, and its test flow chart as shown in Figure 2.This algorithm comprises M0, M1, and M2, M3, six March unit of M4 and M5, this algorithm can detect AF, SAF, TF and CF fault, but it can not detect the DRF fault.When utilizing March C-testing algorithm that FPGA inside in-line memory is tested, can whether have persistent fault, translation exception, inversion coupling fault, idempotent coupling fault, Dynamic Coupling fault and address decoder fault by six March element detection of stored devices, each fault model March element combinations corresponding with it cycle tests is described below:
(1) persistent fault: can be by M
0, M
1Element combinations and M
1, M
2Element combinations is measured;
(2) translation exception: 0 to 1 translation exception can be by M
3, M
4Element combinations is measured, and 1 to 0 fault can be by M
2, M
3Element combinations is measured;
(3) be inverted coupling fault: 0 to 1 is inverted coupling fault can be by M
1, M
2Element combinations and M
3, M
4Element combinations is measured, and 1 to 0 fault can be by M
2, M
3Element combinations and M
4, M
5Element combinations is measured;
(4) idempotent coupling fault: putting 0 fault can be by M
1, M
2Element combinations and M
3, M
4Element combinations is measured, and putting 1 fault can be by M
2, M
3Element combinations and M
4, M
5Element combinations is measured;
(5) Dynamic Coupling fault: putting 0 fault can be by M
1, M
2Element combinations and M
3, M
4Element combinations is measured, and putting 1 fault can be by M
2, M
3Element combinations and M
4, M
5Element combinations is measured;
(6) address decoder fault: in March element ascending, descending addressing traversal storage space process, measure.
Above-mentioned March C-algorithm is tested at the storer that with the position is benchmark, but the bit wide of the inner in-line memory data storage cell of typical FPGA is programmable, data bit width can be set to 1bit, 2bit, 4bit, 8bit, 16bit and 32bit, promptly constitutes multi-bit memory.For multi-bit memory, coupling fault may occur between the storage unit that belongs to different addresses, also may occur between the storage unit of same address.The previous case is called coupling fault between storage unit, and latter event is called coupling fault in the storage unit, and these two kinds of faults also can exist simultaneously.
If directly above-mentioned March C-algorithm is extended to the Test Algorithms for Memory of unit orientation, coupling fault can be detected between storage unit, but can not detect coupling fault in the storage unit.
Summary of the invention
1) goal of the invention:
The object of the present invention is to provide a kind of method of testing to the embedded multi-bit memory fault in FPGA inside, it not only can realize the function of current techniques, can also detect the interior coupling fault of storage unit of the inner embedded multi-bit memory of FPGA.
2) technical scheme:
A kind of method of testing to the embedded multi-bit memory fault in FPGA inside of the present invention, it is based on March C-algorithm increases test pattern.For the embedded n bit memory in FPGA inside, its test pattern number should be 2 * (1+log
2N), test pattern as shown in Figure 3.With 2 * (1+log
2N) plant in 6 March elements of test pattern substitution March C-algorithm, just can obtain with storage unit (bit wide is n bit) is the storer March C-testing algorithm of benchmark:
A kind of method of testing of the present invention to the embedded multi-bit memory fault in FPGA inside, these method concrete steps are as follows:
Step 1:, at first increase test pattern based on March C-algorithm.For the embedded n bit memory in FPGA inside, its test pattern number should be 2 * (1+log
2N).This test pattern is as follows:
| Group0 | 00000000…00000000 | Group1 | 11111111…11111111 |
| Group2 | 01010101…01010101 | Group3 | 10101010…10101010 |
| Group4 | 00110011…00110011 | Group5 | 11001100…11001100 |
| Group6 | 00001111…00001111 | Group7 | 11110000…11110000 |
| Group8 | 00000000…11111111 | Group9 | 11111111…00000000 |
| ... | ... | ... | ... |
Step 2: with 2 * (1+log
2N) plant in 6 March elements of test pattern substitution March C-algorithm---be M0, M1, M2, M3, six March unit of M4 and M5, what just can obtain bit wide and be n bit is the storer March C-testing algorithm of benchmark with the storage unit:
Step 3: utilize the Verilog hardware description language in FPGA internal build BIST structure, to realize test to the embedded multi-bit memory fault in its inside.
Step 4: under the BIST platform, by the start and stop of resolution chart, state controller place state and the inner response analysis device of input memory under test down of control module control different conditions.Generate at the required March element test figure sequence of storer different faults model by test graph builder.
Step 5: the resolution chart according to above generation is tested storer.Provide the storer BIST Verilog of system code snippet below, this code snippet can be realized: to whole storage unit of in-line memory, behind the read test pattern m0 of address ascending order elder generation, write test pattern m1:
Step 6: the observation test waveform, determine the storage failure type.
Wherein, utilize the Verilog hardware description language in FPGA internal build BIST structure described in the step 3, comprise six parts altogether: 1 control module; 2 test graph builders; 3 memory clocks; 4 inner response analysis devices; 5 state controllers; 6 memory under test.As shown in Figure 4.
3) advantage and effect:
Patent of the present invention can realize on the common method for testing memory function basis, detects coupling fault in the inner embedded multi-bit memory storage unit of FPGA, has improved the fault coverage of test.This invention realizes easily, can not increase too much consumption to test macro.
Description of drawings
Fig. 1 embedded memory module functional mode synoptic diagram
Fig. 2 March C-test of heuristics process flow diagram
The inner embedded n bit memory test pattern synoptic diagram of Fig. 3 FPGA
Fig. 4 storer BIST structural representation
Fig. 5 block storage test emulation waveform synoptic diagram
The online logic analyser Group0 of Fig. 6 a, Group1 partly observe the waveform synoptic diagram
The online logic analyser Group2 of Fig. 6 b, Group3 partly observe the waveform synoptic diagram
The online logic analyser Group4 of Fig. 6 c, Group5 partly observe the waveform synoptic diagram
The online logic analyser Group6 of Fig. 6 d, Group7 partly observe the waveform synoptic diagram
The online logic analyser Group8 of Fig. 6 e, Group9 partly observe the waveform synoptic diagram
The symbol code name is described as follows among the figure:
1 control module; 2 test graph builders; 3 memory clocks; 4 inner response analysis devices; 5 state controllers; 6 memory under test.
R carries out read operation to the storer corresponding units
W carries out write operation to the storer corresponding units
R0 reads one 0 value from the storer corresponding units
R1 reads one 1 value from the storer corresponding units
W0 writes one 0 value to the storer corresponding units
W1 writes one 1 value to the storer corresponding units
↑ be that the corresponding units of 0 value writes one 1 value or this unit and takes place to rise and change to storer
↓ be that the corresponding units of 1 value writes one 0 value or this unit and takes place to descend and change to storer
Rising storage address order
Embodiment
As tested object, a kind of method of testing to the embedded multi-bit memory fault in FPGA inside of the present invention is described with the Spartan-3 of Xilinx company series of X C3S400 type FPGA embedded memory.The concrete implementation step of this method is as follows:
Step 1:, increase test pattern at first based on March C-algorithm.For the embedded n bit memory in FPGA inside, its test pattern number should be 2 * (1+log
2N).XC3S400 type FPGA embedded memory bit wide is 16, so its test pattern number is 10.This test pattern is as follows:
| Group0 | 0000000000000000 | Group1 | 1111111111111111 |
| Group2 | 0101010101010101 | Group3 | 1010101010101010 |
| Group4 | 0011001100110011 | Group5 | 1100110011001100 |
| Group6 | 0000111100001111 | Group7 | 1111000011110000 |
| Group8 | 0000000011111111 | Group9 | 1111111100000000 |
Step 2: in 6 March elements with 10 kinds of test pattern substitution March C-algorithms---be M0, M1, M2, M3, six March unit of M4 and M5, the March C-testing algorithm that just can obtain XC3S400 type FPGA embedded memory is as follows:
Step 3: the built-in self-test technology is adopted in this test, utilizes the Verilog hardware description language at XC3S400 internal build BIST platform, realizes the test to its inside in-line memory.The BIST structure comprises six parts altogether: control module 1; Test graph builder 2; Memory clock 3; Inner response analysis device 4; State controller 5; Memory under test 6.As shown in Figure 4.
Step 4: under the storer BIST platform that utilizes the Verilog hardware description language to make up, control module 1 is used to control the start and stop of resolution chart, state controller 5 place states and the inner response analysis device 4 of input memory under test 6 under the different conditions.Test graph builder 2 generates at the required March element test figure sequence of storer different faults model according to the present invention.
Step 5: memory under test 6 bit wides are 16, and its test pattern number is 10.Be defined as respectively according to the test pattern variable after the present invention's expansion:
Memory clock 3 is that input signal generates the required clock input signal r_clk of storer with system clock clk.State controller 5 is used for control store present located test mode, state variable march_state comprises the free time (idle), address ascending order write operation (asc_w), the address ascending order reads back write operation (asc_r_w) earlier, the address descending reads back write operation (desc_r_w) earlier, address ascending order read operation (asc_r) and stop (stop) six basic operation states, after March element test pattern after will expanding was brought state variable march_state into, its virtual condition was extended for the free time (idle), the address ascending order writes m0 operation (asc_w0), the address ascending order writes m1 operation (asc_r0_w1) after reading m0 earlier, the address ascending order writes m0 operation (asc_r1_w0) after reading m1 earlier, the address descending writes m1 operation (desc_r0_w1) after reading m0 earlier, the address descending writes m0 operation (desc_r1_w0) after reading m1 earlier, the address ascending order writes m2 operation (asc_r0_w2) after reading m0 earlier, the address ascending order writes m3 operation (asc_r2_w3) after reading m2 earlier, the address ascending order writes m2 operation (asc_r3_w2) after reading m3 earlier, the address descending writes m3 operation (desc_r2_w3) after reading m2 earlier, the address descending writes m2 operation (desc_r3_w2) after reading m3 earlier, the address ascending order writes m4 operation (asc_r2_w4) after reading m2 earlier, the address ascending order writes m5 operation (asc_r4_w5) after reading m4 earlier, the address ascending order writes m4 operation (asc_r5_w4) after reading m5 earlier, the address descending writes m5 operation (desc_r4_w5) after reading m4 earlier, the address descending writes m4 operation (desc_r5_w4) after reading m5 earlier, the address ascending order writes m6 operation (asc_r4_w6) after reading m4 earlier, the address ascending order writes m7 operation (asc_r6_w7) after reading m6 earlier, the address ascending order writes m6 operation (asc_r7_w6) after reading m7 earlier, the address descending writes m7 operation (desc_r6_w7) after reading m6 earlier, the address descending writes m6 operation (desc_r7_w6) after reading m7 earlier, the address ascending order writes m8 operation (asc_r6_w8) after reading m6 earlier, the address ascending order writes m9 operation (asc_r8_w9) after reading m8 earlier, the address ascending order writes m8 operation (asc_r9_w8) after reading m9 earlier, the address descending writes m9 operation (desc_r8_w9) after reading m8 earlier, the address descending writes m8 operation (desc_r9_w8) after reading m9 earlier, the address ascending order reads m8 operation (asc_r8) and stops (stop) 28 states.Fig. 5 is the inner in-line memory of XC3S400 based on the test emulation waveform synoptic diagram under the March C-algorithm BIST test platform.
When the BIST test macro was tested storer, state controller 5 placed initial idle condition (idle) with current system operating state, and under this state, memory under test 6 work enable signal r_en are put height, start it and enter duty.Because test beginning back test macro at first carries out the address ascending order to storer and writes the m0 operation, therefore memory write enable signal r_we is put height under initial idle condition, the state variable register is written into the asc_w0 state, and test address register is written into the minimum memory unit address of storer.Simultaneously provide clock input signal r_clk to memory under test by memory clock module 3, r_clk is in the upset of the negative edge of system clock clk signal, thereby guarantees that control module changes the address input signal r_addr and the data input signal r_di of storer during for low level at the r_clk signal.After test macro leaves initial idle condition and enters test mode, state controller is by state variable march_state control system test mode of living in, control module 1 cooperatively interacts with state controller 5, the realization test macro is changed between 28 test modes, system failure marking signal fault represents that there is fault in storer under the work at present state during for high level, represents storer non-fault under the work at present state during for low level; Represent when writing enable signal r_we that memory operation is writing data mode, represents during for low level that memory operation is in read data status for high level; Address data signal r_addr be under the work at present state storer write or reading of data at memory unit address; When state exchange counter wait_r_clk is used for Adjustment System different operating state exchange, the matching relationship between output response analyzer sampling address location and contrastive test pattern; Data input signal r_di is a memory test graph data input port, and r_do is the memory data output port.
Step 6: will dispose figure and download on the XC3S400 development board, by online logic analyser, internal signal waveforms figure in the real-time monitored XC3S400 actual moving process, shown in Fig. 6 a, Fig. 6 b, Fig. 6 c, Fig. 6 d and Fig. 6 e, the emulation testing result is in full accord with expection..
Claims (2)
1. method of testing to the embedded multi-bit memory fault in FPGA inside, it is characterized in that: these method concrete steps are as follows:
Step 1:, at first increase test pattern based on March C-algorithm; For the embedded n bit memory in FPGA inside, its test pattern number is 2 * (1+log
2N), this test pattern is as follows:
Step 2: with 2 * (1+log
2N) plant in 6 March elements of test pattern substitution March C-algorithm---be M0, M1, M2, M3, six March unit of M4 and M5, what obtain bit wide and be n bit is the storer March C-testing algorithm of benchmark with the storage unit:
Step 3: utilize the Verilog hardware description language in FPGA internal build BIST structure, to realize test to the embedded multi-bit memory fault in its inside;
Step 4: under the BIST platform, by the start and stop of resolution chart, state controller place state and the inner response analysis device of input memory under test down of control module control different conditions, generate at the required March element test figure sequence of storer different faults model by test graph builder;
Step 5: the resolution chart according to above generation is tested storer; Provide the storer BIST Verilog of system code snippet below, this code snippet is realized: to whole storage unit of in-line memory, behind the read test pattern m0 of address ascending order elder generation, write test pattern m1:
Step 6: the observation test waveform, determine the storage failure type.
2. a kind of method of testing according to claim 1 to the embedded multi-bit memory fault in FPGA inside, it is characterized in that: utilize the Verilog hardware description language in FPGA internal build BIST structure described in the step 3, comprise six parts altogether: 1 control module; 2 test graph builders; 3 memory clocks; 4 inner response analysis devices; 5 state controllers; 6 memory under test.
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| CN105468485A (en) * | 2015-11-19 | 2016-04-06 | 英业达科技有限公司 | Character-oriented memory test method |
| CN107978337A (en) * | 2017-12-21 | 2018-05-01 | 上海华力微电子有限公司 | The high speed circuit structure and its test method tested automatically suitable for random access memory |
| CN108039190A (en) * | 2017-12-15 | 2018-05-15 | 北京京存技术有限公司 | A kind of test method and device |
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| CN103065687A (en) * | 2012-12-28 | 2013-04-24 | 山东华芯半导体有限公司 | A method of parallel detection for RAM production defects in an integrated circuit |
| CN105468485A (en) * | 2015-11-19 | 2016-04-06 | 英业达科技有限公司 | Character-oriented memory test method |
| CN108172259A (en) * | 2017-12-13 | 2018-06-15 | 天津津航计算技术研究所 | RAM resources traverse test position fix method in onboard FPGA based on BIST |
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