CN103065687A - A method of parallel detection for RAM production defects in an integrated circuit - Google Patents
A method of parallel detection for RAM production defects in an integrated circuit Download PDFInfo
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Abstract
The invention discloses a method of parallel detection for RAM production defects in an integrated circuit. According to the present invention, the use of the RAM current address status based on a previous test step for the test of the next step is achieved, without the necessary of testing one test point in each test, so the efficiency is greatly improved. The test method for similar RAMs in parallel test chips can effectively reduce the area of the tested chip, reduce production costs, and reduce the complexity of the test and the test time, thereby reducing the cost of the test.
Description
Technical field
The present invention relates to the method for testing of RAM production defective in a kind of integrated circuit.
Background technology
The RAM(Random Access Memory of macroscopic view, random access memory) test comprises the test of test, data line and the address wire test of storage unit.For control line, owing to finishing having attached in the above two the test, therefore do not do special test.And the test of address wire is always carried out in the normal situation of tentation data line, obviously need the test of advanced row data line, then just can carry out the test of address wire.
Along with the increase of integrated circuit scale and the raising of integrated level, the quantity of RAM is more and more in the system, and width and the degree of depth are also different, and its test is also needed to carry out refinement.To finish the test to RAM in the system in the past, usually the method that adopts is the corresponding test module of each RAM, must increase the area of whole chip, high expensive, and the method for testing that adopts all can not once be surveyed complete all defectives, therefore not only increase chip area, and increased time, testing complex degree and the testing cost of test.
In the production run of integrated circuit, owing to technology or other reasons, easily cause the defective of RAM in the circuit.
The basic generation defective of RAM is as follows at present:
◆ Stuck-At Fault (SAF, stuck-at fault): a certain position among the RAM is fixed as 1 or 0, can't write opposite value; Certain bar line in the RAM circuit should be according to the value of its source node and value in other words, but owing to there being certain fault, its logical value is fixed as 0 or 1; Be fixed as 0 fault if having on the line wr, then be designated as wr (s-a-0), be fixed as 1 fault if having, then be designated as wr (s-a-1).
◆ Stuck-Open Fault (SOpF, stuck-open fault): a certain unit among the RAM, because the fracture of line can't operate on it
◆ Transition Fault (TF, error of transmission): namely a certain position among the RAM is write at 0 o'clock, it is actual, and what write is 1, perhaps writes at 1 o'clock, and it is actual, and what write is 0.
◆ Idempotent Coupling Fault(CFid, the idempotent coupling fault): when a certain position among the RAM to be measured is operated, if this numerical value that writes is different from the numerical value of original this position, saltus step will occur, and this saltus step process may exert an influence to its adjacent position, may cause the phase ortho position to become 1 or 0 state.Therefore, CFid is divided into and is Four types:＜↑ | 0 〉,＜↑ | 1 〉,＜↓ | 0 〉,＜↓ | 1 〉.
Representing by 0 saltus step to upward arrow is 1, and arrow representative downwards is 0 by 1 saltus step.
◆ State Coupling Fault(CFst, the state coupling fault): when a certain position among the RAM to be measured was operated, this position was in certain state, for example was in 1 or during 0 state, may cause the phase ortho position that corresponding the variation occurs, namely may become 1 or 0 state.Therefore, CFst also is divided into Four types:＜1; 1 〉,＜1; 0 〉,＜0; 1 〉,＜0; 0 〉.
◆ Inversion Coupling Fault(CFin, contrary coupling fault): when a certain position among the RAM to be measured is operated, in any case its saltus step is 0 or 0 saltus step is arranged is 1 by 1 saltus step namely, all can cause the change of adjacent certain value.For example a certain position initial value among the RAM to be measured is 0, then it is write 1, and this time, its adjacent certain may just become 1 by 0, and when this position was write 0 again, certain adjacent position had just become 0 again by 1 again.Therefore, CFin is divided into two types:＜↑ | x 〉,＜↓ | x 〉.Become 1 to the upward arrow representative by 0, arrow representative downwards becomes 0 by 1.
◆ Address Fault (AF, address fault): when a certain address among the RAM to be measured is operated, possible operation be not the address of wishing, and become other address.
◆ Byte_Enable Fault(BEF, byte enable mistake): the byte_enable control bit among the RAM may link to each other, and perhaps is fixed as some numerical value 1 or 0.
Summary of the invention
Therefore, the object of the present invention is to provide the method for RAM production defective in a kind of parallel detection integrated circuit, produce the efficient of defect test to improve RAM.
The present invention is by the following technical solutions:
The method of RAM production defective in a kind of parallel detection integrated circuit, similar a plurality of RAM on chip of concurrent testing, the method may further comprise the steps:
1) everybody writes 0 to all addresses of RAM;
In following step, be operand take the address, and after this each step enters the test of next address finish the test of current step in the current address after, until travel through the test that enters next step behind the whole RAM:
2) read the value that deposit the RAM current address, if contain 1 position, then stop detecting, report an error; If entirely be 0, then everybody writes 1 to this address, then reads the value that deposit this address, if contain 0 position, then stops detecting, and reports an error; If entirely be 1, then everybody writes 0 to this address, then reads the value that deposit this address, if contain 1 position, then stops detecting, and reports an error; If entirely be 0, then everybody writes 1 to this address;
3) read the value that deposit the RAM current address, if contain 0 position, then stop detecting, report an error; If entirely be 1, then everybody writes 0 to this address, reads the value that deposit this address, if contain 1 position, then stops detecting, and reports an error; If entirely be 0, then everybody writes 1 to this address.
Can find out from technique scheme, according to the present invention, realize the test that is used for a rear step based on last testing procedure RAM current address state, needn't test at every turn and only test a test point, efficient improves greatly.The method of testing of similar RAM in the concurrent testing chip can effectively reduce the area of test chip, reduces production costs, and has reduced the complexity of test and the time of test, thereby reduced the cost of test.
The method of RAM production defective in the above-mentioned parallel detection integrated circuit, step 1) to step 3) to the sequence of operation of RAM all is from the low address to the high address.
The method of RAM production defective in the above-mentioned parallel detection integrated circuit also comprises the following steps that operate from the RAM high address to low address after step 3):
4) read the value that deposit the RAM current address, if contain 0 position, then stop detecting, report an error; If entirely be 1, then everybody writes 0 to this address;
5) read the value that deposit the RAM current address, if contain 1 position, then stop detecting, report an error; If entirely be 0, then everybody writes 1 to this address; Then read the value that deposit this address, if contain 0 position, then stop detecting, report an error; If entirely be 1, then everybody writes 0 to this address, and the data that will form according to 1,0 sequence again write this address, read this address, judgement CFst＜1 | 1〉defective, if there is this defective, report an error, otherwise the data that will form according to 0,1 sequence write this address, then order is read this address, judgement CFst＜0 | 0〉defective, if there is this defective, report an error, otherwise, finish this address test.
The method of RAM production defective in the above-mentioned parallel detection integrated circuit, when writing with reading out data, the width and the degree of depth that are set as test according to similar RAM is different on the same chip breadth extreme and depth capacity.
The method of RAM production defective in the above-mentioned parallel detection integrated circuit, in test process, the test that enters again next step after the test of the current step of all RAM is all finished.
Description of drawings
Fig. 1 is nine grids test schematic diagram.
Fig. 2 is the structure principle chart of ram test device.
Embodiment
Based in the background technology to the analysis of various defectives, the generation of the test vector by as shown in Figure 2, the wherein as a comparison input of device of former number that writes to the RAM current address of test vector is used for relatively reading number and former number, and corresponding RAM is tested.
According to the present invention, a complete method of testing can simply use statement to be expressed as follows:
↑write 0
↑read 0，write 1，read 1，write 0，read 0，write 1
↑read 1，write 0，read 0 , write 1
↓read 1, write 0
↓read 0，write 1, read 1 , write 0 , write data1 , read data1, write data2 , read data 2
Be operation from the low address to the high address to upward arrow, arrow be the operation from the high address to the low address downwards, and 0 represents full 0, and 1 represents entirely 1, and data1 is 101010 ..., data2 is 010101 ...Method of testing is divided into quinquepartite, and therefore every part representative operates whole address ram operation one time five times whole address ram altogether, namely finishes the said test of this paper and contains five steps.Nature can select the part defective to test.
Further, the method of RAM production defective in a kind of parallel detection integrated circuit, similar a plurality of RAM on chip of concurrent testing, as described in the background section, the integrated level of current chip is more and more higher, and RAM integrated on the chip is more and more, and type is also many, such as large classification SRAM, DRAM, there is certain difference in dissimilar RAM, is to the test with kind RAM when this paper lays particular emphasis on concurrent testing.
The method may further comprise the steps:
1) everybody writes 0 to all addresses of RAM, if such as 16 bit address, then is 16 0;
In following step, be operand take the address, and after this each step enters the test of next address finish the test of current step in the current address after, until travel through the test that enters next step behind the whole RAM:
2) read the value that deposit the RAM current address according to predefined procedure, if contain 1 position, then stop detecting, report an error; If entirely be 0, then everybody writes 1 to this address, then reads the value that deposit this address, if contain 0 position, then stops detecting, and reports an error; If entirely be 1, then everybody writes 0 to this address, then reads the value that deposit this address, if contain 1 position, then stops detecting, and reports an error; If entirely be 0, then everybody writes 1 to this address;
Reading here should be to read appropriate address is disposable, is not that step-by-step is read, then with test vector in corresponding depositing such as the number in this address compare, judge whether correct.Here also can be understood as and judge whether consistent problem of two numbers, much higher than the step-by-step reading efficiency.
Thereby above-mentioned steps also can be understood like this, test vector coupling is by by 0 and/or 1 sequence that forms, the sequence corresponding current step writes such as full 0 to the current address, read in other words sequence of the numerical value deposited this address, compare with the corresponding numerical value that writes or sequence in the test vector of being scheduled to, if there is defective in not identical then showing, report an error, if unanimously, then carry out the same class testing of next address.
3) read the value that deposit the RAM current address according to predetermined order, if contain 0 position, then stop detecting, report an error; If entirely be 1, then everybody writes 0 to this address, reads the value that deposit this address, if contain 1 position, then stops detecting, and reports an error; If entirely be 0, then everybody writes 1 to this address.
Based on above description, and in conjunction with the analysis of background technology part about defective, front several steps are analyzed as follows:
◆ whole RAM is write full 0.
◆ at first read in other words by the 2nd step for second portion, the order of reading can be mated the order of writing, be consistent, as being begun by low address, read at first that the first step writes 0, if promising 1 position in the data of reading just illustrates that this position may be fixed as 1, namely there is the SAF defective, perhaps because line has disconnected and can't write it, namely there is the SOpF defective, perhaps error of transmission, namely write at 0 o'clock, actual what write is 1, namely has the TF defective, perhaps because about, above, the a certain point that affects of top diagonally opposing corner is in 0 state, tested point is changed, namely exist in the CFst defective＜0; 1 〉.
Accept epimere, if what read is 0 entirely, again the current address is write 1 and then read 1, if 0 position is arranged in the sense data, according to top analysis, may have 0 the defective of being fixed as among the SAF, perhaps SOpF defective, perhaps TF defective, perhaps among the CFst＜0; 0 〉, perhaps since laterally the impact point occur to cause the variation of tested point numerical value by 0 to 1 saltus step, namely exist in the CFid defective＜↑ | 0 〉, same or since laterally the impact point exist in the CFin defective＜↑ | x 〉.
Accept epimere, if what read is 1 entirely, and then the current address is write 0 then read 0, if there is 1 position in the data of reading this time, may measure in the new defective CFid defective＜↓ | 1 〉, certainly this is caused by the horizontal point that affects, perhaps exist in the CFin defective＜↓ | x 〉.Again this address is write 1 entirely at last.Then next address is repeated the operation of second portion, analyzing influence point is on the impact of tested point in turn.
Nine grids as shown in Figure 1 are to face note on China's calligraphy history to write imitative a kind of boundary lattice originally, are again " nine grids "; Also have similar structure for memory cell matrix, and the logical circuit of consecutive storage unit may exist certain the impact, will produce structure as shown in Figure 1.
By that analogy, the operation part of back is the same with the front, and can analyze the method for testing that provides according to the analytical approach of top simple introduction is what how to realize the covering of RAM basic test point.
What use the statement performance is the method for testing of complete all test points of covering, but a method of testing can test the part defective, but not to all.
As shown in Figure 2, be the one-piece construction block diagram of whole ram test, it is three parts that the total block diagram is divided into: controller, test vector generator and comparer.The effect of controller is the read-write operation of control RAM, and in RAM read-write process, the variation of control address realizes the Test coverage to whole RAM.Write operation is that the test vector that test vector generator generates is write among the RAM to be measured, guarantees correctness and accuracy that data write.Read operation is that the data reading that will write among the RAM to be measured comes, and gives the comparatively validate that comparator module is carried out data, and whole read procedure will guarantee the correctness of address and the accuracy of reading out data, thereby realizes the test job to RAM to be measured.
Because walk abreast RAM is tested, and the degree of depth of RAM, be that the address number can not be identical, therefore in the process of test, some RAM have shifted to an earlier date certain a part of test job of mentioning in the method for testing, need to control the test job that suspends the RAM that finishes test this time, and the uncompleted RAM of continuation test, until all RAM to be measured have finished in the method for testing after certain a part of test job, carry out together again the test job of back Test Methods section, by that analogy, until finish test jobs whole in the method for testing.
The test vector generator functions of modules is to produce the test vector that is used for testing ram, and its function is that the test vector that produces will guarantee the demand of method of testing, and guarantees test to desired defect point.
Comparer is that the data that will read out among the RAM to be measured compared with the data that originally write, to determine whether the RAM in to be measured exists flaw, because the RAM of concurrent testing can not be identical, when the data that therefore write and read compare, and to make corresponding adjustment according to the difference of the hierarchy structure of RAM to be measured.When there is flaw in some among the RAM to be measured, stop immediately the test job to RAM, and draw high bist_fail signal reporting errors, if the current data of reading is during with the data consistent that writes, continue to carry out the test job of back, until finish all tests, draw high the bist_done signal and report that whole test job finishes.
This paper lays particular emphasis on the mode of whole defective all standings is tested, and accepts the data that RAM writes in the step before the current step, improves the efficient of test.
In above-mentioned method, adopting step 1) all is methods of operating from the low address to the high address to step 3) to the order of the write operation of RAM and read operation, travels through all addresses of RAM, operates relatively simply, also makes things convenient for the expansion of concurrent testing.On the other hand, as shown in Figure 1, from the low address to the high address, high address is current like this is constant, low address takes the lead in changing, can measure like this than the impact on high address of the address change of current address, relate in following content from high toward low, be the impact of seeing that the variation of high address changes low address.
Therefore, the following steps that after step 3), also comprise the operation from the RAM high address to low address:
The following steps that after step 3), also comprise the operation from the RAM high address to low address:
4) order is read the value of RAM current address, if contain 0 position, then stops detecting, and reports an error; If entirely be 1, then everybody writes 0 to this address;
The order here refers to be exactly the preamble constraint from the RAM high address to low address.
5) order is read the value that deposit the RAM current address, if contain 1 position, then stops detecting, and reports an error; If entirely be 0, then everybody writes 1 to this address; Then read the value that deposit this address, if contain 0 position, then stop detecting, report an error; If entirely be 1, then everybody writes 0 to this address, and the data that will form according to 1,0 sequence again write this address, read this address, judgement CFst＜1 | 1〉defective, if there is this defective, report an error, otherwise the data that will form according to 0,1 sequence write this address, then order is read this address, judgement CFst＜0 | 0〉defective, if there is this defective, report an error, otherwise, finish this address test.
When writing with reading out data, set width and the degree of depth of testing according to similar RAM is different on the same chip breadth extreme and depth capacity, the width here refers to bit wide, such as 16,32 or 64 again.Thereby, when test, similar RAM being set identical test parameter, can simplify the operation.
Obviously, before the test, the degree of depth of RAM and width are known.
Further, in test process, the test that enters again next step after the test of the current step of all RAM is all finished.We understand, as long as all RAM in a chip have one product defects is arranged, just should scrap this chip, from test angle, if there is defective in a RAM in some tests, ought to just scrap whole chip.Use said method can effectively improve testing efficiency, be convenient to the generation of test vector based on the concurrent testing of said method.
Classic method: the method for testing of employing can not once be surveyed whole test points of full RAM, often need to change test vector, the repetition measurement method for testing of laying equal stress on, will survey so complete basic test point, the total cycle that needs will be relatively long, and the time of test also prolongs relatively, moreover, the method of testing that tradition adopts is for each RAM an independent test module to be arranged, and has so just increased the area of whole chip, and cost is also just relatively high.
Can find out according to said method: the method for testing of employing can once be surveyed whole test points of full RAM, do not need to reuse method of testing, relative classic method, finish the test of the whole test points of whole RAM, whole test period and test duration have been shortened, moreover, said method has also increased Byte_Enable Fault(BEF) test, so relative classic method, increased test point, make test more comprehensive, and this method adopts is the method for testing of similar RAM in the parallel test system, can reduce like this area of whole chip, reduces production costs, and reduced the complexity of test and the time of test, thereby also reduce the cost of test.
DC synthesis tool by use Synopsys is 32 to being used for 4 width, the byte_enable width is 8, the degree of depth is that the module of 32768 single port ram test is carried out comprehensively, by the result after comprehensive is calculated, obtaining the needed NADN2 GATE(of each RAM Sheffer stroke gate) number is 270.2, well below 500 standard.
Therefore it should be noted that because in test, because simultaneously a plurality of RAM are tested, to the having relatively high expectations of voltage, need voltage to keep stable in the process of whole test, mains ripple can not be above 5%.
Should know, along with the development of packaging technology, the production defective of current RAM compares less, and most tests can both be finished smoothly.Obviously, the mode of once having surveyed all production defectives can more effectively improve testing efficiency.
Claims (5)
1. the method for RAM production defective in the parallel detection integrated circuit is characterized in that, similar a plurality of RAM on chip of concurrent testing, and the method may further comprise the steps:
1) everybody writes 0 to all addresses of RAM;
In following step, be operand take the address, and after this each step enters the test of next address finish the test of current step in the current address after, until travel through the test that enters next step behind the whole RAM:
2) read the value that deposit the RAM current address, if contain 1 position, then stop detecting, report an error; If entirely be 0, then everybody writes 1 to this address, then reads the value that deposit this address, if contain 0 position, then stops detecting, and reports an error; If entirely be 1, then everybody writes 0 to this address, then reads the value that deposit this address, if contain 1 position, then stops detecting, and reports an error; If entirely be 0, then everybody writes 1 to this address;
3) read the value that deposit the RAM current address, if contain 0 position, then stop detecting, report an error; If entirely be 1, then everybody writes 0 to this address, reads the value that deposit this address, if contain 1 position, then stops detecting, and reports an error; If entirely be 0, then everybody writes 1 to this address.
2. the method for RAM production defective in the parallel detection integrated circuit according to claim 1 is characterized in that, step 1) to step 3) to the sequence of operation of RAM all is from the low address to the high address.
3. the method for RAM production defective in the parallel detection integrated circuit according to claim 2 is characterized in that, also comprises the following steps of the operation from the RAM high address to low address after step 3):
4) read the value that deposit the RAM current address, if contain 0 position, then stop detecting, report an error; If entirely be 1, then everybody writes 0 to this address;
5) read the value that deposit the RAM current address, if contain 1 position, then stop detecting, report an error; If entirely be 0, then everybody writes 1 to this address; Then read the value that deposit this address, if contain 0 position, then stop detecting, report an error; If entirely be 1, then everybody writes 0 to this address, and the data that will form according to 1,0 sequence again write this address, read this address, judgement CFst＜1 | 1〉defective, if there is this defective, report an error, otherwise the data that will form according to 0,1 sequence write this address, then order is read this address, judgement CFst＜0 | 0〉defective, if there is this defective, report an error, otherwise, finish this address test.
4. the method for RAM production defective in the parallel detection integrated circuit according to claim 1 is characterized in that, when writing with reading out data, and the width and the degree of depth that are set as test according to similar RAM is different on the same chip breadth extreme and depth capacity.
5. the method for RAM production defective to 4 arbitrary described parallel detection integrated circuit according to claim 1 is characterized in that, in test process, and the test that enters again next step after the test of the current step of all RAM is all finished.
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| CN108615543A (en) * | 2016-12-12 | 2018-10-02 | 中国航空工业集团公司西安航空计算技术研究所 | Self checking method for discrete magnitude signal processing chip |
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