CN100487668C - Regulating technology of built-in processor - Google Patents
Regulating technology of built-in processor Download PDFInfo
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- CN100487668C CN100487668C CNB2006101136292A CN200610113629A CN100487668C CN 100487668 C CN100487668 C CN 100487668C CN B2006101136292 A CNB2006101136292 A CN B2006101136292A CN 200610113629 A CN200610113629 A CN 200610113629A CN 100487668 C CN100487668 C CN 100487668C
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Abstract
The present invention provides a debugging technique based on high-speed JTAG embedded processor. The debugging technique supports the debugging means of resetting and examining and modifying a memory or an internal SFR register in single-step or breakpoint mode, examining program variable, etc. A whole debugging system comprises an environment for development and debugging on a computer, an on-chip simulation module, an embedded processor, a memory/peripheral of the embedded processor and so on, wherein, the environment for development and debugging comprises a compiler, an assembler, a connector, a debugger and so on; the environment for development and debugging sends out commands and data through a parallel port of the computer; the on-chip simulation module decodes received commands and transmits data to the processor in a correct format according to the corresponding commands; the single-step and breakpoint control to a program is realized by triggering the processor to enter interrupt; the SFR register is modified through the combining read of the processor and an interrupt service routine. The present invention adopts high-speed JTAG technique to improve transmission speed and uses a concise and precise debugging flow, which is suitable for the debugging field of embedded processors. Compared with the prior debugging technique, the present invention is simpler and easier to be implemented, fast in transmission speed and convenient for IP sharing.
Description
Technical field
The present invention relates to the debugging field of flush bonding processor, particularly debug the field based on the flush bonding processor of JTAG agreement.
Background technology
Traditional debugging technique is that debug host produces the debugging request by a certain position that register is set, and processor is accepted the debugging request and entered debugging mode, and it is effective to put the debugging answer signal.After entering debugging mode, processor quits work and isolates with the other parts of system.This moment, kernel was no longer got finger from ROM, but was inserted into the order register of processor by jtag interface by the instruction (for realizing the instruction of debug function) that debug host will need processor to carry out.By selecting suitable instruction and control the execution of these instructions, the result of execution can be used to detect or revise memory content and processor register.Owing to used the order register of processor in the debug process, after entering debugging mode, need protection and withdraw from the register information that needs the normal operation of recovery routine before the debugging mode.And the contact of this debugging technique debugging module and processor internal logic closely, and the IP that is unsuitable for debugging module shares; Simultaneously once the non-productive operation of control is many, causes the time long and efficient is low.
In addition, JTAG (Joint Test Action Group, combined testing action group) is a kind of international standard test protocol (an IEEE1149.1 compatibility), is mainly used in chip internal test (Boundary Scan﹠amp; , boundary scan) and the emulator of embedded system.The jtag interface of standard is 5 lines: TMS, TCK, TDI, TDO, and TRST is respectively model selection, clock, data input, DOL Data Output Line and resets.Because standard JTAG agreement is that serially-transmitted data causes transmission speed slow.Yet the memory span of embedded system is increasing now, needs the volume of transmitted data of transmission more and more, and serial transmission has a strong impact on debug performance.
Summary of the invention
Fundamental purpose of the present invention provides a kind of simple, the fast and adjustment method that is easy to share of transmission speed, and slow with the transmission speed that solves prior art, communication efficiency is low, the drawback that the degree of coupling of debugging module and processor is high.Commonly used single step, the breakpoint of this debugging technique support, reset, check and revise storer or inner SFR (Special Function Registers) register, check debugging method such as program variable.Solution of the present invention is:
Emulation module enters debugging mode by hardware logic output look-at-me processor controls on the sheet, and realizes the function of single step and breakpoint by the generation position of control look-at-me.The processor response is interrupted, and enters interrupt service routine.Interrupt service routine is put into the finish command that the inner one section RAM that wards off in addition waits for afterwards debug host temporarily to the value of the SFR register of processor.At this moment debug host is passed to emulation module on the sheet to order and data by the high-speed JTAG interface, and emulation module is write a certain position of register to command decoder on the sheet behind the read-write memory, withdraws from interrupt service routine.Also support read-write operation in the interrupt service routine to the SFR register of processor.Emulation module directly links to each other with all storeies on the sheet, supports the direct high speed read-write to external memory storage.
The present invention makes full use of the pin resource of parallel port, releases 11 unique line jtag interfaces, and TDI and TDO are increased to four by one, has accelerated communication speed.Revise the communication protocol between the emulation module on debug host and the sheet simultaneously, realized once transmitting a plurality of data, improved transfer efficiency, saved the transmission time.
Debugging technique of the present invention need not to use the order register of processor, need not to preserve in advance and the relevant register of write-back again, realizes simplely by the mode of interrupting, and module more independently is easy to transplant and share; And docking port and host-host protocol revise, and significantly improves transfer efficiency.
Description of drawings
Fig. 1 system architecture diagram
The logic diagram of emulation module on Fig. 2 sheet
The connection layout of Fig. 3 high-speed JTAG and computer parallel port
Fig. 4 breakpoint produces principle
The waveform of Fig. 5 memory write
The waveform of Fig. 6 memory read
Fig. 7 interrupt service routine flow process
Embodiment:
Further specify the debugging of using adjustment method of the present invention to support one 16 bit CPU below in conjunction with accompanying drawing and example.This 16 bit CPU is the ASIC design, need increase the function of support hardware emulation when carrying out the FPGA checking.Use adjustment method of the present invention realized to CPU single step, breakpoint, reset, suspend, check the control of revising internal memory or internal register, checking program variable.
Fig. 1 is a system architecture diagram, TCK wherein, TDI[3:0], TDO[3:0], TMS, TRST are the signals of the high-speed JTAG interface between the emulation module on simulated environment on the computing machine and the sheet.Ack is passed through in the operation of interruption and reset signal control CPU between the emulation module on interrupt service routine and the sheet, End, and the Sfr_change signal cooperates cooperation.Simulation software reads the position of the PC pointer indication present procedure operation of CPU.The emulation module support is to the direct read operation of all storeies on the sheet.
Fig. 2 is the logic diagram of emulation module on the sheet.The data of jtag interface are resolved through the TAP controller and are stored in the command register.Command register to command decoder after, according to corresponding order the data of subsequently jtag interface are put into respectively in data length address register, data register, break value register, the control register.If to the read write command of storer, according to the storer output control signal of command type to correspondence, address and data realize the read-write to storer; If the order of breakpoint is set, break value is put in the breakpoint register; If read and write the order of control register, then read or revise the value of control register.Output is interrupted and reset signal realizes control to the CPU operation according to the content of control register.When the value of break value register equates with the PC value, will export look-at-me.According to the Ack signal of CPU output, and the End of control register, Sfr_change controls the position operation of interrupt service routine, finishes the communication between debug host and debugging module and the CPU.
Fig. 3 is a high speed jtag interface and being connected of parallel port.High-speed JTAG is very similar to common jtag interface, and difference is the tdi and the tdo of common jtag interface, all be 1bit bit serial transmission data, and high-speed JTAG is 4bit position transmission data.Transfer rate has improved four times like this.The 3rd pin of the parallel port of computing machine is through overdriving as TCK, the 4th pin is through overdriving as TMS, 9th, 8,7,6 pin are through overdriving as TDI[3:0], TDO[3:0] be input to the 11st, 10,12,13 pin through overdriving, owing to adopt 4 TDI and TDO, receive or send the data of a byte, as long as two tck clocks have been saved the time greatly.
As shown in Figure 2, internal register has command register, control register, break value register, address register.Main frame sends debug command and data by the parallel port, emulation module is saved in the tdi bus eight bit data of going forward in the command register by the tap controller on the sheet, then order is deciphered, according to different orders data are stored in address register respectively again, in break value register and the control register.Table 1 is the command type of command register.Comprise go, read-write memory, the read-write breakpoint, the read-write control register is read pc.Address register has comprised the start address and the data length of the data that promptly will transmit, and form is as shown in table 2.The break value register is 23 a register, deposits the position of program halt.Comprised the control and the status information of total system in the control register, form is as shown in table 3.
Table 1 command type and coding
| Command type | Coding |
| GO_COMMAND | 0xD |
| WRITE_ROM | 0x1 |
| READ_ROM | 0x2 |
| WRITE_RAM | 0x3 |
| READ_RAM | 0x4 |
| WRITE_EEPROM | 0x5 |
| READ_EEPROM | 0x6 |
| WRITE_JRAM (sfr register) | 0x7 |
| READ_JRAM (sfr register) | 0x8 |
| WRITE_CTRL (control register) | 0x9 |
| READ_CTRL (control register) | 0xA |
| WRITE_BKP1 (breakpoint 1) | 0xB |
| READ_BKP1 (breakpoint 1) | 0xC |
| WRITE_BKP2 (breakpoint 2) | 0xE |
| READ_BKP2 (breakpoint 2) | 0xF |
| WRITE_BKP3 (breakpoint 3) | 0x10 |
| READ_BKP3 (breakpoint 3) | 0x11 |
| READ_PC | 0x12 |
Table 2 address register
| The position | Access attribute | Describe |
| 32:23 | R/W | Data length |
| 22:0 | R/W | The address |
Table 3 control register
| The position | Access attribute | Describe |
| 7:3 | Keep | |
| 2 | R/W | CPU_end end mark position |
| 1 | R/W | The single step enable bit |
| 0 | R/W | Cpu reset |
As shown in Figure 2, output is interrupted and reset signal realizes control to CPU according to the content of control register, and this CPU can judge whether look-at-me is arranged when second clock period that every instruction is carried out, just do not carry out this instruction if having, and response is interrupted; If no, just continue to carry out this instruction.Around this principle, we are high by the single step enable bit of write control register command configuration control register, and first clock period of the second instruction of hardware logic after withdrawing from interrupt service routine begins to export the look-at-me of a clock period length.Guarantee like this after executing an instruction, to enter interruption, realize the single step function.As shown in table 3, the position 2 of write control register is high, and hardware logic produces look-at-me realization single-step operation carry out an instruction after withdrawing from interrupt service routine after.
Fig. 4 is the principle that breakpoint is realized, by writing the breakpoint address of breakpoint command configure breakpoint value register for expection; The PC value that each clock period all samples current in the program operation process compares with value in the breakpoint register, equates just to produce look-at-me.
Reset operation produces a reset signal and gives processor by the Reset position height of control register after withdrawing from interrupt service routine.
As shown in Figure 2, emulation module interface direct and storer directly links on the sheet.Read-write to storer is carried out in two steps: be operation to which storer by read-write memory order notice hardware at first, preserve start address and data length then to address register; Then by the GO order, if the order of previous step is a write operation, what closely follow after the go is exactly data to be written, if the order of previous step is read operation, will export corresponding data after the go on the tdo bus.Read operation according to the sequential of start address and data length structure memory read, in the temporary inner register of the data of reading in, cooperates tck clock output data on the tdo bus as shown in Figure 6 then.Write operation becomes the data integration on the tdi 16 to be put in the internal register as shown in Figure 5, according to the sequential of writing of start address and data length structure storer, in writing data into memory.
As shown in Figure 2, according to the Ack signal of CPU output, and the End of control register, the Sfr_change signal is controlled the operation of interrupt service routine.In interrupt service routine, realized read-write operation to the SFR register.Because the SFR register of CPU inside is numerous, and location distribution is very messy, if still adopt the method for read-write memory to read and write the SFR register, need on the sheet emulation module and each SFR register all direct-connected, design can be very complicated.Therefore we are by adding the function that instruction realizes reading and writing SFR in interrupt service routine.Successively the value of SFR register is moved on in inner one section JRAM space of warding off in addition by the mov instruction, and then, use the method for memory read that data are passed to debugger by the JTAG mouth.By the register order that consults with software, correctly show the value of all registers.If change SFR register is put into the address of the register that will change and content in the inner JRAM space by the memory write method, the zone bit of hardware change simultaneously Sfr_change shows that the value of SFR register changes.Interrupt service routine is read address and the content that JRAM obtains register to be changed after inquiring this zone bit, carries out relevant register and revises.Enable END zone bit notice interrupt service routine afterwards again and withdraw from interruption, the flow process of interrupt service routine such as Fig. 7.In addition, interrupt service routine and program code are two ROM storage spaces.Have no progeny in entering, processor is got finger from the IROM of interrupt service routine, withdraw from interrupt service routine after, program is got finger from program code (PROM).The purpose of Shi Xianing is because this interruption is not open to the user like this, belongs to debugging and interrupts.So should not take user's code space, make mistakes in order to avoid lead to divergence.
Emulation module on the sheet of realizing according to such scheme, and debugger, CPU has connected the furnishing merit, and working stability and speed are very fast.The time of the data of actual test transmission 1 megabyte is less than 1s.For 16 of this project team CPU checking and users provide good debug platform.
Claims (6)
1. the adjustment method of a flush bonding processor, it is characterized in that emulation module is as the interface between debug host and the processor on the sheet, emulation module and debug host are passed through TCK, TDI[3:0], TDO[3:0], TMS, the high-speed JTAG interface of TRST links to each other, emulation module and processor are realized debugging by the mode of interruption and reset signal, the register of on sheet, setting up terminal server to read and write in the emulation module, emulation module directly links to each other with all storeies on the sheet, supports the direct read operation to external memory storage.
2. the adjustment method of a kind of flush bonding processor as claimed in claim 1 is characterized in that described TDI, TDO are four bit serial data transmission.
3. the adjustment method of a kind of flush bonding processor as claimed in claim 1, it is characterized in that interrupt service routine and program code are two ROM storage spaces, have no progeny in entering, processor is got finger from the IROM of interrupt service routine, after withdrawing from interrupt service routine, program is got finger from program code PROM.
4. the adjustment method of a kind of flush bonding processor as claimed in claim 1 is characterized in that the mutual state of register understanding that emulation module can be read and write by interrupt service routine on interrupt service routine and the sheet, cooperates and realizes control.
5. the adjustment method of a kind of flush bonding processor as claimed in claim 1, it is characterized in that in interrupt service routine, mode by instruction is put into the value of SFR register in the inner block RAM of warding off in addition, is the data among the RAM that the value of SFR register is read up by the JTAG mouth again; Revise the SFR register value and the address of the register of needs modification are put among the above-mentioned RAM, the interrupt service routine reading also carries out corresponding modification.
6. the adjustment method of a kind of flush bonding processor as claimed in claim 1, it is characterized in that the method that single step realizes, the look-at-me of a clock period length of first clock period output of the second instruction after withdrawing from interrupt service routine realizes just having carried out an instruction.
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| CN102467446A (en) * | 2010-11-11 | 2012-05-23 | 上海华虹集成电路有限责任公司 | Processor chip emulator capable of setting program pointer value |
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| CN101639516B (en) * | 2008-07-31 | 2013-08-28 | 华为技术有限公司 | Data processing method, controller and system |
| CN101751327B (en) * | 2008-12-04 | 2012-04-18 | 北京中电华大电子设计有限责任公司 | Method for tracing embedded processor debugging |
| CN101769988B (en) * | 2008-12-30 | 2013-11-06 | 易视芯科技(北京)有限公司 | Chip debugging method, system and debugging module |
| CN102063367B (en) * | 2010-10-29 | 2013-07-17 | 凌阳科技股份有限公司 | Off-line analysis method and device aiming at computer crash program |
| CN102902624B (en) * | 2012-11-09 | 2015-10-21 | 上海斐讯数据通信技术有限公司 | A kind of software debugging system and method |
| CN110765716A (en) * | 2019-12-06 | 2020-02-07 | 国微集团(深圳)有限公司 | Method and system for checking simulation signal of digital product |
| CN112069020B (en) * | 2020-08-13 | 2023-09-15 | 中国航空无线电电子研究所 | Embedded operating system-based on-board avionics software fault monitoring system |
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Address after: 102209 Beijing, Beiqijia, the future of science and technology in the south area of China electronic network security and information technology industry base C building, Patentee after: Beijing CEC Huada Electronic Design Co., Ltd. Address before: 100015 Beijing city Chaoyang District District No. 1 Gaojiayuan Patentee before: Beijing CEC Huada Electronic Design Co., Ltd. |
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