CN101769988B - Chip debugging method, system and debugging module - Google Patents
Chip debugging method, system and debugging module Download PDFInfo
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- CN101769988B CN101769988B CN 200810246880 CN200810246880A CN101769988B CN 101769988 B CN101769988 B CN 101769988B CN 200810246880 CN200810246880 CN 200810246880 CN 200810246880 A CN200810246880 A CN 200810246880A CN 101769988 B CN101769988 B CN 101769988B
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Abstract
The invention provides a chip debugging method, which comprises the following steps that: a debugging module receives infusion instructions and corresponding infusion points sent by a MCU, and caches infusion data input to the infusion points into a write data register of the debugging module; and when the infusion data cached into the write data register reach a predetermined bit value, the debugging module inputs the cached infusion data to the infusion points, and simultaneously sends a clock enabling signal to a clock module to start the clock of the infusion points during infusing. The MCU realizes the logic control of the debugging module in the chip debugging method by configuring a register of the debugging module through an APB bus, and infusion and capture modes are simple and flexible.
Description
Technical field
The present invention relates to the integrated circuit (IC) design technical field, particularly a kind of chip adjustment method, system and chip debugging module.
Background technology
Along with integrated level and the complexity of chip are more and more higher, the debugging in chip design also becomes increasingly complex, and the purpose of debugging will determine that not only fault has appearred in chip, also will look for out of order reason.Under debugging mode, the designer can pour into data in debugged system in controlled mode, grabs several points data reading from predetermined more afterwards, thereby detects the state of debugged system.But along with improving constantly of chip design level, as popularizing of the technology such as SOC (System on Chip, SOC (system on a chip)), the quantity that point is counted in the filling in debugged system also gets more and more, and the kind of filling with several points also becomes increasingly complex.Because different fillings is counted point and may be needed different transmission modes, debugging module may mate by the clock when filling with several somes normal operation fully in addition.Therefore in the prior art, in order to realize pouring into of data, a plurality of debugging modules can be set in chip count point from different fillings and mate, these debugging modules can take the chip area of preciousness undoubtedly, raise the cost.In addition, a plurality of debugging modules are set also can increase designer's workload, increase the design cycle of chip.
As shown in Figure 1, be the structural drawing of a kind of chip debug circuit in prior art.As can be seen from the figure, debugging module and MCU (Micro Controller Unit, micro-control unit) be connected by APB (Advanced Peripheral BUS, advanced peripheral bus), and directly control debugging module by MCU debugged system is filled with number and grabs number.Debugging module is counted point with a plurality of fillings and is grabbed several points by MUX (Multiplexer, multi-way switch) and is connected.As MCU during to the data register configuration data of debugging module, because clock period of MCU only can configure the data of 8bit, therefore need to carry out buffer memory in debugging module, when after the data that are cached to 32bit in debugging module, the data of this 32bit being circulated in debugged system.Debugged like this system needs four clock period can receive that pours into data, and this and the normal work clock of debugged system do not mate, and not only effect is debugged in impact, but also the workload can increase the designer and debug the time.
Summary of the invention
Purpose of the present invention is intended to solve at least one of above-mentioned technological deficiency, particularly solves the defective that existing chip debugging scheme can't be mated with the normal operation clock of debugged system.
For achieving the above object, one aspect of the present invention proposes a kind of chip adjustment method, comprise the following steps: debugging module receives that micro-control unit MCU sends pours into instruction and corresponding filling is counted a little, and will input that described filling counts point pour into data buffer storage in the write data register of described debugging module; When buffer memory in the write data register described pours into data and reaches predetermined bit value, described debugging module pours into the described filling of data input with buffer memory described and counts in point, simultaneously to clock module tranmitting data register enable signal to open the clock that point is counted in described filling when filling with number.
As an embodiment of said method of the present invention, described predetermined bit value can be 32bit.
As an embodiment of said method of the present invention, described debugging module can be connected by advanced peripheral bus APB bus with described MCU, and information and the described data that pour into that point is counted in described filling send to described debugging module by described MCU by described APB bus.
As an embodiment of said method of the present invention, said method also comprises: thus described debugging module is resolved several points of grabbing of grabbing several instructions and correspondence that the APB bus is obtained described MCU transmission; Described debugging module is grabbed number according to described several points of grabbing of grabbing several instructions and correspondence, simultaneously grab several instructions and produce and read enable signal the data in described storer being read into the read data register in described debugging module according to described, and make the address of described storer add 1; Described debugging module receives the instruction of reading of described MCU transmission, and the data in described read data register are offered described MCU.
As an embodiment of said method of the present invention, said method also comprises: described debugging module is resolved the start address that described APB bus is obtained reading out data from described storer.
As an embodiment of said method of the present invention, said method also comprises: described debugging module is resolved described APB bus and is obtained and grab number cut-off address, in the current address of described storer be described when grabbing number cut-off address described debugging module stop grabbing number.
As an embodiment of said method of the present invention, said method also comprises: described debugging module and a plurality of fillings are counted point and are grabbed several points and be connected.
The present invention also proposes a kind of chip debug system on the other hand, comprise MCU, the debugging module that is connected with described MCU, the debugged system that is connected with described debugging module, and the clock module that clock is provided for described debugging module and described debugged system, in wherein said debugged system, at least one several of filling is connected with described debugging module, described MCU, be used for configuring the event registers of described debugging module to send the instruction of filling number to described debugging module, and indicate the several points of filling, and will pour into the write data register that data deposit described debugging module in; Described debugging module, be used for when write data register buffer memory described pours into data and reach predetermined bit value, write data register buffer memory described poured into the filling that the described event registers of data input indicates counts in point, simultaneously to described clock module tranmitting data register enable signal to open the clock that point is counted in described filling when filling with number.
As an embodiment of said system of the present invention, described predetermined bit value can be 32bit.
As an embodiment of said system of the present invention, described MCU is connected by the APB bus with described debugging module, and described MCU is configured the register in described debugging module by described APB bus.
An embodiment as said system of the present invention, said system also comprise with described debugged system at least one grabs the storer that several points and described debugging module all are connected, in described debugging module and described debugged system described at least one grab several points and also be connected; Described storer is used for preserving the data of grabbing several some crawls from described; Described MCU also is used for grabbing several instructions by the number register of grabbing of the described debugging module of described APB bus configuration with transmission, indicates simultaneously corresponding several points of grabbing; Described debugging module, also be used for described grab that number register indicates described grabbed several points and grab number, simultaneously grab several instructions and produce and read enable signal so that the data in described storer are read in read data register according to described, and make the address of described storer add 1, and receive that described MCU sends read instruction after, the data in described read data register are offered described MCU.
As an embodiment of said system of the present invention, described MCU also is used for configuring the initial address register of described debugging module with the start address to described debugging module indication from described storer reading out data.
As an embodiment of said system of the present invention, described MCU, the cut-off address register that also is used for configuring described debugging module is to indicate described debugging module to stop grab number as described when grabbing number cut-off address in the current address of described storer.
As an embodiment of said system of the present invention, described debugging module is counted point by multi-way switch MUX and described debugged intrasystem a plurality of fillings and is grabbed several points and be connected with a plurality of.
Further aspect of the present invention also proposes a kind of debugging module, comprise event registers, write data register, clock enable signal generation module and fill with the digital-to-analogue piece, described event registers, MCU counts instruction by the filling of described APB bus configuration and corresponding filling is counted a little for preserving; The write data register is used for the described MCU of buffer memory by the data that pour into of described APB bus transmission; Described clock enable signal generation module is used for when write data register buffer memory described pours into data and reach predetermined bit value, produces the clock enable signal to open the clock that point is counted in described filling when the filling number; Described filling digital-to-analogue piece is used for when write data register buffer memory described pours into data and reach predetermined bit value, write data register buffer memory described is poured into data input the indicated described filling of described event registers and count a little.
As an embodiment of the above-mentioned debugging module of the present invention, described predetermined bit value can be 32bit.
An embodiment as the above-mentioned debugging module of the present invention also comprises the APB bus interface that is connected with the APB bus.
An embodiment as the above-mentioned debugging module of the present invention, described debugging module also comprises grabs number register, grabs the digital-to-analogue piece and reads the enable signal generation module, the described number register of grabbing is used for preserving described MCU by several points of grabbing of the several instructions of grabbing of described APB bus configuration and correspondence; The described digital-to-analogue piece of grabbing is used for described grab that number register indicates described grabbed several points and grab number; The described enable signal generation module of reading is used for grabbing several instructions and producing and read enable signal the data of storer are read in read data register according to described, and makes the address of described storer add 1.
As an embodiment of the above-mentioned debugging module of the present invention, described debugging module also comprises initial address register, is used for preserving described MCU by the start address from described storer reading out data of described APB bus configuration.
An embodiment as the above-mentioned debugging module of the present invention, described debugging module also comprises the cut-off address register, end the address for preserving the number of grabbing of described MCU by described APB bus configuration, the described digital-to-analogue piece of grabbing is that described grabbing stops grabbing number when number ends the address in the current address of described storer.
The logic control of debugging module is in the present invention realized by the register of APB bus configuration debugging module by MCU, fills with number and grabs several mode simple and flexible.And the present invention controls clock module by the clock enable signal that debugging module produces, make it fill with the clock of several points in opening debugged system when filling with number, make input clock and debugged system mate fully at the normal operation clock, debugging efficiency not only can be improved, but also chip area can be reduced.In addition, the present invention also can control the number of grabbing of debugging module, not only can select different several points of grabbing, also can select to grasp the data volume of data, and can produce after debugging module is receiving to grab several instructions and read accordingly enable signal, data in storer are read in register in debugging module, thereby offered MCU receiving after MCU reads instruction, further improve debugging efficiency.
The aspect that the present invention adds and advantage part in the following description provide, and part will become obviously from the following description, or recognize by practice of the present invention.
Description of drawings
Above-mentioned and/or the additional aspect of the present invention and advantage will become from the following description of the accompanying drawings of embodiments and obviously and easily understand, wherein:
Fig. 1 is the structural drawing of a kind of chip debug circuit in prior art;
Fig. 2 is the schematic diagram of APB bus timing;
Fig. 3 is the chip adjustment method process flow diagram of one embodiment of the invention;
Sequential chart when Fig. 4 is debugging module filling number;
Fig. 5 is that debugging module is grabbed the sequential chart when several;
Fig. 6 is the chip debug system structural drawing of one embodiment of the invention;
Fig. 7 is one embodiment of the invention debugging module structural drawing.
Embodiment
The below describes embodiments of the invention in detail, and the example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or the element with identical or similar functions from start to finish.Be exemplary below by the embodiment that is described with reference to the drawings, only be used for explaining the present invention, and can not be interpreted as limitation of the present invention.
The present invention mainly is, by the clock enable signal that debugging module produces, clock module is controlled, make it fill with the clock of several points in only opening debugged system when filling with number, make input clock and debugged system in normal operation clock coupling, debugging efficiency not only can be improved, but also chip area can be reduced.
In addition, as a preferred embodiment of the present invention, grab when several by debugging module at MCU, debugging module is read enable signal accordingly receiving can produce after grabbing several instructions, data in storer are read in register in debugging module, thereby offer MCU receiving after MCU reads instruction, further improved debugging efficiency.Further, need not in the present invention existing MCU is made a change, all logic controls to debugging module all can be realized by the register of APB bus configuration debugging module by MCU, fill with number and grab several mode simple and flexible.
In order clearer understanding to be arranged to the present invention, below at first the APB bus in the present invention is simply introduced, but need to prove that it is only in order to make the present invention clearer that following embodiment of the present invention describes as an example of the APB bus example, and do not mean that the present invention only can realize by the APB bus, also can be connected by other buses between MCU and debugging module, for example I
2C bus etc.; when only using other buses to be connected, the interface of its bus and order etc. can change; but these variations there is no impact to application of the present invention; those skilled in the art can be combined with thought of the present invention according to the distinctive interface of these other buses or order the present invention is applied to other interfaces, so within the variation of these buses all should be included in protection scope of the present invention.
As shown in table 1 below, be the interface schematic diagram of APB bus interface on debugging module.MCU controls debugging module by the APB bus, the register of configuration debugging module, and simultaneously debugging module is resolved the information such as the instruction that obtains MCU and data by resolving the APB bus.As shown in Figure 2, be the schematic diagram of APB bus timing.
Table 1
| Paddr (address) | 8 | I |
| Pwdata (writing data) | 8 | I |
| Prdata (read data) | 8 | O |
| Psel (selection) | 1 | I |
| Pwrite (write signal) | 1 | I |
| Penable (enable signal) | 1 | I |
Debugging module not only has above-mentioned interface in the present invention, also needs to have the described interface of following table 2, shown in its corresponding function also sees table.
Table 2
| clkena | 1 | O | The clock enable signal, make pour into data the time control clock module |
| demodulate_xxx_data_strb | 1 | O | Pour into the data useful signal that certain fills with several points, resolved by the APB bus and get |
| demodulate_xxx_data | N | O | Pour into the data that certain fills with several points, sent into by the APB bus and fill with several points |
| xxx_xxx_data_strb | 1 | I | Grasp the useful signal that certain grabs several somes data |
| xxx_xxx_data | N | I | Grasp the data that certain grabs several points, read by the APB bus |
Below will specifically describe as an example of the APB bus example, but what need explanation again is to use the APB bus only to be one embodiment of the present of invention, the present invention also can use other buses.
As shown in Figure 3, chip adjustment method process flow diagram for one embodiment of the invention, comprise in this embodiment debugging module, coupled MCU and debugged system, and the clock module that clock is provided for debugging module and debugged system, debugging module is grabbed several points with the several points of at least one filling in debugged system with at least one by MUX and is connected, and wherein debugging module is connected with MCU by the APB bus.In order clearer understanding to be arranged to this embodiment, can be simultaneously with reference to Fig. 4 and Fig. 5, Fig. 4 is the sequential chart of debugging module when filling with number, Fig. 5 is that debugging module is grabbed the sequential chart when several.This embodiment comprises the following steps:
Step S301, MCU sends to debugging module the filling that pours into instruction and correspondence and counts a little.Wherein, in this embodiment, MCU controls debugging module by the APB bus, more specifically, MCU is configured the register in debugging module by the APB bus, for example, the event in debugging module (case) register is configured, this event registers represents the event that will debug, fills with number indication and corresponding filling and counts a little.
Step S302, MCU will pour into data and write write data register (data_write) in debugging module.
Step S303, when the pouring into data and reach predetermined bit value of buffer memory in write data register, debugging module is counted the filling corresponding to data input that pour into of buffer memory in point, simultaneously to clock module tranmitting data register enable signal just to open the clock of the several points of filling when filling with number.Particularly, suppose that MCU once only can configure the data of 8bit, and predetermined bit value be 32bit, debugging module need to wait until that the data that pour into of buffer memory reach that when being scheduled to the bit value, ability pours into to debugged system.Predetermined bit value described herein determined by debugged system, and for example, debugged system needs 32bit, should predetermined bit value can be made as 32bit, if debugged system needs 16bit, should predetermined bit value can be made as 16bit.Simultaneously with reference to figure 4, debugging module produces the useful signal (apb_din_strb) that pours into data, and the data of buffer memory are poured into data (apb_din) as what count to the corresponding filling of debugged system that point pours into.Because MCU once only can configure the data of 8bit, therefore need 4 cycles could produce one and pour into data (apb_din), in order to be complementary with debugged system normal operation clock, in the present invention, debugging module also needs to produce clock enable signal (clkena), makes clock module only open the clock that point is counted in this filling when filling with number.Therefore when not filling with number, it is idle that point is counted in this filling like this, and the data that pour into of its input are with the clock coupling of its normal operation for filling with several points.Wherein, need to prove, debugging module can be resolved in several ways and be produced the useful signal (apb_din_strb) that pours into data, particularly, for example, APB bus timing shown in Figure 2, debugging module just can learn by the parsing of pwrite, psel, three control signals of penable and paddr address wire whether MCU is joining number to write data register, and hence one can see that when can join and enough required pour into data (namely reaching predetermined bit value), thereby parsing obtains pouring into the useful signal of data.
As the preferred embodiments of the present invention, debugging module of the present invention is counted function except having above-mentioned filling, also has the several functions of grabbing of simple and flexible.Debugging module can go out to grab accordingly several instructions and grab several points etc. according to the Command Line Parsing that MCU exchanges the die trial block register in the present invention, like this for MCU or as prior art still just at configuration register, and debugging module can deposit corresponding data of grabbing several points in the read data register (data_read) of debugging module according to the several instructions of grabbing that are resolved in the present invention, thereby MCU can directly take the data in this read data register away, further improve debugging efficiency, specifically see following steps for details.
Step S304, debugging module resolve several points of grabbing of grabbing several instructions and correspondence that the APB bus sends to obtain MCU.Particularly, the number of grabbing in MCU configuration debugging module begins register (start), and the indication debugging module begins to grab to count and indicate grabs several points accordingly.
Step S305, debugging module is grabbed number according to several points of grabbing of grabbing several instructions and correspondence, simultaneously grab several instructions and produce and read enable signal the data in storer being read in the read data register in debugging module according to described, and make the address of described storer add 1.Particularly, with reference to shown in Figure 5, suppose that the clock of APB bus is 30MHz in this embodiment, the clock of debugging module is 60MHz, debugging module can produce according to pwrite, psel, three control signals of penable and paddr address wire and read enable signal (apb_read), more specifically, for example pwrite=0, psel=1, penable=1, and paddr produces when being the address of read data register (data_read) and reads enable signal (apb_read).Equally; debugging module also can be resolved in several ways and be obtained reading enable signal (apb_read) in this embodiment; and if the bus between debugging module and MCU is different; analysis mode also can change, and what need explanation again is these variations all should be included in protection scope of the present invention within not breaking away from above-mentioned thought range of the present invention within.
Step S306, debugging module offers MCU receiving the instruction of reading of MCU transmission with the data in read data register, and MCU just can in time obtain it and grab several results like this.In upper example as shown in fig. 5, the enable signal (apb_read) of reading in debugging module is two cycles, when first cycle, debugging module is read into the data of storing in storer in read data register (data_read) in debugging module, and makes the address of storer add 1; Can just the data that just deposit read data register in be read away at second period MCU.
As a kind of optimal way of the present invention, MCU also can send to debugging module with grabbing several addresses of ending, and debugging module stops grabbing number in the current address of storer for grabbing when number ends the address.Particularly, can indicate in several ways debugging module to stop grabbing number, as the address size stored in storer of indication, surpass certain address size post debugging module from the storer current address and stop grabbing number.In the present invention, can realize by the cut-off address register (length) that MCU configures in debugging module.
On the basis of above embodiment, as another optimal way of the present invention, MCU also can send to debugging module with the several start addresses of grabbing in storer, and this grabs the address that several start addresses begin for from the storer sense data time.Particularly, can realize by the initial address register (addr_start) that MCU configures in debugging module.
Can find out from above-mentioned explanation, MCU can be to grabbing the flexible configuration of number beginning register (start), cut-off address register (length) and initial address register (addr_start), thereby realize grabbing more flexibly several modes, make the commissioning staff can obtain according to the demand of oneself data of oneself wanting fully.
As shown in Figure 6, chip debug system structural drawing for one embodiment of the invention, comprise MCU100, the debugging module 200 that is connected with MCU100, the debugged system 300 that is connected with debugging module 200, and the clock module 400 that clock is provided for debugging module 200 and debugged system 300, wherein there is at least one to fill with several points in debugged system 300 and grabs at several with at least one and be connected with debugging module 200.MCU100 is used for the event registers of configuration debugging module 200 and fills with the number instruction to send to debugging module 200, and indicates the several points of filling, and will pour into the write data register that data deposit debugging module 200 in.Debugging module 200 is used for when the pouring into data and reach predetermined bit value of write data register buffer memory, the filling that data incoming event register indicates that pours into of write data register buffer memory is counted in point, simultaneously to clock module 400 tranmitting data register enable signals to open the clock of filling with several points when filling with number.Wherein, predetermined bit value can arrange according to the needs of debugged system, for example can be 32bit.
As one embodiment of the present of invention, MCU100 is connected by the APB bus with debugging module 200, and MCU is configured the register in debugging module by the APB bus.Equally, MCU100 also can be connected by other buses with debugging module 200, contains but other buses also should be protection domain of the present invention.
As one embodiment of the present of invention, said system also comprise with debugged system 300 in grab the storer 500 that several points and debugging module 200 all are connected.Storer 500 is used for preserving from grabbing the data of several some crawls.MCU100 also is used for grabbing several instructions by the number register of grabbing of APB bus configuration debugging module 200 with transmission, indicates simultaneously corresponding several points of grabbing.Debugging module 200 also is used for grabbing number to grabbing several points of grabbing that number register indicates, read enable signal so that the data in storer are read in read data register according to grabbing several instructions generations simultaneously, and make the address of storer 500 add 1, and receive that MCU100 sends read instruction after, the data in read data register are offered MCU100.
As one embodiment of the present of invention, MCU100 also is used for initial address register and/or the cut-off address register of configuration debugging module 200, and initial address register is used for the start address to debugging module 200 indications from storer 500 reading out datas; Debugging module 200 stops grabbing number in the current address of storer 500 for grabbing when number ends the address.
As one embodiment of the present of invention, debugging module 200 is counted point by MUX and debugged intrasystem a plurality of fillings and is grabbed several points and be connected with a plurality of.
Wherein, as shown in Figure 7, be one embodiment of the invention debugging module structural drawing, this debugging module 200 comprises event registers 211, write data register 212, clock enable signal generation module 220 and fills with digital-to-analogue piece 230.MCU100 counts instruction by the filling of APB bus configuration to event registers 211 and corresponding filling is counted a little for preserving.Write data register 212 is used for buffer memory MCU100 by the data that pour into of APB bus transmission.Clock enable signal generation module 220 is used for producing the clock enable signal to open the clock of the several points of filling when filling with number when the pouring into data and reach predetermined bit value of write data register 212 buffer memorys.Filling with digital-to-analogue piece 230 is used for when the pouring into data and reach predetermined bit value of write data register 212 buffer memorys, the data incoming event register 211 indicated fillings that pour into of write data register 212 buffer memorys being counted a little.Wherein, debugging module 200 also comprises the APB bus interface 240 that is connected with the APB bus.
As a preferred embodiment of the invention, debugging module 200 also comprises grabs number register 213 and read data register 214 and grabs digital-to-analogue piece 250, reads enable signal generation module 260.Grab number register 213 and be used for preserving MCU100 by several points of grabbing of the several instructions of grabbing of APB bus configuration and correspondence.Grabbing digital-to-analogue piece 250 is used for grabbing number to grabbing several points of grabbing that number register 213 indicates.Read enable signal generation module 260 and be used for producing and reading enable signal the data of storer 500 are read in read data register 214 according to grabbing several instructions, and make the address of storer 500 add 1.
As the preferred embodiments of the present invention, debugging module 200 also comprises initial address register 215 and/or cut-off address register 216.Initial address register 215 is used for preserving MCU100 by the start address from storer 500 reading out datas of APB bus configuration.Cut-off address register 216 ends the address for preserving the number of grabbing of MCU100 by the APB bus configuration, grabs digital-to-analogue piece 250 and stops grabbing number in the current address of storer 500 when number ends the address for grabbing.
The logic control of debugging module is in the present invention realized by the register of APB bus configuration debugging module by MCU, fills with number and grabs several mode simple and flexible.And the present invention controls clock module by the clock enable signal that debugging module produces, make it fill with the clock of several points in opening debugged system when filling with number, make input clock and debugged system mate fully at the normal operation clock, debugging efficiency not only can be improved, but also chip area can be reduced.In addition, the present invention also can control the number of grabbing of debugging module, not only can select different several points of grabbing, also can select to grasp the data volume of data, and can produce after debugging module is receiving to grab several instructions and read accordingly enable signal, data in storer are read in register in debugging module, thereby offered MCU receiving after MCU reads instruction, further improve debugging efficiency.
Although illustrated and described embodiments of the invention, for the ordinary skill in the art, be appreciated that without departing from the principles and spirit of the present invention and can carry out multiple variation, modification, replacement and modification to these embodiment, scope of the present invention is by claims and be equal to and limit.
Claims (20)
1. a chip adjustment method, is characterized in that, comprises the following steps:
Debugging module receives that micro-control unit MCU sends pours into instruction and corresponding filling is counted a little, and will input that described filling counts point pour into data buffer storage in the write data register of described debugging module;
When buffer memory in the write data register described pours into data and reaches predetermined bit value, described debugging module pours into the described filling of data input with buffer memory described and counts in point, simultaneously to clock module tranmitting data register enable signal to open the clock that point is counted in described filling when filling with number, wherein, described predetermined bit value is determined by debugged system.
2. chip adjustment method as claimed in claim 1, is characterized in that, described predetermined bit value is 32bit.
3. chip adjustment method as claimed in claim 1, it is characterized in that, described debugging module is connected by advanced peripheral bus APB bus with described MCU, and information and the described data that pour into that point is counted in described filling send to described debugging module by described MCU by described APB bus.
4. chip adjustment method as claimed in claim 3, is characterized in that, also comprises:
Thereby described debugging module is resolved the APB bus and is obtained several points of grabbing of grabbing several instructions and correspondence that described MCU sends;
Described debugging module is grabbed number according to described several points of grabbing of grabbing several instructions and correspondence, simultaneously grab several instructions and produce and read enable signal the data in storer being read into the read data register in described debugging module according to described, and make the address of described storer add 1;
Described debugging module receives the instruction of reading of described MCU transmission, and the data in described read data register are offered described MCU.
5. chip adjustment method as claimed in claim 4, is characterized in that, also comprises:
Described debugging module is resolved the start address that described APB bus is obtained reading out data from described storer.
6. chip adjustment method as claimed in claim 4, is characterized in that, also comprises:
Described debugging module is resolved described APB bus and is obtained and grab number cut-off address, in the current address of described storer be described when grabbing number cut-off address described debugging module stop grabbing number.
7. chip adjustment method as claimed in claim 4, is characterized in that, also comprises: described debugging module and a plurality of fillings are counted point and are grabbed several points and be connected.
8. chip debug system, it is characterized in that, comprise micro-control unit MCU, the debugging module that is connected with described MCU, the debugged system that is connected with described debugging module, and the clock module that clock is provided for described debugging module and described debugged system, in wherein said debugged system, at least one is filled with at several and is connected with described debugging module
Described MCU fills with the number instruction for the event registers that configures described debugging module to send to described debugging module, and indicates the several points of filling, and will pour into the write data register that data deposit described debugging module in;
Described debugging module, be used for when write data register buffer memory described pours into data and reach predetermined bit value, write data register buffer memory described poured into the filling that the described event registers of data input indicates counts a little, simultaneously to described clock module tranmitting data register enable signal to open the clock that point is counted in described filling when filling with number, wherein, described predetermined bit value is determined by debugged system.
9. chip debug system as claimed in claim 8, is characterized in that, described predetermined bit value is 32bit.
10. chip debug system as claimed in claim 8, is characterized in that, described MCU is connected by the APB bus with described debugging module, and described MCU is configured the register in described debugging module by described APB bus.
11. chip debug system as claimed in claim 10, it is characterized in that, also comprise with described debugged system at least one grabs the storer that several points and described debugging module all are connected, in described debugging module and described debugged system described at least one grab several points and also be connected;
Described storer is used for preserving the data of grabbing several some crawls from described;
Described MCU also is used for grabbing several instructions by the number register of grabbing of the described debugging module of described APB bus configuration with transmission, indicates simultaneously corresponding several points of grabbing;
Described debugging module, also be used for described grab that number register indicates described grabbed several points and grab number, simultaneously grab several instructions and produce and read enable signal so that the data in described storer are read in read data register according to described, and make the address of described storer add 1, and receive that described MCU sends read instruction after, the data in described read data register are offered described MCU.
12. chip debug system as claimed in claim 11 is characterized in that, described MCU also is used for configuring the initial address register of described debugging module with the start address to described debugging module indication from described storer reading out data.
13. chip debug system as claimed in claim 11, it is characterized in that, described MCU, the cut-off address register that also is used for configuring described debugging module is to indicate described debugging module to stop grab number as described when grabbing number cut-off address in the current address of described storer.
14. chip debug system as claimed in claim 8 is characterized in that, described debugging module is counted point by multi-way switch MUX and described debugged intrasystem a plurality of fillings and is grabbed several points and be connected with a plurality of.
15. a debugging apparatus is characterized in that, comprises event registers, write data register, clock enable signal generation module and fills with the digital-to-analogue piece,
Described event registers is counted the filling of instruction and correspondence and is counted a little for the filling of preserving the MCU configuration;
The write data register is for the data that pour into of the described MCU transmission of buffer memory;
Described clock enable signal generation module, be used for when write data register buffer memory described pours into data and reach predetermined bit value, produce the clock enable signal to open the clock that point is counted in described filling when filling with number, wherein, described predetermined bit value is determined by debugged system;
Described filling digital-to-analogue piece is used for when write data register buffer memory described pours into data and reach predetermined bit value, write data register buffer memory described is poured into data input the indicated described filling of described event registers and count a little.
16. debugging apparatus as claimed in claim 15 is characterized in that, described predetermined bit value is 32bit.
17. debugging apparatus as claimed in claim 15 is characterized in that, also comprises the APB bus interface that is connected with the APB bus.
18. debugging apparatus as claimed in claim 17 is characterized in that, also comprises grabbing number register, grab the digital-to-analogue piece and reading the enable signal generation module,
The described number register of grabbing is used for preserving described MCU by several points of grabbing of the several instructions of grabbing of described APB bus configuration and correspondence;
The described digital-to-analogue piece of grabbing is used for described grab that number register indicates described grabbed several points and grab number;
The described enable signal generation module of reading is used for grabbing several instructions and producing and read enable signal the data of storer are read in read data register according to described, and makes the address of described storer add 1.
19. debugging apparatus as claimed in claim 18 is characterized in that, also comprises initial address register, is used for preserving described MCU by the start address from described storer reading out data of described APB bus configuration.
20. debugging apparatus as claimed in claim 18, it is characterized in that, also comprise the cut-off address register, end the address for preserving the number of grabbing of described MCU by described APB bus configuration, the described digital-to-analogue piece of grabbing is that described grabbing stops grabbing number when number ends the address in the current address of described storer.
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| CN103246584B (en) * | 2012-02-14 | 2017-02-22 | 苏州澜起微电子科技有限公司 | Chip structure of system-on-chip and method for storing debug information |
| CN103744009B (en) * | 2013-12-17 | 2016-12-07 | 记忆科技(深圳)有限公司 | A kind of serial transmission chip detecting method, system and integrated chip |
| CN105808396A (en) * | 2016-03-04 | 2016-07-27 | 浙江大华技术股份有限公司 | Chip debugging device, debugging method and SOC (System of Chip) chip system |
| CN109408433B (en) * | 2018-10-08 | 2021-05-11 | 北京理工大学 | Interface device suitable for debugging of application specific integrated circuit and working method |
| CN112559437A (en) * | 2019-09-25 | 2021-03-26 | 阿里巴巴集团控股有限公司 | Debugging unit and processor |
| CN113489415B (en) * | 2021-07-26 | 2023-04-07 | 深圳市航顺芯片技术研发有限公司 | Motor debugging method, device, module, motor and motor debugging system |
| CN113868070B (en) * | 2021-09-23 | 2023-08-25 | 山东云海国创云计算装备产业创新中心有限公司 | SD card controller debugging method, system, storage medium and device |
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